drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/os.h>
  26 #include <core/class.h>
  27
  28 #include <subdev/bios.h>
  29 #include <subdev/bios/dcb.h>
  30 #include <subdev/bios/dp.h>
  31 #include <subdev/bios/init.h>
  32
  33 #include "nv50.h"
  34
  35 static inline u32
  36 nvd0_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
  37 {
  38         static const u8 nvd0[] = { 16, 8, 0, 24 };
  39         return nvd0[lane];
  40 }
  41
  42 int
  43 nvd0_sor_dp_train(struct nv50_disp_priv *priv, int or, int link,
  44                   u16 type, u16 mask, u32 data, struct dcb_output *info)
  45 {
  46         const u32 loff = (or * 0x800) + (link * 0x80);
  47         const u32 patt = (data & NV94_DISP_SOR_DP_TRAIN_PATTERN);
  48         nv_mask(priv, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * patt);
  49         return 0;
  50 }
  51
  52 int
  53 nvd0_sor_dp_lnkctl(struct nv50_disp_priv *priv, int or, int link, int head,
  54                    u16 type, u16 mask, u32 data, struct dcb_output *dcbo)
  55 {
  56         struct nouveau_bios *bios = nouveau_bios(priv);
  57         const u32 loff = (or * 0x800) + (link * 0x80);
  58         const u32 soff = (or * 0x800);
  59         const u8  link_bw = (data & NV94_DISP_SOR_DP_LNKCTL_WIDTH) >> 8;
  60         const u8  link_nr = (data & NV94_DISP_SOR_DP_LNKCTL_COUNT);
  61         u32 dpctrl = 0x00000000;
  62         u32 clksor = 0x00000000;
  63         u32 outp, lane = 0;
  64         u8  ver, hdr, cnt, len;
  65         struct nvbios_dpout info;
  66         int i;
  67
  68         outp = nvbios_dpout_match(bios, type, mask, &ver, &hdr, &cnt, &len, &info);
  69         if (outp && info.lnkcmp) {
  70                 struct nvbios_init init = {
  71                         .subdev = nv_subdev(priv),
  72                         .bios = bios,
  73                         .offset = 0x0000,
  74                         .outp = dcbo,
  75                         .crtc = head,
  76                         .execute = 1,
  77                 };
  78
  79                 while (nv_ro08(bios, info.lnkcmp) < link_bw)
  80                         info.lnkcmp += 3;
  81                 init.offset = nv_ro16(bios, info.lnkcmp + 1);
  82
  83                 nvbios_exec(&init);
  84         }
  85
  86         clksor |= link_bw << 18;
  87         dpctrl |= ((1 << link_nr) - 1) << 16;
  88         if (data & NV94_DISP_SOR_DP_LNKCTL_FRAME_ENH)
  89                 dpctrl |= 0x00004000;
  90
  91         for (i = 0; i < link_nr; i++)
  92                 lane |= 1 << (nvd0_sor_dp_lane_map(priv, i) >> 3);
  93
  94         nv_mask(priv, 0x612300 + soff, 0x007c0000, clksor);
  95         nv_mask(priv, 0x61c10c + loff, 0x001f4000, dpctrl);
  96         nv_mask(priv, 0x61c130 + loff, 0x0000000f, lane);
  97         return 0;
  98 }
  99
 100 int
 101 nvd0_sor_dp_drvctl(struct nv50_disp_priv *priv, int or, int link, int lane,
 102                    u16 type, u16 mask, u32 data, struct dcb_output *dcbo)
 103 {
 104         struct nouveau_bios *bios = nouveau_bios(priv);
 105         const u32 loff = (or * 0x800) + (link * 0x80);
 106         const u8 swing = (data & NV94_DISP_SOR_DP_DRVCTL_VS) >> 8;
 107         const u8 preem = (data & NV94_DISP_SOR_DP_DRVCTL_PE);
 108         u32 addr, shift = nvd0_sor_dp_lane_map(priv, lane);
 109         u8  ver, hdr, cnt, len;
 110         struct nvbios_dpout outp;
 111         struct nvbios_dpcfg ocfg;
 112
 113         addr = nvbios_dpout_match(bios, type, mask, &ver, &hdr, &cnt, &len, &outp);
 114         if (!addr)
 115                 return -ENODEV;
 116
 117         addr = nvbios_dpcfg_match(bios, addr, 0, swing, preem, &ver, &hdr, &cnt, &len, &ocfg);
 118         if (!addr)
 119                 return -EINVAL;
 120
 121         nv_mask(priv, 0x61c118 + loff, 0x000000ff << shift, ocfg.drv << shift);
 122         nv_mask(priv, 0x61c120 + loff, 0x000000ff << shift, ocfg.pre << shift);
 123         nv_mask(priv, 0x61c130 + loff, 0x0000ff00, ocfg.unk << 8);
 124         nv_mask(priv, 0x61c13c + loff, 0x00000000, 0x00000000);
 125         return 0;
 126 }