drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/gpuobj.h>
  26
  27 #include <subdev/fb.h>
  28 #include <subdev/vm/nv04.h>
  29
  30 #include <engine/dmaobj.h>
  31
  32 struct nv04_dmaeng_priv {
  33         struct nouveau_dmaeng base;
  34 };
  35
  36 struct nv04_dmaobj_priv {
  37         struct nouveau_dmaobj base;
  38 };
  39
  40 static int
  41 nv04_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
  42                  struct nouveau_object *parent,
  43                  struct nouveau_dmaobj *dmaobj,
  44                  struct nouveau_gpuobj **pgpuobj)
  45 {
  46         struct nouveau_gpuobj *gpuobj;
  47         u32 flags0 = nv_mclass(dmaobj);
  48         u32 flags2 = 0x00000000;
  49         u32 offset = (dmaobj->start & 0xfffff000);
  50         u32 adjust = (dmaobj->start & 0x00000fff);
  51         u32 length = dmaobj->limit - dmaobj->start;
  52         int ret;
  53
  54         if (dmaobj->target == NV_MEM_TARGET_VM) {
  55                 gpuobj = nv04_vmmgr(dmaeng)->vm->pgt[0].obj[0];
  56                 if (dmaobj->start == 0)
  57                         return nouveau_gpuobj_dup(parent, gpuobj, pgpuobj);
  58
  59                 offset  = nv_ro32(gpuobj, 8 + (offset >> 10));
  60                 offset &= 0xfffff000;
  61                 dmaobj->target = NV_MEM_TARGET_PCI;
  62                 dmaobj->access = NV_MEM_ACCESS_RW;
  63         }
  64
  65         switch (dmaobj->target) {
  66         case NV_MEM_TARGET_VRAM:
  67                 flags0 |= 0x00003000;
  68                 break;
  69         case NV_MEM_TARGET_PCI:
  70                 flags0 |= 0x00023000;
  71                 break;
  72         case NV_MEM_TARGET_PCI_NOSNOOP:
  73                 flags0 |= 0x00033000;
  74                 break;
  75         default:
  76                 return -EINVAL;
  77         }
  78
  79         switch (dmaobj->access) {
  80         case NV_MEM_ACCESS_RO:
  81                 flags0 |= 0x00004000;
  82                 break;
  83         case NV_MEM_ACCESS_WO:
  84                 flags0 |= 0x00008000;
  85         case NV_MEM_ACCESS_RW:
  86                 flags2 |= 0x00000002;
  87                 break;
  88         default:
  89                 return -EINVAL;
  90         }
  91
  92         ret = nouveau_gpuobj_new(parent, parent, 16, 16, 0, &gpuobj);
  93         *pgpuobj = gpuobj;
  94         if (ret == 0) {
  95                 nv_wo32(*pgpuobj, 0x00, flags0 | (adjust << 20));
  96                 nv_wo32(*pgpuobj, 0x04, length);
  97                 nv_wo32(*pgpuobj, 0x08, flags2 | offset);
  98                 nv_wo32(*pgpuobj, 0x0c, flags2 | offset);
  99         }
 100
 101         return ret;
 102 }
 103
 104 static int
 105 nv04_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 106                  struct nouveau_oclass *oclass, void *data, u32 size,
 107                  struct nouveau_object **pobject)
 108 {
 109         struct nouveau_dmaeng *dmaeng = (void *)engine;
 110         struct nv04_dmaobj_priv *dmaobj;
 111         struct nouveau_gpuobj *gpuobj;
 112         int ret;
 113
 114         ret = nouveau_dmaobj_create(parent, engine, oclass,
 115                                     data, size, &dmaobj);
 116         *pobject = nv_object(dmaobj);
 117         if (ret)
 118                 return ret;
 119
 120         switch (nv_mclass(parent)) {
 121         case 0x006e:
 122                 ret = dmaeng->bind(dmaeng, *pobject, &dmaobj->base, &gpuobj);
 123                 nouveau_object_ref(NULL, pobject);
 124                 *pobject = nv_object(gpuobj);
 125                 break;
 126         default:
 127                 break;
 128         }
 129
 130         return ret;
 131 }
 132
 133 static struct nouveau_ofuncs
 134 nv04_dmaobj_ofuncs = {
 135         .ctor = nv04_dmaobj_ctor,
 136         .dtor = _nouveau_dmaobj_dtor,
 137         .init = _nouveau_dmaobj_init,
 138         .fini = _nouveau_dmaobj_fini,
 139 };
 140
 141 static struct nouveau_oclass
 142 nv04_dmaobj_sclass[] = {
 143         { 0x0002, &nv04_dmaobj_ofuncs },
 144         { 0x0003, &nv04_dmaobj_ofuncs },
 145         { 0x003d, &nv04_dmaobj_ofuncs },
 146         {}
 147 };
 148
 149 static int
 150 nv04_dmaeng_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 151                  struct nouveau_oclass *oclass, void *data, u32 size,
 152                  struct nouveau_object **pobject)
 153 {
 154         struct nv04_dmaeng_priv *priv;
 155         int ret;
 156
 157         ret = nouveau_dmaeng_create(parent, engine, oclass, &priv);
 158         *pobject = nv_object(priv);
 159         if (ret)
 160                 return ret;
 161
 162         priv->base.base.sclass = nv04_dmaobj_sclass;
 163         priv->base.bind = nv04_dmaobj_bind;
 164         return 0;
 165 }
 166
 167 struct nouveau_oclass
 168 nv04_dmaeng_oclass = {
 169         .handle = NV_ENGINE(DMAOBJ, 0x04),
 170         .ofuncs = &(struct nouveau_ofuncs) {
 171                 .ctor = nv04_dmaeng_ctor,
 172                 .dtor = _nouveau_dmaeng_dtor,
 173                 .init = _nouveau_dmaeng_init,
 174                 .fini = _nouveau_dmaeng_fini,
 175         },
 176 };