drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/client.h>
  26 #include <core/gpuobj.h>
  27 #include <core/class.h>
  28 #include <nvif/unpack.h>
  29 #include <nvif/class.h>
  30
  31 #include <subdev/fb.h>
  32
  33 #include "priv.h"
  34
  35 struct nv50_dmaobj_priv {
  36         struct nouveau_dmaobj base;
  37         u32 flags0;
  38         u32 flags5;
  39 };
  40
  41 static int
  42 nv50_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
  43                  struct nouveau_object *parent,
  44                  struct nouveau_gpuobj **pgpuobj)
  45 {
  46         struct nv50_dmaobj_priv *priv = (void *)dmaobj;
  47         int ret;
  48
  49         if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
  50                 switch (nv_mclass(parent->parent)) {
  51                 case NV40_CHANNEL_DMA:
  52                 case NV50_CHANNEL_GPFIFO:
  53                 case G82_CHANNEL_GPFIFO:
  54                 case NV50_DISP_MAST_CLASS:
  55                 case NV84_DISP_MAST_CLASS:
  56                 case NV94_DISP_MAST_CLASS:
  57                 case NVA0_DISP_MAST_CLASS:
  58                 case NVA3_DISP_MAST_CLASS:
  59                 case NV50_DISP_SYNC_CLASS:
  60                 case NV84_DISP_SYNC_CLASS:
  61                 case NV94_DISP_SYNC_CLASS:
  62                 case NVA0_DISP_SYNC_CLASS:
  63                 case NVA3_DISP_SYNC_CLASS:
  64                 case NV50_DISP_OVLY_CLASS:
  65                 case NV84_DISP_OVLY_CLASS:
  66                 case NV94_DISP_OVLY_CLASS:
  67                 case NVA0_DISP_OVLY_CLASS:
  68                 case NVA3_DISP_OVLY_CLASS:
  69                         break;
  70                 default:
  71                         return -EINVAL;
  72                 }
  73         }
  74
  75         ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
  76         if (ret == 0) {
  77                 nv_wo32(*pgpuobj, 0x00, priv->flags0 | nv_mclass(dmaobj));
  78                 nv_wo32(*pgpuobj, 0x04, lower_32_bits(priv->base.limit));
  79                 nv_wo32(*pgpuobj, 0x08, lower_32_bits(priv->base.start));
  80                 nv_wo32(*pgpuobj, 0x0c, upper_32_bits(priv->base.limit) << 24 |
  81                                         upper_32_bits(priv->base.start));
  82                 nv_wo32(*pgpuobj, 0x10, 0x00000000);
  83                 nv_wo32(*pgpuobj, 0x14, priv->flags5);
  84         }
  85
  86         return ret;
  87 }
  88
  89 static int
  90 nv50_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
  91                  struct nouveau_oclass *oclass, void *data, u32 size,
  92                  struct nouveau_object **pobject)
  93 {
  94         struct nouveau_dmaeng *dmaeng = (void *)engine;
  95         union {
  96                 struct nv50_dma_v0 v0;
  97         } *args;
  98         struct nv50_dmaobj_priv *priv;
  99         u32 user, part, comp, kind;
 100         int ret;
 101
 102         ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
 103         *pobject = nv_object(priv);
 104         if (ret)
 105                 return ret;
 106         args = data;
 107
 108         nv_ioctl(parent, "create nv50 dma size %d\n", size);
 109         if (nvif_unpack(args->v0, 0, 0, false)) {
 110                 nv_ioctl(parent, "create nv50 dma vers %d priv %d part %d "
 111                                  "comp %d kind %02x\n", args->v0.version,
 112                          args->v0.priv, args->v0.part, args->v0.comp,
 113                          args->v0.kind);
 114                 user = args->v0.priv;
 115                 part = args->v0.part;
 116                 comp = args->v0.comp;
 117                 kind = args->v0.kind;
 118         } else
 119         if (size == 0) {
 120                 if (priv->base.target != NV_MEM_TARGET_VM) {
 121                         user = NV50_DMA_V0_PRIV_US;
 122                         part = NV50_DMA_V0_PART_256;
 123                         comp = NV50_DMA_V0_COMP_NONE;
 124                         kind = NV50_DMA_V0_KIND_PITCH;
 125                 } else {
 126                         user = NV50_DMA_V0_PRIV_VM;
 127                         part = NV50_DMA_V0_PART_VM;
 128                         comp = NV50_DMA_V0_COMP_VM;
 129                         kind = NV50_DMA_V0_KIND_VM;
 130                 }
 131         } else
 132                 return ret;
 133
 134         if (user > 2 || part > 2 || comp > 3 || kind > 0x7f)
 135                 return -EINVAL;
 136         priv->flags0 = (comp << 29) | (kind << 22) | (user << 20);
 137         priv->flags5 = (part << 16);
 138
 139         switch (priv->base.target) {
 140         case NV_MEM_TARGET_VM:
 141                 priv->flags0 |= 0x00000000;
 142                 break;
 143         case NV_MEM_TARGET_VRAM:
 144                 priv->flags0 |= 0x00010000;
 145                 break;
 146         case NV_MEM_TARGET_PCI:
 147                 priv->flags0 |= 0x00020000;
 148                 break;
 149         case NV_MEM_TARGET_PCI_NOSNOOP:
 150                 priv->flags0 |= 0x00030000;
 151                 break;
 152         default:
 153                 return -EINVAL;
 154         }
 155
 156         switch (priv->base.access) {
 157         case NV_MEM_ACCESS_VM:
 158                 break;
 159         case NV_MEM_ACCESS_RO:
 160                 priv->flags0 |= 0x00040000;
 161                 break;
 162         case NV_MEM_ACCESS_WO:
 163         case NV_MEM_ACCESS_RW:
 164                 priv->flags0 |= 0x00080000;
 165                 break;
 166         default:
 167                 return -EINVAL;
 168         }
 169
 170         return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
 171 }
 172
 173 static struct nouveau_ofuncs
 174 nv50_dmaobj_ofuncs = {
 175         .ctor =  nv50_dmaobj_ctor,
 176         .dtor = _nvkm_dmaobj_dtor,
 177         .init = _nvkm_dmaobj_init,
 178         .fini = _nvkm_dmaobj_fini,
 179 };
 180
 181 static struct nouveau_oclass
 182 nv50_dmaeng_sclass[] = {
 183         { NV_DMA_FROM_MEMORY, &nv50_dmaobj_ofuncs },
 184         { NV_DMA_TO_MEMORY, &nv50_dmaobj_ofuncs },
 185         { NV_DMA_IN_MEMORY, &nv50_dmaobj_ofuncs },
 186         {}
 187 };
 188
 189 struct nouveau_oclass *
 190 nv50_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
 191         .base.handle = NV_ENGINE(DMAOBJ, 0x50),
 192         .base.ofuncs = &(struct nouveau_ofuncs) {
 193                 .ctor = _nvkm_dmaeng_ctor,
 194                 .dtor = _nvkm_dmaeng_dtor,
 195                 .init = _nvkm_dmaeng_init,
 196                 .fini = _nvkm_dmaeng_fini,
 197         },
 198         .sclass = nv50_dmaeng_sclass,
 199         .bind = nv50_dmaobj_bind,
 200 }.base;