2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <core/class.h>
27 #include <core/engctx.h>
28 #include <core/ramht.h>
30 #include <subdev/instmem.h>
31 #include <subdev/instmem/nv04.h>
32 #include <subdev/fb.h>
34 #include <engine/fifo.h>
38 static struct ramfc_desc
40 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT
},
41 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET
},
42 { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT
},
43 { 16, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE
},
44 { 16, 16, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT
},
45 { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_STATE
},
46 { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_FETCH
},
47 { 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_ENGINE
},
48 { 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_PULL1
},
52 /*******************************************************************************
53 * FIFO channel objects
54 ******************************************************************************/
57 nv10_fifo_chan_ctor(struct nouveau_object
*parent
,
58 struct nouveau_object
*engine
,
59 struct nouveau_oclass
*oclass
, void *data
, u32 size
,
60 struct nouveau_object
**pobject
)
62 struct nv04_fifo_priv
*priv
= (void *)engine
;
63 struct nv04_fifo_chan
*chan
;
64 struct nv_channel_dma_class
*args
= data
;
67 if (size
< sizeof(*args
))
70 ret
= nouveau_fifo_channel_create(parent
, engine
, oclass
, 0, 0x800000,
71 0x10000, args
->pushbuf
,
72 (1 << NVDEV_ENGINE_DMAOBJ
) |
73 (1 << NVDEV_ENGINE_SW
) |
74 (1 << NVDEV_ENGINE_GR
), &chan
);
75 *pobject
= nv_object(chan
);
79 nv_parent(chan
)->object_attach
= nv04_fifo_object_attach
;
80 nv_parent(chan
)->object_detach
= nv04_fifo_object_detach
;
81 chan
->ramfc
= chan
->base
.chid
* 32;
83 nv_wo32(priv
->ramfc
, chan
->ramfc
+ 0x00, args
->offset
);
84 nv_wo32(priv
->ramfc
, chan
->ramfc
+ 0x04, args
->offset
);
85 nv_wo32(priv
->ramfc
, chan
->ramfc
+ 0x0c, chan
->base
.pushgpu
->addr
>> 4);
86 nv_wo32(priv
->ramfc
, chan
->ramfc
+ 0x14,
87 NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES
|
88 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES
|
90 NV_PFIFO_CACHE1_BIG_ENDIAN
|
92 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8
);
96 static struct nouveau_ofuncs
98 .ctor
= nv10_fifo_chan_ctor
,
99 .dtor
= nv04_fifo_chan_dtor
,
100 .init
= nv04_fifo_chan_init
,
101 .fini
= nv04_fifo_chan_fini
,
102 .rd32
= _nouveau_fifo_channel_rd32
,
103 .wr32
= _nouveau_fifo_channel_wr32
,
106 static struct nouveau_oclass
107 nv10_fifo_sclass
[] = {
108 { 0x006e, &nv10_fifo_ofuncs
},
112 /*******************************************************************************
113 * FIFO context - basically just the instmem reserved for the channel
114 ******************************************************************************/
116 static struct nouveau_oclass
118 .handle
= NV_ENGCTX(FIFO
, 0x10),
119 .ofuncs
= &(struct nouveau_ofuncs
) {
120 .ctor
= nv04_fifo_context_ctor
,
121 .dtor
= _nouveau_fifo_context_dtor
,
122 .init
= _nouveau_fifo_context_init
,
123 .fini
= _nouveau_fifo_context_fini
,
124 .rd32
= _nouveau_fifo_context_rd32
,
125 .wr32
= _nouveau_fifo_context_wr32
,
129 /*******************************************************************************
131 ******************************************************************************/
134 nv10_fifo_ctor(struct nouveau_object
*parent
, struct nouveau_object
*engine
,
135 struct nouveau_oclass
*oclass
, void *data
, u32 size
,
136 struct nouveau_object
**pobject
)
138 struct nv04_instmem_priv
*imem
= nv04_instmem(parent
);
139 struct nv04_fifo_priv
*priv
;
142 ret
= nouveau_fifo_create(parent
, engine
, oclass
, 0, 31, &priv
);
143 *pobject
= nv_object(priv
);
147 nouveau_ramht_ref(imem
->ramht
, &priv
->ramht
);
148 nouveau_gpuobj_ref(imem
->ramro
, &priv
->ramro
);
149 nouveau_gpuobj_ref(imem
->ramfc
, &priv
->ramfc
);
151 nv_subdev(priv
)->unit
= 0x00000100;
152 nv_subdev(priv
)->intr
= nv04_fifo_intr
;
153 nv_engine(priv
)->cclass
= &nv10_fifo_cclass
;
154 nv_engine(priv
)->sclass
= nv10_fifo_sclass
;
155 priv
->base
.pause
= nv04_fifo_pause
;
156 priv
->base
.start
= nv04_fifo_start
;
157 priv
->ramfc_desc
= nv10_ramfc
;
161 struct nouveau_oclass
163 .handle
= NV_ENGINE(FIFO
, 0x10),
164 .ofuncs
= &(struct nouveau_ofuncs
) {
165 .ctor
= nv10_fifo_ctor
,
166 .dtor
= nv04_fifo_dtor
,
167 .init
= nv04_fifo_init
,
168 .fini
= _nouveau_fifo_fini
,