2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <core/class.h>
27 #include <core/engctx.h>
28 #include <core/ramht.h>
30 #include <subdev/instmem.h>
31 #include <subdev/instmem/nv04.h>
32 #include <subdev/fb.h>
34 #include <engine/fifo.h>
38 static struct ramfc_desc
40 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT
},
41 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET
},
42 { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT
},
43 { 32, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE
},
44 { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT
},
45 { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_STATE
},
46 { 28, 0, 0x18, 0, NV04_PFIFO_CACHE1_DMA_FETCH
},
47 { 2, 28, 0x18, 28, 0x002058 },
48 { 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_ENGINE
},
49 { 32, 0, 0x20, 0, NV04_PFIFO_CACHE1_PULL1
},
50 { 32, 0, 0x24, 0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE
},
51 { 32, 0, 0x28, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP
},
52 { 32, 0, 0x2c, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT
},
53 { 32, 0, 0x30, 0, NV10_PFIFO_CACHE1_SEMAPHORE
},
54 { 32, 0, 0x34, 0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE
},
55 { 32, 0, 0x38, 0, NV40_PFIFO_GRCTX_INSTANCE
},
56 { 17, 0, 0x3c, 0, NV04_PFIFO_DMA_TIMESLICE
},
57 { 32, 0, 0x40, 0, 0x0032e4 },
58 { 32, 0, 0x44, 0, 0x0032e8 },
59 { 32, 0, 0x4c, 0, 0x002088 },
60 { 32, 0, 0x50, 0, 0x003300 },
61 { 32, 0, 0x54, 0, 0x00330c },
65 /*******************************************************************************
66 * FIFO channel objects
67 ******************************************************************************/
70 nv40_fifo_object_attach(struct nouveau_object
*parent
,
71 struct nouveau_object
*object
, u32 handle
)
73 struct nv04_fifo_priv
*priv
= (void *)parent
->engine
;
74 struct nv04_fifo_chan
*chan
= (void *)parent
;
75 u32 context
, chid
= chan
->base
.chid
;
78 if (nv_iclass(object
, NV_GPUOBJ_CLASS
))
79 context
= nv_gpuobj(object
)->addr
>> 4;
81 context
= 0x00000004; /* just non-zero */
83 switch (nv_engidx(object
->engine
)) {
84 case NVDEV_ENGINE_DMAOBJ
:
86 context
|= 0x00000000;
89 context
|= 0x00100000;
91 case NVDEV_ENGINE_MPEG
:
92 context
|= 0x00200000;
98 context
|= chid
<< 23;
100 mutex_lock(&nv_subdev(priv
)->mutex
);
101 ret
= nouveau_ramht_insert(priv
->ramht
, chid
, handle
, context
);
102 mutex_unlock(&nv_subdev(priv
)->mutex
);
107 nv40_fifo_context_attach(struct nouveau_object
*parent
,
108 struct nouveau_object
*engctx
)
110 struct nv04_fifo_priv
*priv
= (void *)parent
->engine
;
111 struct nv04_fifo_chan
*chan
= (void *)parent
;
115 switch (nv_engidx(engctx
->engine
)) {
116 case NVDEV_ENGINE_SW
:
118 case NVDEV_ENGINE_GR
:
122 case NVDEV_ENGINE_MPEG
:
130 spin_lock_irqsave(&priv
->base
.lock
, flags
);
131 nv_mask(priv
, 0x002500, 0x00000001, 0x00000000);
133 if ((nv_rd32(priv
, 0x003204) & priv
->base
.max
) == chan
->base
.chid
)
134 nv_wr32(priv
, reg
, nv_gpuobj(engctx
)->addr
>> 4);
135 nv_wo32(priv
->ramfc
, chan
->ramfc
+ ctx
, nv_gpuobj(engctx
)->addr
>> 4);
137 nv_mask(priv
, 0x002500, 0x00000001, 0x00000001);
138 spin_unlock_irqrestore(&priv
->base
.lock
, flags
);
143 nv40_fifo_context_detach(struct nouveau_object
*parent
, bool suspend
,
144 struct nouveau_object
*engctx
)
146 struct nv04_fifo_priv
*priv
= (void *)parent
->engine
;
147 struct nv04_fifo_chan
*chan
= (void *)parent
;
151 switch (nv_engidx(engctx
->engine
)) {
152 case NVDEV_ENGINE_SW
:
154 case NVDEV_ENGINE_GR
:
158 case NVDEV_ENGINE_MPEG
:
166 spin_lock_irqsave(&priv
->base
.lock
, flags
);
167 nv_mask(priv
, 0x002500, 0x00000001, 0x00000000);
169 if ((nv_rd32(priv
, 0x003204) & priv
->base
.max
) == chan
->base
.chid
)
170 nv_wr32(priv
, reg
, 0x00000000);
171 nv_wo32(priv
->ramfc
, chan
->ramfc
+ ctx
, 0x00000000);
173 nv_mask(priv
, 0x002500, 0x00000001, 0x00000001);
174 spin_unlock_irqrestore(&priv
->base
.lock
, flags
);
179 nv40_fifo_chan_ctor(struct nouveau_object
*parent
,
180 struct nouveau_object
*engine
,
181 struct nouveau_oclass
*oclass
, void *data
, u32 size
,
182 struct nouveau_object
**pobject
)
184 struct nv04_fifo_priv
*priv
= (void *)engine
;
185 struct nv04_fifo_chan
*chan
;
186 struct nv_channel_dma_class
*args
= data
;
189 if (size
< sizeof(*args
))
192 ret
= nouveau_fifo_channel_create(parent
, engine
, oclass
, 0, 0xc00000,
193 0x1000, args
->pushbuf
,
194 (1 << NVDEV_ENGINE_DMAOBJ
) |
195 (1 << NVDEV_ENGINE_SW
) |
196 (1 << NVDEV_ENGINE_GR
) |
197 (1 << NVDEV_ENGINE_MPEG
), &chan
);
198 *pobject
= nv_object(chan
);
202 nv_parent(chan
)->context_attach
= nv40_fifo_context_attach
;
203 nv_parent(chan
)->context_detach
= nv40_fifo_context_detach
;
204 nv_parent(chan
)->object_attach
= nv40_fifo_object_attach
;
205 nv_parent(chan
)->object_detach
= nv04_fifo_object_detach
;
206 chan
->ramfc
= chan
->base
.chid
* 128;
208 nv_wo32(priv
->ramfc
, chan
->ramfc
+ 0x00, args
->offset
);
209 nv_wo32(priv
->ramfc
, chan
->ramfc
+ 0x04, args
->offset
);
210 nv_wo32(priv
->ramfc
, chan
->ramfc
+ 0x0c, chan
->base
.pushgpu
->addr
>> 4);
211 nv_wo32(priv
->ramfc
, chan
->ramfc
+ 0x18, 0x30000000 |
212 NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES
|
213 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES
|
215 NV_PFIFO_CACHE1_BIG_ENDIAN
|
217 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8
);
218 nv_wo32(priv
->ramfc
, chan
->ramfc
+ 0x3c, 0x0001ffff);
222 static struct nouveau_ofuncs
224 .ctor
= nv40_fifo_chan_ctor
,
225 .dtor
= nv04_fifo_chan_dtor
,
226 .init
= nv04_fifo_chan_init
,
227 .fini
= nv04_fifo_chan_fini
,
228 .rd32
= _nouveau_fifo_channel_rd32
,
229 .wr32
= _nouveau_fifo_channel_wr32
,
232 static struct nouveau_oclass
233 nv40_fifo_sclass
[] = {
234 { 0x006e, &nv40_fifo_ofuncs
},
238 /*******************************************************************************
239 * FIFO context - basically just the instmem reserved for the channel
240 ******************************************************************************/
242 static struct nouveau_oclass
244 .handle
= NV_ENGCTX(FIFO
, 0x40),
245 .ofuncs
= &(struct nouveau_ofuncs
) {
246 .ctor
= nv04_fifo_context_ctor
,
247 .dtor
= _nouveau_fifo_context_dtor
,
248 .init
= _nouveau_fifo_context_init
,
249 .fini
= _nouveau_fifo_context_fini
,
250 .rd32
= _nouveau_fifo_context_rd32
,
251 .wr32
= _nouveau_fifo_context_wr32
,
255 /*******************************************************************************
257 ******************************************************************************/
260 nv40_fifo_ctor(struct nouveau_object
*parent
, struct nouveau_object
*engine
,
261 struct nouveau_oclass
*oclass
, void *data
, u32 size
,
262 struct nouveau_object
**pobject
)
264 struct nv04_instmem_priv
*imem
= nv04_instmem(parent
);
265 struct nv04_fifo_priv
*priv
;
268 ret
= nouveau_fifo_create(parent
, engine
, oclass
, 0, 31, &priv
);
269 *pobject
= nv_object(priv
);
273 nouveau_ramht_ref(imem
->ramht
, &priv
->ramht
);
274 nouveau_gpuobj_ref(imem
->ramro
, &priv
->ramro
);
275 nouveau_gpuobj_ref(imem
->ramfc
, &priv
->ramfc
);
277 nv_subdev(priv
)->unit
= 0x00000100;
278 nv_subdev(priv
)->intr
= nv04_fifo_intr
;
279 nv_engine(priv
)->cclass
= &nv40_fifo_cclass
;
280 nv_engine(priv
)->sclass
= nv40_fifo_sclass
;
281 priv
->base
.pause
= nv04_fifo_pause
;
282 priv
->base
.start
= nv04_fifo_start
;
283 priv
->ramfc_desc
= nv40_ramfc
;
288 nv40_fifo_init(struct nouveau_object
*object
)
290 struct nv04_fifo_priv
*priv
= (void *)object
;
291 struct nouveau_fb
*pfb
= nouveau_fb(object
);
294 ret
= nouveau_fifo_init(&priv
->base
);
298 nv_wr32(priv
, 0x002040, 0x000000ff);
299 nv_wr32(priv
, 0x002044, 0x2101ffff);
300 nv_wr32(priv
, 0x002058, 0x00000001);
302 nv_wr32(priv
, NV03_PFIFO_RAMHT
, (0x03 << 24) /* search 128 */ |
303 ((priv
->ramht
->bits
- 9) << 16) |
304 (priv
->ramht
->base
.addr
>> 8));
305 nv_wr32(priv
, NV03_PFIFO_RAMRO
, priv
->ramro
->addr
>> 8);
307 switch (nv_device(priv
)->chipset
) {
311 nv_wr32(priv
, 0x002230, 0x00000001);
318 nv_wr32(priv
, 0x002220, 0x00030002);
321 nv_wr32(priv
, 0x002230, 0x00000000);
322 nv_wr32(priv
, 0x002220, ((pfb
->ram
.size
- 512 * 1024 +
323 priv
->ramfc
->addr
) >> 16) |
328 nv_wr32(priv
, NV03_PFIFO_CACHE1_PUSH1
, priv
->base
.max
);
330 nv_wr32(priv
, NV03_PFIFO_INTR_0
, 0xffffffff);
331 nv_wr32(priv
, NV03_PFIFO_INTR_EN_0
, 0xffffffff);
333 nv_wr32(priv
, NV03_PFIFO_CACHE1_PUSH0
, 1);
334 nv_wr32(priv
, NV04_PFIFO_CACHE1_PULL0
, 1);
335 nv_wr32(priv
, NV03_PFIFO_CACHES
, 1);
339 struct nouveau_oclass
341 .handle
= NV_ENGINE(FIFO
, 0x40),
342 .ofuncs
= &(struct nouveau_ofuncs
) {
343 .ctor
= nv40_fifo_ctor
,
344 .dtor
= nv04_fifo_dtor
,
345 .init
= nv40_fifo_init
,
346 .fini
= _nouveau_fifo_fini
,