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drm/nouveau: port all engines to new engine module format
[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / engine / graph / ctxnv50.c
1 /*
2 * Copyright 2009 Marcin Kościelnicki
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <core/gpuobj.h>
24
25 #define CP_FLAG_CLEAR 0
26 #define CP_FLAG_SET 1
27 #define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0)
28 #define CP_FLAG_SWAP_DIRECTION_LOAD 0
29 #define CP_FLAG_SWAP_DIRECTION_SAVE 1
30 #define CP_FLAG_UNK01 ((0 * 32) + 1)
31 #define CP_FLAG_UNK01_CLEAR 0
32 #define CP_FLAG_UNK01_SET 1
33 #define CP_FLAG_UNK03 ((0 * 32) + 3)
34 #define CP_FLAG_UNK03_CLEAR 0
35 #define CP_FLAG_UNK03_SET 1
36 #define CP_FLAG_USER_SAVE ((0 * 32) + 5)
37 #define CP_FLAG_USER_SAVE_NOT_PENDING 0
38 #define CP_FLAG_USER_SAVE_PENDING 1
39 #define CP_FLAG_USER_LOAD ((0 * 32) + 6)
40 #define CP_FLAG_USER_LOAD_NOT_PENDING 0
41 #define CP_FLAG_USER_LOAD_PENDING 1
42 #define CP_FLAG_UNK0B ((0 * 32) + 0xb)
43 #define CP_FLAG_UNK0B_CLEAR 0
44 #define CP_FLAG_UNK0B_SET 1
45 #define CP_FLAG_XFER_SWITCH ((0 * 32) + 0xe)
46 #define CP_FLAG_XFER_SWITCH_DISABLE 0
47 #define CP_FLAG_XFER_SWITCH_ENABLE 1
48 #define CP_FLAG_STATE ((0 * 32) + 0x1c)
49 #define CP_FLAG_STATE_STOPPED 0
50 #define CP_FLAG_STATE_RUNNING 1
51 #define CP_FLAG_UNK1D ((0 * 32) + 0x1d)
52 #define CP_FLAG_UNK1D_CLEAR 0
53 #define CP_FLAG_UNK1D_SET 1
54 #define CP_FLAG_UNK20 ((1 * 32) + 0)
55 #define CP_FLAG_UNK20_CLEAR 0
56 #define CP_FLAG_UNK20_SET 1
57 #define CP_FLAG_STATUS ((2 * 32) + 0)
58 #define CP_FLAG_STATUS_BUSY 0
59 #define CP_FLAG_STATUS_IDLE 1
60 #define CP_FLAG_AUTO_SAVE ((2 * 32) + 4)
61 #define CP_FLAG_AUTO_SAVE_NOT_PENDING 0
62 #define CP_FLAG_AUTO_SAVE_PENDING 1
63 #define CP_FLAG_AUTO_LOAD ((2 * 32) + 5)
64 #define CP_FLAG_AUTO_LOAD_NOT_PENDING 0
65 #define CP_FLAG_AUTO_LOAD_PENDING 1
66 #define CP_FLAG_NEWCTX ((2 * 32) + 10)
67 #define CP_FLAG_NEWCTX_BUSY 0
68 #define CP_FLAG_NEWCTX_DONE 1
69 #define CP_FLAG_XFER ((2 * 32) + 11)
70 #define CP_FLAG_XFER_IDLE 0
71 #define CP_FLAG_XFER_BUSY 1
72 #define CP_FLAG_ALWAYS ((2 * 32) + 13)
73 #define CP_FLAG_ALWAYS_FALSE 0
74 #define CP_FLAG_ALWAYS_TRUE 1
75 #define CP_FLAG_INTR ((2 * 32) + 15)
76 #define CP_FLAG_INTR_NOT_PENDING 0
77 #define CP_FLAG_INTR_PENDING 1
78
79 #define CP_CTX 0x00100000
80 #define CP_CTX_COUNT 0x000f0000
81 #define CP_CTX_COUNT_SHIFT 16
82 #define CP_CTX_REG 0x00003fff
83 #define CP_LOAD_SR 0x00200000
84 #define CP_LOAD_SR_VALUE 0x000fffff
85 #define CP_BRA 0x00400000
86 #define CP_BRA_IP 0x0001ff00
87 #define CP_BRA_IP_SHIFT 8
88 #define CP_BRA_IF_CLEAR 0x00000080
89 #define CP_BRA_FLAG 0x0000007f
90 #define CP_WAIT 0x00500000
91 #define CP_WAIT_SET 0x00000080
92 #define CP_WAIT_FLAG 0x0000007f
93 #define CP_SET 0x00700000
94 #define CP_SET_1 0x00000080
95 #define CP_SET_FLAG 0x0000007f
96 #define CP_NEWCTX 0x00600004
97 #define CP_NEXT_TO_SWAP 0x00600005
98 #define CP_SET_CONTEXT_POINTER 0x00600006
99 #define CP_SET_XFER_POINTER 0x00600007
100 #define CP_ENABLE 0x00600009
101 #define CP_END 0x0060000c
102 #define CP_NEXT_TO_CURRENT 0x0060000d
103 #define CP_DISABLE1 0x0090ffff
104 #define CP_DISABLE2 0x0091ffff
105 #define CP_XFER_1 0x008000ff
106 #define CP_XFER_2 0x008800ff
107 #define CP_SEEK_1 0x00c000ff
108 #define CP_SEEK_2 0x00c800ff
109
110 #include "nv50.h"
111 #include "ctx.h"
112
113 #define IS_NVA3F(x) (((x) > 0xa0 && (x) < 0xaa) || (x) == 0xaf)
114 #define IS_NVAAF(x) ((x) >= 0xaa && (x) <= 0xac)
115
116 /*
117 * This code deals with PGRAPH contexts on NV50 family cards. Like NV40, it's
118 * the GPU itself that does context-switching, but it needs a special
119 * microcode to do it. And it's the driver's task to supply this microcode,
120 * further known as ctxprog, as well as the initial context values, known
121 * as ctxvals.
122 *
123 * Without ctxprog, you cannot switch contexts. Not even in software, since
124 * the majority of context [xfer strands] isn't accessible directly. You're
125 * stuck with a single channel, and you also suffer all the problems resulting
126 * from missing ctxvals, since you cannot load them.
127 *
128 * Without ctxvals, you're stuck with PGRAPH's default context. It's enough to
129 * run 2d operations, but trying to utilise 3d or CUDA will just lock you up,
130 * since you don't have... some sort of needed setup.
131 *
132 * Nouveau will just disable acceleration if not given ctxprog + ctxvals, since
133 * it's too much hassle to handle no-ctxprog as a special case.
134 */
135
136 /*
137 * How ctxprogs work.
138 *
139 * The ctxprog is written in its own kind of microcode, with very small and
140 * crappy set of available commands. You upload it to a small [512 insns]
141 * area of memory on PGRAPH, and it'll be run when PFIFO wants PGRAPH to
142 * switch channel. or when the driver explicitely requests it. Stuff visible
143 * to ctxprog consists of: PGRAPH MMIO registers, PGRAPH context strands,
144 * the per-channel context save area in VRAM [known as ctxvals or grctx],
145 * 4 flags registers, a scratch register, two grctx pointers, plus many
146 * random poorly-understood details.
147 *
148 * When ctxprog runs, it's supposed to check what operations are asked of it,
149 * save old context if requested, optionally reset PGRAPH and switch to the
150 * new channel, and load the new context. Context consists of three major
151 * parts: subset of MMIO registers and two "xfer areas".
152 */
153
154 /* TODO:
155 * - document unimplemented bits compared to nvidia
156 * - NVAx: make a TP subroutine, use it.
157 * - use 0x4008fc instead of 0x1540?
158 */
159
160 enum cp_label {
161 cp_check_load = 1,
162 cp_setup_auto_load,
163 cp_setup_load,
164 cp_setup_save,
165 cp_swap_state,
166 cp_prepare_exit,
167 cp_exit,
168 };
169
170 static void nv50_graph_construct_mmio(struct nouveau_grctx *ctx);
171 static void nv50_graph_construct_xfer1(struct nouveau_grctx *ctx);
172 static void nv50_graph_construct_xfer2(struct nouveau_grctx *ctx);
173
174 /* Main function: construct the ctxprog skeleton, call the other functions. */
175
176 static int
177 nv50_grctx_generate(struct nouveau_grctx *ctx)
178 {
179 cp_set (ctx, STATE, RUNNING);
180 cp_set (ctx, XFER_SWITCH, ENABLE);
181 /* decide whether we're loading/unloading the context */
182 cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save);
183 cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save);
184
185 cp_name(ctx, cp_check_load);
186 cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load);
187 cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load);
188 cp_bra (ctx, ALWAYS, TRUE, cp_prepare_exit);
189
190 /* setup for context load */
191 cp_name(ctx, cp_setup_auto_load);
192 cp_out (ctx, CP_DISABLE1);
193 cp_out (ctx, CP_DISABLE2);
194 cp_out (ctx, CP_ENABLE);
195 cp_out (ctx, CP_NEXT_TO_SWAP);
196 cp_set (ctx, UNK01, SET);
197 cp_name(ctx, cp_setup_load);
198 cp_out (ctx, CP_NEWCTX);
199 cp_wait(ctx, NEWCTX, BUSY);
200 cp_set (ctx, UNK1D, CLEAR);
201 cp_set (ctx, SWAP_DIRECTION, LOAD);
202 cp_bra (ctx, UNK0B, SET, cp_prepare_exit);
203 cp_bra (ctx, ALWAYS, TRUE, cp_swap_state);
204
205 /* setup for context save */
206 cp_name(ctx, cp_setup_save);
207 cp_set (ctx, UNK1D, SET);
208 cp_wait(ctx, STATUS, BUSY);
209 cp_wait(ctx, INTR, PENDING);
210 cp_bra (ctx, STATUS, BUSY, cp_setup_save);
211 cp_set (ctx, UNK01, SET);
212 cp_set (ctx, SWAP_DIRECTION, SAVE);
213
214 /* general PGRAPH state */
215 cp_name(ctx, cp_swap_state);
216 cp_set (ctx, UNK03, SET);
217 cp_pos (ctx, 0x00004/4);
218 cp_ctx (ctx, 0x400828, 1); /* needed. otherwise, flickering happens. */
219 cp_pos (ctx, 0x00100/4);
220 nv50_graph_construct_mmio(ctx);
221 nv50_graph_construct_xfer1(ctx);
222 nv50_graph_construct_xfer2(ctx);
223
224 cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load);
225
226 cp_set (ctx, UNK20, SET);
227 cp_set (ctx, SWAP_DIRECTION, SAVE); /* no idea why this is needed, but fixes at least one lockup. */
228 cp_lsr (ctx, ctx->ctxvals_base);
229 cp_out (ctx, CP_SET_XFER_POINTER);
230 cp_lsr (ctx, 4);
231 cp_out (ctx, CP_SEEK_1);
232 cp_out (ctx, CP_XFER_1);
233 cp_wait(ctx, XFER, BUSY);
234
235 /* pre-exit state updates */
236 cp_name(ctx, cp_prepare_exit);
237 cp_set (ctx, UNK01, CLEAR);
238 cp_set (ctx, UNK03, CLEAR);
239 cp_set (ctx, UNK1D, CLEAR);
240
241 cp_bra (ctx, USER_SAVE, PENDING, cp_exit);
242 cp_out (ctx, CP_NEXT_TO_CURRENT);
243
244 cp_name(ctx, cp_exit);
245 cp_set (ctx, USER_SAVE, NOT_PENDING);
246 cp_set (ctx, USER_LOAD, NOT_PENDING);
247 cp_set (ctx, XFER_SWITCH, DISABLE);
248 cp_set (ctx, STATE, STOPPED);
249 cp_out (ctx, CP_END);
250 ctx->ctxvals_pos += 0x400; /* padding... no idea why you need it */
251
252 return 0;
253 }
254
255 void
256 nv50_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem)
257 {
258 nv50_grctx_generate(&(struct nouveau_grctx) {
259 .device = device,
260 .mode = NOUVEAU_GRCTX_VALS,
261 .data = mem,
262 });
263 }
264
265 int
266 nv50_grctx_init(struct nouveau_device *device, u32 *size)
267 {
268 u32 *ctxprog = kmalloc(512 * 4, GFP_KERNEL), i;
269 struct nouveau_grctx ctx = {
270 .device = device,
271 .mode = NOUVEAU_GRCTX_PROG,
272 .data = ctxprog,
273 .ctxprog_max = 512,
274 };
275
276 if (!ctxprog)
277 return -ENOMEM;
278 nv50_grctx_generate(&ctx);
279
280 nv_wr32(device, 0x400324, 0);
281 for (i = 0; i < ctx.ctxprog_len; i++)
282 nv_wr32(device, 0x400328, ctxprog[i]);
283 *size = ctx.ctxvals_pos * 4;
284 kfree(ctxprog);
285 return 0;
286 }
287
288 /*
289 * Constructs MMIO part of ctxprog and ctxvals. Just a matter of knowing which
290 * registers to save/restore and the default values for them.
291 */
292
293 static void
294 nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx);
295
296 static void
297 nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
298 {
299 struct nouveau_device *device = ctx->device;
300 int i, j;
301 int offset, base;
302 u32 units = nv_rd32 (ctx->device, 0x1540);
303
304 /* 0800: DISPATCH */
305 cp_ctx(ctx, 0x400808, 7);
306 gr_def(ctx, 0x400814, 0x00000030);
307 cp_ctx(ctx, 0x400834, 0x32);
308 if (device->chipset == 0x50) {
309 gr_def(ctx, 0x400834, 0xff400040);
310 gr_def(ctx, 0x400838, 0xfff00080);
311 gr_def(ctx, 0x40083c, 0xfff70090);
312 gr_def(ctx, 0x400840, 0xffe806a8);
313 }
314 gr_def(ctx, 0x400844, 0x00000002);
315 if (IS_NVA3F(device->chipset))
316 gr_def(ctx, 0x400894, 0x00001000);
317 gr_def(ctx, 0x4008e8, 0x00000003);
318 gr_def(ctx, 0x4008ec, 0x00001000);
319 if (device->chipset == 0x50)
320 cp_ctx(ctx, 0x400908, 0xb);
321 else if (device->chipset < 0xa0)
322 cp_ctx(ctx, 0x400908, 0xc);
323 else
324 cp_ctx(ctx, 0x400908, 0xe);
325
326 if (device->chipset >= 0xa0)
327 cp_ctx(ctx, 0x400b00, 0x1);
328 if (IS_NVA3F(device->chipset)) {
329 cp_ctx(ctx, 0x400b10, 0x1);
330 gr_def(ctx, 0x400b10, 0x0001629d);
331 cp_ctx(ctx, 0x400b20, 0x1);
332 gr_def(ctx, 0x400b20, 0x0001629d);
333 }
334
335 nv50_graph_construct_mmio_ddata(ctx);
336
337 /* 0C00: VFETCH */
338 cp_ctx(ctx, 0x400c08, 0x2);
339 gr_def(ctx, 0x400c08, 0x0000fe0c);
340
341 /* 1000 */
342 if (device->chipset < 0xa0) {
343 cp_ctx(ctx, 0x401008, 0x4);
344 gr_def(ctx, 0x401014, 0x00001000);
345 } else if (!IS_NVA3F(device->chipset)) {
346 cp_ctx(ctx, 0x401008, 0x5);
347 gr_def(ctx, 0x401018, 0x00001000);
348 } else {
349 cp_ctx(ctx, 0x401008, 0x5);
350 gr_def(ctx, 0x401018, 0x00004000);
351 }
352
353 /* 1400 */
354 cp_ctx(ctx, 0x401400, 0x8);
355 cp_ctx(ctx, 0x401424, 0x3);
356 if (device->chipset == 0x50)
357 gr_def(ctx, 0x40142c, 0x0001fd87);
358 else
359 gr_def(ctx, 0x40142c, 0x00000187);
360 cp_ctx(ctx, 0x401540, 0x5);
361 gr_def(ctx, 0x401550, 0x00001018);
362
363 /* 1800: STREAMOUT */
364 cp_ctx(ctx, 0x401814, 0x1);
365 gr_def(ctx, 0x401814, 0x000000ff);
366 if (device->chipset == 0x50) {
367 cp_ctx(ctx, 0x40181c, 0xe);
368 gr_def(ctx, 0x401850, 0x00000004);
369 } else if (device->chipset < 0xa0) {
370 cp_ctx(ctx, 0x40181c, 0xf);
371 gr_def(ctx, 0x401854, 0x00000004);
372 } else {
373 cp_ctx(ctx, 0x40181c, 0x13);
374 gr_def(ctx, 0x401864, 0x00000004);
375 }
376
377 /* 1C00 */
378 cp_ctx(ctx, 0x401c00, 0x1);
379 switch (device->chipset) {
380 case 0x50:
381 gr_def(ctx, 0x401c00, 0x0001005f);
382 break;
383 case 0x84:
384 case 0x86:
385 case 0x94:
386 gr_def(ctx, 0x401c00, 0x044d00df);
387 break;
388 case 0x92:
389 case 0x96:
390 case 0x98:
391 case 0xa0:
392 case 0xaa:
393 case 0xac:
394 gr_def(ctx, 0x401c00, 0x042500df);
395 break;
396 case 0xa3:
397 case 0xa5:
398 case 0xa8:
399 case 0xaf:
400 gr_def(ctx, 0x401c00, 0x142500df);
401 break;
402 }
403
404 /* 2000 */
405
406 /* 2400 */
407 cp_ctx(ctx, 0x402400, 0x1);
408 if (device->chipset == 0x50)
409 cp_ctx(ctx, 0x402408, 0x1);
410 else
411 cp_ctx(ctx, 0x402408, 0x2);
412 gr_def(ctx, 0x402408, 0x00000600);
413
414 /* 2800: CSCHED */
415 cp_ctx(ctx, 0x402800, 0x1);
416 if (device->chipset == 0x50)
417 gr_def(ctx, 0x402800, 0x00000006);
418
419 /* 2C00: ZCULL */
420 cp_ctx(ctx, 0x402c08, 0x6);
421 if (device->chipset != 0x50)
422 gr_def(ctx, 0x402c14, 0x01000000);
423 gr_def(ctx, 0x402c18, 0x000000ff);
424 if (device->chipset == 0x50)
425 cp_ctx(ctx, 0x402ca0, 0x1);
426 else
427 cp_ctx(ctx, 0x402ca0, 0x2);
428 if (device->chipset < 0xa0)
429 gr_def(ctx, 0x402ca0, 0x00000400);
430 else if (!IS_NVA3F(device->chipset))
431 gr_def(ctx, 0x402ca0, 0x00000800);
432 else
433 gr_def(ctx, 0x402ca0, 0x00000400);
434 cp_ctx(ctx, 0x402cac, 0x4);
435
436 /* 3000: ENG2D */
437 cp_ctx(ctx, 0x403004, 0x1);
438 gr_def(ctx, 0x403004, 0x00000001);
439
440 /* 3400 */
441 if (device->chipset >= 0xa0) {
442 cp_ctx(ctx, 0x403404, 0x1);
443 gr_def(ctx, 0x403404, 0x00000001);
444 }
445
446 /* 5000: CCACHE */
447 cp_ctx(ctx, 0x405000, 0x1);
448 switch (device->chipset) {
449 case 0x50:
450 gr_def(ctx, 0x405000, 0x00300080);
451 break;
452 case 0x84:
453 case 0xa0:
454 case 0xa3:
455 case 0xa5:
456 case 0xa8:
457 case 0xaa:
458 case 0xac:
459 case 0xaf:
460 gr_def(ctx, 0x405000, 0x000e0080);
461 break;
462 case 0x86:
463 case 0x92:
464 case 0x94:
465 case 0x96:
466 case 0x98:
467 gr_def(ctx, 0x405000, 0x00000080);
468 break;
469 }
470 cp_ctx(ctx, 0x405014, 0x1);
471 gr_def(ctx, 0x405014, 0x00000004);
472 cp_ctx(ctx, 0x40501c, 0x1);
473 cp_ctx(ctx, 0x405024, 0x1);
474 cp_ctx(ctx, 0x40502c, 0x1);
475
476 /* 6000? */
477 if (device->chipset == 0x50)
478 cp_ctx(ctx, 0x4063e0, 0x1);
479
480 /* 6800: M2MF */
481 if (device->chipset < 0x90) {
482 cp_ctx(ctx, 0x406814, 0x2b);
483 gr_def(ctx, 0x406818, 0x00000f80);
484 gr_def(ctx, 0x406860, 0x007f0080);
485 gr_def(ctx, 0x40689c, 0x007f0080);
486 } else {
487 cp_ctx(ctx, 0x406814, 0x4);
488 if (device->chipset == 0x98)
489 gr_def(ctx, 0x406818, 0x00000f80);
490 else
491 gr_def(ctx, 0x406818, 0x00001f80);
492 if (IS_NVA3F(device->chipset))
493 gr_def(ctx, 0x40681c, 0x00000030);
494 cp_ctx(ctx, 0x406830, 0x3);
495 }
496
497 /* 7000: per-ROP group state */
498 for (i = 0; i < 8; i++) {
499 if (units & (1<<(i+16))) {
500 cp_ctx(ctx, 0x407000 + (i<<8), 3);
501 if (device->chipset == 0x50)
502 gr_def(ctx, 0x407000 + (i<<8), 0x1b74f820);
503 else if (device->chipset != 0xa5)
504 gr_def(ctx, 0x407000 + (i<<8), 0x3b74f821);
505 else
506 gr_def(ctx, 0x407000 + (i<<8), 0x7b74f821);
507 gr_def(ctx, 0x407004 + (i<<8), 0x89058001);
508
509 if (device->chipset == 0x50) {
510 cp_ctx(ctx, 0x407010 + (i<<8), 1);
511 } else if (device->chipset < 0xa0) {
512 cp_ctx(ctx, 0x407010 + (i<<8), 2);
513 gr_def(ctx, 0x407010 + (i<<8), 0x00001000);
514 gr_def(ctx, 0x407014 + (i<<8), 0x0000001f);
515 } else {
516 cp_ctx(ctx, 0x407010 + (i<<8), 3);
517 gr_def(ctx, 0x407010 + (i<<8), 0x00001000);
518 if (device->chipset != 0xa5)
519 gr_def(ctx, 0x407014 + (i<<8), 0x000000ff);
520 else
521 gr_def(ctx, 0x407014 + (i<<8), 0x000001ff);
522 }
523
524 cp_ctx(ctx, 0x407080 + (i<<8), 4);
525 if (device->chipset != 0xa5)
526 gr_def(ctx, 0x407080 + (i<<8), 0x027c10fa);
527 else
528 gr_def(ctx, 0x407080 + (i<<8), 0x827c10fa);
529 if (device->chipset == 0x50)
530 gr_def(ctx, 0x407084 + (i<<8), 0x000000c0);
531 else
532 gr_def(ctx, 0x407084 + (i<<8), 0x400000c0);
533 gr_def(ctx, 0x407088 + (i<<8), 0xb7892080);
534
535 if (device->chipset < 0xa0)
536 cp_ctx(ctx, 0x407094 + (i<<8), 1);
537 else if (!IS_NVA3F(device->chipset))
538 cp_ctx(ctx, 0x407094 + (i<<8), 3);
539 else {
540 cp_ctx(ctx, 0x407094 + (i<<8), 4);
541 gr_def(ctx, 0x4070a0 + (i<<8), 1);
542 }
543 }
544 }
545
546 cp_ctx(ctx, 0x407c00, 0x3);
547 if (device->chipset < 0x90)
548 gr_def(ctx, 0x407c00, 0x00010040);
549 else if (device->chipset < 0xa0)
550 gr_def(ctx, 0x407c00, 0x00390040);
551 else
552 gr_def(ctx, 0x407c00, 0x003d0040);
553 gr_def(ctx, 0x407c08, 0x00000022);
554 if (device->chipset >= 0xa0) {
555 cp_ctx(ctx, 0x407c10, 0x3);
556 cp_ctx(ctx, 0x407c20, 0x1);
557 cp_ctx(ctx, 0x407c2c, 0x1);
558 }
559
560 if (device->chipset < 0xa0) {
561 cp_ctx(ctx, 0x407d00, 0x9);
562 } else {
563 cp_ctx(ctx, 0x407d00, 0x15);
564 }
565 if (device->chipset == 0x98)
566 gr_def(ctx, 0x407d08, 0x00380040);
567 else {
568 if (device->chipset < 0x90)
569 gr_def(ctx, 0x407d08, 0x00010040);
570 else if (device->chipset < 0xa0)
571 gr_def(ctx, 0x407d08, 0x00390040);
572 else
573 gr_def(ctx, 0x407d08, 0x003d0040);
574 gr_def(ctx, 0x407d0c, 0x00000022);
575 }
576
577 /* 8000+: per-TP state */
578 for (i = 0; i < 10; i++) {
579 if (units & (1<<i)) {
580 if (device->chipset < 0xa0)
581 base = 0x408000 + (i<<12);
582 else
583 base = 0x408000 + (i<<11);
584 if (device->chipset < 0xa0)
585 offset = base + 0xc00;
586 else
587 offset = base + 0x80;
588 cp_ctx(ctx, offset + 0x00, 1);
589 gr_def(ctx, offset + 0x00, 0x0000ff0a);
590 cp_ctx(ctx, offset + 0x08, 1);
591
592 /* per-MP state */
593 for (j = 0; j < (device->chipset < 0xa0 ? 2 : 4); j++) {
594 if (!(units & (1 << (j+24)))) continue;
595 if (device->chipset < 0xa0)
596 offset = base + 0x200 + (j<<7);
597 else
598 offset = base + 0x100 + (j<<7);
599 cp_ctx(ctx, offset, 0x20);
600 gr_def(ctx, offset + 0x00, 0x01800000);
601 gr_def(ctx, offset + 0x04, 0x00160000);
602 gr_def(ctx, offset + 0x08, 0x01800000);
603 gr_def(ctx, offset + 0x18, 0x0003ffff);
604 switch (device->chipset) {
605 case 0x50:
606 gr_def(ctx, offset + 0x1c, 0x00080000);
607 break;
608 case 0x84:
609 gr_def(ctx, offset + 0x1c, 0x00880000);
610 break;
611 case 0x86:
612 gr_def(ctx, offset + 0x1c, 0x018c0000);
613 break;
614 case 0x92:
615 case 0x96:
616 case 0x98:
617 gr_def(ctx, offset + 0x1c, 0x118c0000);
618 break;
619 case 0x94:
620 gr_def(ctx, offset + 0x1c, 0x10880000);
621 break;
622 case 0xa0:
623 case 0xa5:
624 gr_def(ctx, offset + 0x1c, 0x310c0000);
625 break;
626 case 0xa3:
627 case 0xa8:
628 case 0xaa:
629 case 0xac:
630 case 0xaf:
631 gr_def(ctx, offset + 0x1c, 0x300c0000);
632 break;
633 }
634 gr_def(ctx, offset + 0x40, 0x00010401);
635 if (device->chipset == 0x50)
636 gr_def(ctx, offset + 0x48, 0x00000040);
637 else
638 gr_def(ctx, offset + 0x48, 0x00000078);
639 gr_def(ctx, offset + 0x50, 0x000000bf);
640 gr_def(ctx, offset + 0x58, 0x00001210);
641 if (device->chipset == 0x50)
642 gr_def(ctx, offset + 0x5c, 0x00000080);
643 else
644 gr_def(ctx, offset + 0x5c, 0x08000080);
645 if (device->chipset >= 0xa0)
646 gr_def(ctx, offset + 0x68, 0x0000003e);
647 }
648
649 if (device->chipset < 0xa0)
650 cp_ctx(ctx, base + 0x300, 0x4);
651 else
652 cp_ctx(ctx, base + 0x300, 0x5);
653 if (device->chipset == 0x50)
654 gr_def(ctx, base + 0x304, 0x00007070);
655 else if (device->chipset < 0xa0)
656 gr_def(ctx, base + 0x304, 0x00027070);
657 else if (!IS_NVA3F(device->chipset))
658 gr_def(ctx, base + 0x304, 0x01127070);
659 else
660 gr_def(ctx, base + 0x304, 0x05127070);
661
662 if (device->chipset < 0xa0)
663 cp_ctx(ctx, base + 0x318, 1);
664 else
665 cp_ctx(ctx, base + 0x320, 1);
666 if (device->chipset == 0x50)
667 gr_def(ctx, base + 0x318, 0x0003ffff);
668 else if (device->chipset < 0xa0)
669 gr_def(ctx, base + 0x318, 0x03ffffff);
670 else
671 gr_def(ctx, base + 0x320, 0x07ffffff);
672
673 if (device->chipset < 0xa0)
674 cp_ctx(ctx, base + 0x324, 5);
675 else
676 cp_ctx(ctx, base + 0x328, 4);
677
678 if (device->chipset < 0xa0) {
679 cp_ctx(ctx, base + 0x340, 9);
680 offset = base + 0x340;
681 } else if (!IS_NVA3F(device->chipset)) {
682 cp_ctx(ctx, base + 0x33c, 0xb);
683 offset = base + 0x344;
684 } else {
685 cp_ctx(ctx, base + 0x33c, 0xd);
686 offset = base + 0x344;
687 }
688 gr_def(ctx, offset + 0x0, 0x00120407);
689 gr_def(ctx, offset + 0x4, 0x05091507);
690 if (device->chipset == 0x84)
691 gr_def(ctx, offset + 0x8, 0x05100202);
692 else
693 gr_def(ctx, offset + 0x8, 0x05010202);
694 gr_def(ctx, offset + 0xc, 0x00030201);
695 if (device->chipset == 0xa3)
696 cp_ctx(ctx, base + 0x36c, 1);
697
698 cp_ctx(ctx, base + 0x400, 2);
699 gr_def(ctx, base + 0x404, 0x00000040);
700 cp_ctx(ctx, base + 0x40c, 2);
701 gr_def(ctx, base + 0x40c, 0x0d0c0b0a);
702 gr_def(ctx, base + 0x410, 0x00141210);
703
704 if (device->chipset < 0xa0)
705 offset = base + 0x800;
706 else
707 offset = base + 0x500;
708 cp_ctx(ctx, offset, 6);
709 gr_def(ctx, offset + 0x0, 0x000001f0);
710 gr_def(ctx, offset + 0x4, 0x00000001);
711 gr_def(ctx, offset + 0x8, 0x00000003);
712 if (device->chipset == 0x50 || IS_NVAAF(device->chipset))
713 gr_def(ctx, offset + 0xc, 0x00008000);
714 gr_def(ctx, offset + 0x14, 0x00039e00);
715 cp_ctx(ctx, offset + 0x1c, 2);
716 if (device->chipset == 0x50)
717 gr_def(ctx, offset + 0x1c, 0x00000040);
718 else
719 gr_def(ctx, offset + 0x1c, 0x00000100);
720 gr_def(ctx, offset + 0x20, 0x00003800);
721
722 if (device->chipset >= 0xa0) {
723 cp_ctx(ctx, base + 0x54c, 2);
724 if (!IS_NVA3F(device->chipset))
725 gr_def(ctx, base + 0x54c, 0x003fe006);
726 else
727 gr_def(ctx, base + 0x54c, 0x003fe007);
728 gr_def(ctx, base + 0x550, 0x003fe000);
729 }
730
731 if (device->chipset < 0xa0)
732 offset = base + 0xa00;
733 else
734 offset = base + 0x680;
735 cp_ctx(ctx, offset, 1);
736 gr_def(ctx, offset, 0x00404040);
737
738 if (device->chipset < 0xa0)
739 offset = base + 0xe00;
740 else
741 offset = base + 0x700;
742 cp_ctx(ctx, offset, 2);
743 if (device->chipset < 0xa0)
744 gr_def(ctx, offset, 0x0077f005);
745 else if (device->chipset == 0xa5)
746 gr_def(ctx, offset, 0x6cf7f007);
747 else if (device->chipset == 0xa8)
748 gr_def(ctx, offset, 0x6cfff007);
749 else if (device->chipset == 0xac)
750 gr_def(ctx, offset, 0x0cfff007);
751 else
752 gr_def(ctx, offset, 0x0cf7f007);
753 if (device->chipset == 0x50)
754 gr_def(ctx, offset + 0x4, 0x00007fff);
755 else if (device->chipset < 0xa0)
756 gr_def(ctx, offset + 0x4, 0x003f7fff);
757 else
758 gr_def(ctx, offset + 0x4, 0x02bf7fff);
759 cp_ctx(ctx, offset + 0x2c, 1);
760 if (device->chipset == 0x50) {
761 cp_ctx(ctx, offset + 0x50, 9);
762 gr_def(ctx, offset + 0x54, 0x000003ff);
763 gr_def(ctx, offset + 0x58, 0x00000003);
764 gr_def(ctx, offset + 0x5c, 0x00000003);
765 gr_def(ctx, offset + 0x60, 0x000001ff);
766 gr_def(ctx, offset + 0x64, 0x0000001f);
767 gr_def(ctx, offset + 0x68, 0x0000000f);
768 gr_def(ctx, offset + 0x6c, 0x0000000f);
769 } else if (device->chipset < 0xa0) {
770 cp_ctx(ctx, offset + 0x50, 1);
771 cp_ctx(ctx, offset + 0x70, 1);
772 } else {
773 cp_ctx(ctx, offset + 0x50, 1);
774 cp_ctx(ctx, offset + 0x60, 5);
775 }
776 }
777 }
778 }
779
780 static void
781 dd_emit(struct nouveau_grctx *ctx, int num, u32 val) {
782 int i;
783 if (val && ctx->mode == NOUVEAU_GRCTX_VALS)
784 for (i = 0; i < num; i++)
785 nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + i), val);
786 ctx->ctxvals_pos += num;
787 }
788
789 static void
790 nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx)
791 {
792 struct nouveau_device *device = ctx->device;
793 int base, num;
794 base = ctx->ctxvals_pos;
795
796 /* tesla state */
797 dd_emit(ctx, 1, 0); /* 00000001 UNK0F90 */
798 dd_emit(ctx, 1, 0); /* 00000001 UNK135C */
799
800 /* SRC_TIC state */
801 dd_emit(ctx, 1, 0); /* 00000007 SRC_TILE_MODE_Z */
802 dd_emit(ctx, 1, 2); /* 00000007 SRC_TILE_MODE_Y */
803 dd_emit(ctx, 1, 1); /* 00000001 SRC_LINEAR #1 */
804 dd_emit(ctx, 1, 0); /* 000000ff SRC_ADDRESS_HIGH */
805 dd_emit(ctx, 1, 0); /* 00000001 SRC_SRGB */
806 if (device->chipset >= 0x94)
807 dd_emit(ctx, 1, 0); /* 00000003 eng2d UNK0258 */
808 dd_emit(ctx, 1, 1); /* 00000fff SRC_DEPTH */
809 dd_emit(ctx, 1, 0x100); /* 0000ffff SRC_HEIGHT */
810
811 /* turing state */
812 dd_emit(ctx, 1, 0); /* 0000000f TEXTURES_LOG2 */
813 dd_emit(ctx, 1, 0); /* 0000000f SAMPLERS_LOG2 */
814 dd_emit(ctx, 1, 0); /* 000000ff CB_DEF_ADDRESS_HIGH */
815 dd_emit(ctx, 1, 0); /* ffffffff CB_DEF_ADDRESS_LOW */
816 dd_emit(ctx, 1, 0); /* ffffffff SHARED_SIZE */
817 dd_emit(ctx, 1, 2); /* ffffffff REG_MODE */
818 dd_emit(ctx, 1, 1); /* 0000ffff BLOCK_ALLOC_THREADS */
819 dd_emit(ctx, 1, 1); /* 00000001 LANES32 */
820 dd_emit(ctx, 1, 0); /* 000000ff UNK370 */
821 dd_emit(ctx, 1, 0); /* 000000ff USER_PARAM_UNK */
822 dd_emit(ctx, 1, 0); /* 000000ff USER_PARAM_COUNT */
823 dd_emit(ctx, 1, 1); /* 000000ff UNK384 bits 8-15 */
824 dd_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */
825 dd_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */
826 dd_emit(ctx, 1, 0); /* 0000ffff CB_ADDR_INDEX */
827 dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_X */
828 dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_XMY */
829 dd_emit(ctx, 1, 0); /* 00000001 BLOCKDIM_XMY_OVERFLOW */
830 dd_emit(ctx, 1, 1); /* 0003ffff BLOCKDIM_XMYMZ */
831 dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_Y */
832 dd_emit(ctx, 1, 1); /* 0000007f BLOCKDIM_Z */
833 dd_emit(ctx, 1, 4); /* 000000ff CP_REG_ALLOC_TEMP */
834 dd_emit(ctx, 1, 1); /* 00000001 BLOCKDIM_DIRTY */
835 if (IS_NVA3F(device->chipset))
836 dd_emit(ctx, 1, 0); /* 00000003 UNK03E8 */
837 dd_emit(ctx, 1, 1); /* 0000007f BLOCK_ALLOC_HALFWARPS */
838 dd_emit(ctx, 1, 1); /* 00000007 LOCAL_WARPS_NO_CLAMP */
839 dd_emit(ctx, 1, 7); /* 00000007 LOCAL_WARPS_LOG_ALLOC */
840 dd_emit(ctx, 1, 1); /* 00000007 STACK_WARPS_NO_CLAMP */
841 dd_emit(ctx, 1, 7); /* 00000007 STACK_WARPS_LOG_ALLOC */
842 dd_emit(ctx, 1, 1); /* 00001fff BLOCK_ALLOC_REGSLOTS_PACKED */
843 dd_emit(ctx, 1, 1); /* 00001fff BLOCK_ALLOC_REGSLOTS_STRIDED */
844 dd_emit(ctx, 1, 1); /* 000007ff BLOCK_ALLOC_THREADS */
845
846 /* compat 2d state */
847 if (device->chipset == 0x50) {
848 dd_emit(ctx, 4, 0); /* 0000ffff clip X, Y, W, H */
849
850 dd_emit(ctx, 1, 1); /* ffffffff chroma COLOR_FORMAT */
851
852 dd_emit(ctx, 1, 1); /* ffffffff pattern COLOR_FORMAT */
853 dd_emit(ctx, 1, 0); /* ffffffff pattern SHAPE */
854 dd_emit(ctx, 1, 1); /* ffffffff pattern PATTERN_SELECT */
855
856 dd_emit(ctx, 1, 0xa); /* ffffffff surf2d SRC_FORMAT */
857 dd_emit(ctx, 1, 0); /* ffffffff surf2d DMA_SRC */
858 dd_emit(ctx, 1, 0); /* 000000ff surf2d SRC_ADDRESS_HIGH */
859 dd_emit(ctx, 1, 0); /* ffffffff surf2d SRC_ADDRESS_LOW */
860 dd_emit(ctx, 1, 0x40); /* 0000ffff surf2d SRC_PITCH */
861 dd_emit(ctx, 1, 0); /* 0000000f surf2d SRC_TILE_MODE_Z */
862 dd_emit(ctx, 1, 2); /* 0000000f surf2d SRC_TILE_MODE_Y */
863 dd_emit(ctx, 1, 0x100); /* ffffffff surf2d SRC_HEIGHT */
864 dd_emit(ctx, 1, 1); /* 00000001 surf2d SRC_LINEAR */
865 dd_emit(ctx, 1, 0x100); /* ffffffff surf2d SRC_WIDTH */
866
867 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_B_X */
868 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_B_Y */
869 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_C_X */
870 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_C_Y */
871 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_D_X */
872 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_D_Y */
873 dd_emit(ctx, 1, 1); /* ffffffff gdirect COLOR_FORMAT */
874 dd_emit(ctx, 1, 0); /* ffffffff gdirect OPERATION */
875 dd_emit(ctx, 1, 0); /* 0000ffff gdirect POINT_X */
876 dd_emit(ctx, 1, 0); /* 0000ffff gdirect POINT_Y */
877
878 dd_emit(ctx, 1, 0); /* 0000ffff blit SRC_Y */
879 dd_emit(ctx, 1, 0); /* ffffffff blit OPERATION */
880
881 dd_emit(ctx, 1, 0); /* ffffffff ifc OPERATION */
882
883 dd_emit(ctx, 1, 0); /* ffffffff iifc INDEX_FORMAT */
884 dd_emit(ctx, 1, 0); /* ffffffff iifc LUT_OFFSET */
885 dd_emit(ctx, 1, 4); /* ffffffff iifc COLOR_FORMAT */
886 dd_emit(ctx, 1, 0); /* ffffffff iifc OPERATION */
887 }
888
889 /* m2mf state */
890 dd_emit(ctx, 1, 0); /* ffffffff m2mf LINE_COUNT */
891 dd_emit(ctx, 1, 0); /* ffffffff m2mf LINE_LENGTH_IN */
892 dd_emit(ctx, 2, 0); /* ffffffff m2mf OFFSET_IN, OFFSET_OUT */
893 dd_emit(ctx, 1, 1); /* ffffffff m2mf TILING_DEPTH_OUT */
894 dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_HEIGHT_OUT */
895 dd_emit(ctx, 1, 0); /* ffffffff m2mf TILING_POSITION_OUT_Z */
896 dd_emit(ctx, 1, 1); /* 00000001 m2mf LINEAR_OUT */
897 dd_emit(ctx, 2, 0); /* 0000ffff m2mf TILING_POSITION_OUT_X, Y */
898 dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_PITCH_OUT */
899 dd_emit(ctx, 1, 1); /* ffffffff m2mf TILING_DEPTH_IN */
900 dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_HEIGHT_IN */
901 dd_emit(ctx, 1, 0); /* ffffffff m2mf TILING_POSITION_IN_Z */
902 dd_emit(ctx, 1, 1); /* 00000001 m2mf LINEAR_IN */
903 dd_emit(ctx, 2, 0); /* 0000ffff m2mf TILING_POSITION_IN_X, Y */
904 dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_PITCH_IN */
905
906 /* more compat 2d state */
907 if (device->chipset == 0x50) {
908 dd_emit(ctx, 1, 1); /* ffffffff line COLOR_FORMAT */
909 dd_emit(ctx, 1, 0); /* ffffffff line OPERATION */
910
911 dd_emit(ctx, 1, 1); /* ffffffff triangle COLOR_FORMAT */
912 dd_emit(ctx, 1, 0); /* ffffffff triangle OPERATION */
913
914 dd_emit(ctx, 1, 0); /* 0000000f sifm TILE_MODE_Z */
915 dd_emit(ctx, 1, 2); /* 0000000f sifm TILE_MODE_Y */
916 dd_emit(ctx, 1, 0); /* 000000ff sifm FORMAT_FILTER */
917 dd_emit(ctx, 1, 1); /* 000000ff sifm FORMAT_ORIGIN */
918 dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_PITCH */
919 dd_emit(ctx, 1, 1); /* 00000001 sifm SRC_LINEAR */
920 dd_emit(ctx, 1, 0); /* 000000ff sifm SRC_OFFSET_HIGH */
921 dd_emit(ctx, 1, 0); /* ffffffff sifm SRC_OFFSET */
922 dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_HEIGHT */
923 dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_WIDTH */
924 dd_emit(ctx, 1, 3); /* ffffffff sifm COLOR_FORMAT */
925 dd_emit(ctx, 1, 0); /* ffffffff sifm OPERATION */
926
927 dd_emit(ctx, 1, 0); /* ffffffff sifc OPERATION */
928 }
929
930 /* tesla state */
931 dd_emit(ctx, 1, 0); /* 0000000f GP_TEXTURES_LOG2 */
932 dd_emit(ctx, 1, 0); /* 0000000f GP_SAMPLERS_LOG2 */
933 dd_emit(ctx, 1, 0); /* 000000ff */
934 dd_emit(ctx, 1, 0); /* ffffffff */
935 dd_emit(ctx, 1, 4); /* 000000ff UNK12B0_0 */
936 dd_emit(ctx, 1, 0x70); /* 000000ff UNK12B0_1 */
937 dd_emit(ctx, 1, 0x80); /* 000000ff UNK12B0_3 */
938 dd_emit(ctx, 1, 0); /* 000000ff UNK12B0_2 */
939 dd_emit(ctx, 1, 0); /* 0000000f FP_TEXTURES_LOG2 */
940 dd_emit(ctx, 1, 0); /* 0000000f FP_SAMPLERS_LOG2 */
941 if (IS_NVA3F(device->chipset)) {
942 dd_emit(ctx, 1, 0); /* ffffffff */
943 dd_emit(ctx, 1, 0); /* 0000007f MULTISAMPLE_SAMPLES_LOG2 */
944 } else {
945 dd_emit(ctx, 1, 0); /* 0000000f MULTISAMPLE_SAMPLES_LOG2 */
946 }
947 dd_emit(ctx, 1, 0xc); /* 000000ff SEMANTIC_COLOR.BFC0_ID */
948 if (device->chipset != 0x50)
949 dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_COLOR.CLMP_EN */
950 dd_emit(ctx, 1, 8); /* 000000ff SEMANTIC_COLOR.COLR_NR */
951 dd_emit(ctx, 1, 0x14); /* 000000ff SEMANTIC_COLOR.FFC0_ID */
952 if (device->chipset == 0x50) {
953 dd_emit(ctx, 1, 0); /* 000000ff SEMANTIC_LAYER */
954 dd_emit(ctx, 1, 0); /* 00000001 */
955 } else {
956 dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_PTSZ.ENABLE */
957 dd_emit(ctx, 1, 0x29); /* 000000ff SEMANTIC_PTSZ.PTSZ_ID */
958 dd_emit(ctx, 1, 0x27); /* 000000ff SEMANTIC_PRIM */
959 dd_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */
960 dd_emit(ctx, 1, 8); /* 0000000f SMENATIC_CLIP.CLIP_HIGH */
961 dd_emit(ctx, 1, 4); /* 000000ff SEMANTIC_CLIP.CLIP_LO */
962 dd_emit(ctx, 1, 0x27); /* 000000ff UNK0FD4 */
963 dd_emit(ctx, 1, 0); /* 00000001 UNK1900 */
964 }
965 dd_emit(ctx, 1, 0); /* 00000007 RT_CONTROL_MAP0 */
966 dd_emit(ctx, 1, 1); /* 00000007 RT_CONTROL_MAP1 */
967 dd_emit(ctx, 1, 2); /* 00000007 RT_CONTROL_MAP2 */
968 dd_emit(ctx, 1, 3); /* 00000007 RT_CONTROL_MAP3 */
969 dd_emit(ctx, 1, 4); /* 00000007 RT_CONTROL_MAP4 */
970 dd_emit(ctx, 1, 5); /* 00000007 RT_CONTROL_MAP5 */
971 dd_emit(ctx, 1, 6); /* 00000007 RT_CONTROL_MAP6 */
972 dd_emit(ctx, 1, 7); /* 00000007 RT_CONTROL_MAP7 */
973 dd_emit(ctx, 1, 1); /* 0000000f RT_CONTROL_COUNT */
974 dd_emit(ctx, 8, 0); /* 00000001 RT_HORIZ_UNK */
975 dd_emit(ctx, 8, 0); /* ffffffff RT_ADDRESS_LOW */
976 dd_emit(ctx, 1, 0xcf); /* 000000ff RT_FORMAT */
977 dd_emit(ctx, 7, 0); /* 000000ff RT_FORMAT */
978 if (device->chipset != 0x50)
979 dd_emit(ctx, 3, 0); /* 1, 1, 1 */
980 else
981 dd_emit(ctx, 2, 0); /* 1, 1 */
982 dd_emit(ctx, 1, 0); /* ffffffff GP_ENABLE */
983 dd_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT*/
984 dd_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */
985 dd_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
986 if (IS_NVA3F(device->chipset)) {
987 dd_emit(ctx, 1, 3); /* 00000003 */
988 dd_emit(ctx, 1, 0); /* 00000001 UNK1418. Alone. */
989 }
990 if (device->chipset != 0x50)
991 dd_emit(ctx, 1, 3); /* 00000003 UNK15AC */
992 dd_emit(ctx, 1, 1); /* ffffffff RASTERIZE_ENABLE */
993 dd_emit(ctx, 1, 0); /* 00000001 FP_CONTROL.EXPORTS_Z */
994 if (device->chipset != 0x50)
995 dd_emit(ctx, 1, 0); /* 00000001 FP_CONTROL.MULTIPLE_RESULTS */
996 dd_emit(ctx, 1, 0x12); /* 000000ff FP_INTERPOLANT_CTRL.COUNT */
997 dd_emit(ctx, 1, 0x10); /* 000000ff FP_INTERPOLANT_CTRL.COUNT_NONFLAT */
998 dd_emit(ctx, 1, 0xc); /* 000000ff FP_INTERPOLANT_CTRL.OFFSET */
999 dd_emit(ctx, 1, 1); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.W */
1000 dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.X */
1001 dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.Y */
1002 dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.Z */
1003 dd_emit(ctx, 1, 4); /* 000000ff FP_RESULT_COUNT */
1004 dd_emit(ctx, 1, 2); /* ffffffff REG_MODE */
1005 dd_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */
1006 if (device->chipset >= 0xa0)
1007 dd_emit(ctx, 1, 0); /* ffffffff */
1008 dd_emit(ctx, 1, 0); /* 00000001 GP_BUILTIN_RESULT_EN.LAYER_IDX */
1009 dd_emit(ctx, 1, 0); /* ffffffff STRMOUT_ENABLE */
1010 dd_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */
1011 dd_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */
1012 dd_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE*/
1013 if (device->chipset != 0x50)
1014 dd_emit(ctx, 8, 0); /* 00000001 */
1015 if (device->chipset >= 0xa0) {
1016 dd_emit(ctx, 1, 1); /* 00000007 VTX_ATTR_DEFINE.COMP */
1017 dd_emit(ctx, 1, 1); /* 00000007 VTX_ATTR_DEFINE.SIZE */
1018 dd_emit(ctx, 1, 2); /* 00000007 VTX_ATTR_DEFINE.TYPE */
1019 dd_emit(ctx, 1, 0); /* 000000ff VTX_ATTR_DEFINE.ATTR */
1020 }
1021 dd_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
1022 dd_emit(ctx, 1, 0x14); /* 0000001f ZETA_FORMAT */
1023 dd_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
1024 dd_emit(ctx, 1, 0); /* 0000000f VP_TEXTURES_LOG2 */
1025 dd_emit(ctx, 1, 0); /* 0000000f VP_SAMPLERS_LOG2 */
1026 if (IS_NVA3F(device->chipset))
1027 dd_emit(ctx, 1, 0); /* 00000001 */
1028 dd_emit(ctx, 1, 2); /* 00000003 POLYGON_MODE_BACK */
1029 if (device->chipset >= 0xa0)
1030 dd_emit(ctx, 1, 0); /* 00000003 VTX_ATTR_DEFINE.SIZE - 1 */
1031 dd_emit(ctx, 1, 0); /* 0000ffff CB_ADDR_INDEX */
1032 if (device->chipset >= 0xa0)
1033 dd_emit(ctx, 1, 0); /* 00000003 */
1034 dd_emit(ctx, 1, 0); /* 00000001 CULL_FACE_ENABLE */
1035 dd_emit(ctx, 1, 1); /* 00000003 CULL_FACE */
1036 dd_emit(ctx, 1, 0); /* 00000001 FRONT_FACE */
1037 dd_emit(ctx, 1, 2); /* 00000003 POLYGON_MODE_FRONT */
1038 dd_emit(ctx, 1, 0x1000); /* 00007fff UNK141C */
1039 if (device->chipset != 0x50) {
1040 dd_emit(ctx, 1, 0xe00); /* 7fff */
1041 dd_emit(ctx, 1, 0x1000); /* 7fff */
1042 dd_emit(ctx, 1, 0x1e00); /* 7fff */
1043 }
1044 dd_emit(ctx, 1, 0); /* 00000001 BEGIN_END_ACTIVE */
1045 dd_emit(ctx, 1, 1); /* 00000001 POLYGON_MODE_??? */
1046 dd_emit(ctx, 1, 1); /* 000000ff GP_REG_ALLOC_TEMP / 4 rounded up */
1047 dd_emit(ctx, 1, 1); /* 000000ff FP_REG_ALLOC_TEMP... without /4? */
1048 dd_emit(ctx, 1, 1); /* 000000ff VP_REG_ALLOC_TEMP / 4 rounded up */
1049 dd_emit(ctx, 1, 1); /* 00000001 */
1050 dd_emit(ctx, 1, 0); /* 00000001 */
1051 dd_emit(ctx, 1, 0); /* 00000001 VTX_ATTR_MASK_UNK0 nonempty */
1052 dd_emit(ctx, 1, 0); /* 00000001 VTX_ATTR_MASK_UNK1 nonempty */
1053 dd_emit(ctx, 1, 0x200); /* 0003ffff GP_VERTEX_OUTPUT_COUNT*GP_REG_ALLOC_RESULT */
1054 if (IS_NVA3F(device->chipset))
1055 dd_emit(ctx, 1, 0x200);
1056 dd_emit(ctx, 1, 0); /* 00000001 */
1057 if (device->chipset < 0xa0) {
1058 dd_emit(ctx, 1, 1); /* 00000001 */
1059 dd_emit(ctx, 1, 0x70); /* 000000ff */
1060 dd_emit(ctx, 1, 0x80); /* 000000ff */
1061 dd_emit(ctx, 1, 0); /* 000000ff */
1062 dd_emit(ctx, 1, 0); /* 00000001 */
1063 dd_emit(ctx, 1, 1); /* 00000001 */
1064 dd_emit(ctx, 1, 0x70); /* 000000ff */
1065 dd_emit(ctx, 1, 0x80); /* 000000ff */
1066 dd_emit(ctx, 1, 0); /* 000000ff */
1067 } else {
1068 dd_emit(ctx, 1, 1); /* 00000001 */
1069 dd_emit(ctx, 1, 0xf0); /* 000000ff */
1070 dd_emit(ctx, 1, 0xff); /* 000000ff */
1071 dd_emit(ctx, 1, 0); /* 000000ff */
1072 dd_emit(ctx, 1, 0); /* 00000001 */
1073 dd_emit(ctx, 1, 1); /* 00000001 */
1074 dd_emit(ctx, 1, 0xf0); /* 000000ff */
1075 dd_emit(ctx, 1, 0xff); /* 000000ff */
1076 dd_emit(ctx, 1, 0); /* 000000ff */
1077 dd_emit(ctx, 1, 9); /* 0000003f UNK114C.COMP,SIZE */
1078 }
1079
1080 /* eng2d state */
1081 dd_emit(ctx, 1, 0); /* 00000001 eng2d COLOR_KEY_ENABLE */
1082 dd_emit(ctx, 1, 0); /* 00000007 eng2d COLOR_KEY_FORMAT */
1083 dd_emit(ctx, 1, 1); /* ffffffff eng2d DST_DEPTH */
1084 dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d DST_FORMAT */
1085 dd_emit(ctx, 1, 0); /* ffffffff eng2d DST_LAYER */
1086 dd_emit(ctx, 1, 1); /* 00000001 eng2d DST_LINEAR */
1087 dd_emit(ctx, 1, 0); /* 00000007 eng2d PATTERN_COLOR_FORMAT */
1088 dd_emit(ctx, 1, 0); /* 00000007 eng2d OPERATION */
1089 dd_emit(ctx, 1, 0); /* 00000003 eng2d PATTERN_SELECT */
1090 dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d SIFC_FORMAT */
1091 dd_emit(ctx, 1, 0); /* 00000001 eng2d SIFC_BITMAP_ENABLE */
1092 dd_emit(ctx, 1, 2); /* 00000003 eng2d SIFC_BITMAP_UNK808 */
1093 dd_emit(ctx, 1, 0); /* ffffffff eng2d BLIT_DU_DX_FRACT */
1094 dd_emit(ctx, 1, 1); /* ffffffff eng2d BLIT_DU_DX_INT */
1095 dd_emit(ctx, 1, 0); /* ffffffff eng2d BLIT_DV_DY_FRACT */
1096 dd_emit(ctx, 1, 1); /* ffffffff eng2d BLIT_DV_DY_INT */
1097 dd_emit(ctx, 1, 0); /* 00000001 eng2d BLIT_CONTROL_FILTER */
1098 dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d DRAW_COLOR_FORMAT */
1099 dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d SRC_FORMAT */
1100 dd_emit(ctx, 1, 1); /* 00000001 eng2d SRC_LINEAR #2 */
1101
1102 num = ctx->ctxvals_pos - base;
1103 ctx->ctxvals_pos = base;
1104 if (IS_NVA3F(device->chipset))
1105 cp_ctx(ctx, 0x404800, num);
1106 else
1107 cp_ctx(ctx, 0x405400, num);
1108 }
1109
1110 /*
1111 * xfer areas. These are a pain.
1112 *
1113 * There are 2 xfer areas: the first one is big and contains all sorts of
1114 * stuff, the second is small and contains some per-TP context.
1115 *
1116 * Each area is split into 8 "strands". The areas, when saved to grctx,
1117 * are made of 8-word blocks. Each block contains a single word from
1118 * each strand. The strands are independent of each other, their
1119 * addresses are unrelated to each other, and data in them is closely
1120 * packed together. The strand layout varies a bit between cards: here
1121 * and there, a single word is thrown out in the middle and the whole
1122 * strand is offset by a bit from corresponding one on another chipset.
1123 * For this reason, addresses of stuff in strands are almost useless.
1124 * Knowing sequence of stuff and size of gaps between them is much more
1125 * useful, and that's how we build the strands in our generator.
1126 *
1127 * NVA0 takes this mess to a whole new level by cutting the old strands
1128 * into a few dozen pieces [known as genes], rearranging them randomly,
1129 * and putting them back together to make new strands. Hopefully these
1130 * genes correspond more or less directly to the same PGRAPH subunits
1131 * as in 400040 register.
1132 *
1133 * The most common value in default context is 0, and when the genes
1134 * are separated by 0's, gene bounduaries are quite speculative...
1135 * some of them can be clearly deduced, others can be guessed, and yet
1136 * others won't be resolved without figuring out the real meaning of
1137 * given ctxval. For the same reason, ending point of each strand
1138 * is unknown. Except for strand 0, which is the longest strand and
1139 * its end corresponds to end of the whole xfer.
1140 *
1141 * An unsolved mystery is the seek instruction: it takes an argument
1142 * in bits 8-18, and that argument is clearly the place in strands to
1143 * seek to... but the offsets don't seem to correspond to offsets as
1144 * seen in grctx. Perhaps there's another, real, not randomly-changing
1145 * addressing in strands, and the xfer insn just happens to skip over
1146 * the unused bits? NV10-NV30 PIPE comes to mind...
1147 *
1148 * As far as I know, there's no way to access the xfer areas directly
1149 * without the help of ctxprog.
1150 */
1151
1152 static void
1153 xf_emit(struct nouveau_grctx *ctx, int num, u32 val) {
1154 int i;
1155 if (val && ctx->mode == NOUVEAU_GRCTX_VALS)
1156 for (i = 0; i < num; i++)
1157 nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + (i << 3)), val);
1158 ctx->ctxvals_pos += num << 3;
1159 }
1160
1161 /* Gene declarations... */
1162
1163 static void nv50_graph_construct_gene_dispatch(struct nouveau_grctx *ctx);
1164 static void nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx);
1165 static void nv50_graph_construct_gene_ccache(struct nouveau_grctx *ctx);
1166 static void nv50_graph_construct_gene_unk10xx(struct nouveau_grctx *ctx);
1167 static void nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx);
1168 static void nv50_graph_construct_gene_zcull(struct nouveau_grctx *ctx);
1169 static void nv50_graph_construct_gene_clipid(struct nouveau_grctx *ctx);
1170 static void nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx);
1171 static void nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx);
1172 static void nv50_graph_construct_gene_eng2d(struct nouveau_grctx *ctx);
1173 static void nv50_graph_construct_gene_csched(struct nouveau_grctx *ctx);
1174 static void nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx);
1175 static void nv50_graph_construct_gene_strmout(struct nouveau_grctx *ctx);
1176 static void nv50_graph_construct_gene_unk34xx(struct nouveau_grctx *ctx);
1177 static void nv50_graph_construct_gene_ropm1(struct nouveau_grctx *ctx);
1178 static void nv50_graph_construct_gene_ropm2(struct nouveau_grctx *ctx);
1179 static void nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx);
1180 static void nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx);
1181
1182 static void
1183 nv50_graph_construct_xfer1(struct nouveau_grctx *ctx)
1184 {
1185 struct nouveau_device *device = ctx->device;
1186 int i;
1187 int offset;
1188 int size = 0;
1189 u32 units = nv_rd32 (ctx->device, 0x1540);
1190
1191 offset = (ctx->ctxvals_pos+0x3f)&~0x3f;
1192 ctx->ctxvals_base = offset;
1193
1194 if (device->chipset < 0xa0) {
1195 /* Strand 0 */
1196 ctx->ctxvals_pos = offset;
1197 nv50_graph_construct_gene_dispatch(ctx);
1198 nv50_graph_construct_gene_m2mf(ctx);
1199 nv50_graph_construct_gene_unk24xx(ctx);
1200 nv50_graph_construct_gene_clipid(ctx);
1201 nv50_graph_construct_gene_zcull(ctx);
1202 if ((ctx->ctxvals_pos-offset)/8 > size)
1203 size = (ctx->ctxvals_pos-offset)/8;
1204
1205 /* Strand 1 */
1206 ctx->ctxvals_pos = offset + 0x1;
1207 nv50_graph_construct_gene_vfetch(ctx);
1208 nv50_graph_construct_gene_eng2d(ctx);
1209 nv50_graph_construct_gene_csched(ctx);
1210 nv50_graph_construct_gene_ropm1(ctx);
1211 nv50_graph_construct_gene_ropm2(ctx);
1212 if ((ctx->ctxvals_pos-offset)/8 > size)
1213 size = (ctx->ctxvals_pos-offset)/8;
1214
1215 /* Strand 2 */
1216 ctx->ctxvals_pos = offset + 0x2;
1217 nv50_graph_construct_gene_ccache(ctx);
1218 nv50_graph_construct_gene_unk1cxx(ctx);
1219 nv50_graph_construct_gene_strmout(ctx);
1220 nv50_graph_construct_gene_unk14xx(ctx);
1221 nv50_graph_construct_gene_unk10xx(ctx);
1222 nv50_graph_construct_gene_unk34xx(ctx);
1223 if ((ctx->ctxvals_pos-offset)/8 > size)
1224 size = (ctx->ctxvals_pos-offset)/8;
1225
1226 /* Strand 3: per-ROP group state */
1227 ctx->ctxvals_pos = offset + 3;
1228 for (i = 0; i < 6; i++)
1229 if (units & (1 << (i + 16)))
1230 nv50_graph_construct_gene_ropc(ctx);
1231 if ((ctx->ctxvals_pos-offset)/8 > size)
1232 size = (ctx->ctxvals_pos-offset)/8;
1233
1234 /* Strands 4-7: per-TP state */
1235 for (i = 0; i < 4; i++) {
1236 ctx->ctxvals_pos = offset + 4 + i;
1237 if (units & (1 << (2 * i)))
1238 nv50_graph_construct_xfer_tp(ctx);
1239 if (units & (1 << (2 * i + 1)))
1240 nv50_graph_construct_xfer_tp(ctx);
1241 if ((ctx->ctxvals_pos-offset)/8 > size)
1242 size = (ctx->ctxvals_pos-offset)/8;
1243 }
1244 } else {
1245 /* Strand 0 */
1246 ctx->ctxvals_pos = offset;
1247 nv50_graph_construct_gene_dispatch(ctx);
1248 nv50_graph_construct_gene_m2mf(ctx);
1249 nv50_graph_construct_gene_unk34xx(ctx);
1250 nv50_graph_construct_gene_csched(ctx);
1251 nv50_graph_construct_gene_unk1cxx(ctx);
1252 nv50_graph_construct_gene_strmout(ctx);
1253 if ((ctx->ctxvals_pos-offset)/8 > size)
1254 size = (ctx->ctxvals_pos-offset)/8;
1255
1256 /* Strand 1 */
1257 ctx->ctxvals_pos = offset + 1;
1258 nv50_graph_construct_gene_unk10xx(ctx);
1259 if ((ctx->ctxvals_pos-offset)/8 > size)
1260 size = (ctx->ctxvals_pos-offset)/8;
1261
1262 /* Strand 2 */
1263 ctx->ctxvals_pos = offset + 2;
1264 if (device->chipset == 0xa0)
1265 nv50_graph_construct_gene_unk14xx(ctx);
1266 nv50_graph_construct_gene_unk24xx(ctx);
1267 if ((ctx->ctxvals_pos-offset)/8 > size)
1268 size = (ctx->ctxvals_pos-offset)/8;
1269
1270 /* Strand 3 */
1271 ctx->ctxvals_pos = offset + 3;
1272 nv50_graph_construct_gene_vfetch(ctx);
1273 if ((ctx->ctxvals_pos-offset)/8 > size)
1274 size = (ctx->ctxvals_pos-offset)/8;
1275
1276 /* Strand 4 */
1277 ctx->ctxvals_pos = offset + 4;
1278 nv50_graph_construct_gene_ccache(ctx);
1279 if ((ctx->ctxvals_pos-offset)/8 > size)
1280 size = (ctx->ctxvals_pos-offset)/8;
1281
1282 /* Strand 5 */
1283 ctx->ctxvals_pos = offset + 5;
1284 nv50_graph_construct_gene_ropm2(ctx);
1285 nv50_graph_construct_gene_ropm1(ctx);
1286 /* per-ROP context */
1287 for (i = 0; i < 8; i++)
1288 if (units & (1<<(i+16)))
1289 nv50_graph_construct_gene_ropc(ctx);
1290 if ((ctx->ctxvals_pos-offset)/8 > size)
1291 size = (ctx->ctxvals_pos-offset)/8;
1292
1293 /* Strand 6 */
1294 ctx->ctxvals_pos = offset + 6;
1295 nv50_graph_construct_gene_zcull(ctx);
1296 nv50_graph_construct_gene_clipid(ctx);
1297 nv50_graph_construct_gene_eng2d(ctx);
1298 if (units & (1 << 0))
1299 nv50_graph_construct_xfer_tp(ctx);
1300 if (units & (1 << 1))
1301 nv50_graph_construct_xfer_tp(ctx);
1302 if (units & (1 << 2))
1303 nv50_graph_construct_xfer_tp(ctx);
1304 if (units & (1 << 3))
1305 nv50_graph_construct_xfer_tp(ctx);
1306 if ((ctx->ctxvals_pos-offset)/8 > size)
1307 size = (ctx->ctxvals_pos-offset)/8;
1308
1309 /* Strand 7 */
1310 ctx->ctxvals_pos = offset + 7;
1311 if (device->chipset == 0xa0) {
1312 if (units & (1 << 4))
1313 nv50_graph_construct_xfer_tp(ctx);
1314 if (units & (1 << 5))
1315 nv50_graph_construct_xfer_tp(ctx);
1316 if (units & (1 << 6))
1317 nv50_graph_construct_xfer_tp(ctx);
1318 if (units & (1 << 7))
1319 nv50_graph_construct_xfer_tp(ctx);
1320 if (units & (1 << 8))
1321 nv50_graph_construct_xfer_tp(ctx);
1322 if (units & (1 << 9))
1323 nv50_graph_construct_xfer_tp(ctx);
1324 } else {
1325 nv50_graph_construct_gene_unk14xx(ctx);
1326 }
1327 if ((ctx->ctxvals_pos-offset)/8 > size)
1328 size = (ctx->ctxvals_pos-offset)/8;
1329 }
1330
1331 ctx->ctxvals_pos = offset + size * 8;
1332 ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f;
1333 cp_lsr (ctx, offset);
1334 cp_out (ctx, CP_SET_XFER_POINTER);
1335 cp_lsr (ctx, size);
1336 cp_out (ctx, CP_SEEK_1);
1337 cp_out (ctx, CP_XFER_1);
1338 cp_wait(ctx, XFER, BUSY);
1339 }
1340
1341 /*
1342 * non-trivial demagiced parts of ctx init go here
1343 */
1344
1345 static void
1346 nv50_graph_construct_gene_dispatch(struct nouveau_grctx *ctx)
1347 {
1348 /* start of strand 0 */
1349 struct nouveau_device *device = ctx->device;
1350 /* SEEK */
1351 if (device->chipset == 0x50)
1352 xf_emit(ctx, 5, 0);
1353 else if (!IS_NVA3F(device->chipset))
1354 xf_emit(ctx, 6, 0);
1355 else
1356 xf_emit(ctx, 4, 0);
1357 /* SEEK */
1358 /* the PGRAPH's internal FIFO */
1359 if (device->chipset == 0x50)
1360 xf_emit(ctx, 8*3, 0);
1361 else
1362 xf_emit(ctx, 0x100*3, 0);
1363 /* and another bonus slot?!? */
1364 xf_emit(ctx, 3, 0);
1365 /* and YET ANOTHER bonus slot? */
1366 if (IS_NVA3F(device->chipset))
1367 xf_emit(ctx, 3, 0);
1368 /* SEEK */
1369 /* CTX_SWITCH: caches of gr objects bound to subchannels. 8 values, last used index */
1370 xf_emit(ctx, 9, 0);
1371 /* SEEK */
1372 xf_emit(ctx, 9, 0);
1373 /* SEEK */
1374 xf_emit(ctx, 9, 0);
1375 /* SEEK */
1376 xf_emit(ctx, 9, 0);
1377 /* SEEK */
1378 if (device->chipset < 0x90)
1379 xf_emit(ctx, 4, 0);
1380 /* SEEK */
1381 xf_emit(ctx, 2, 0);
1382 /* SEEK */
1383 xf_emit(ctx, 6*2, 0);
1384 xf_emit(ctx, 2, 0);
1385 /* SEEK */
1386 xf_emit(ctx, 2, 0);
1387 /* SEEK */
1388 xf_emit(ctx, 6*2, 0);
1389 xf_emit(ctx, 2, 0);
1390 /* SEEK */
1391 if (device->chipset == 0x50)
1392 xf_emit(ctx, 0x1c, 0);
1393 else if (device->chipset < 0xa0)
1394 xf_emit(ctx, 0x1e, 0);
1395 else
1396 xf_emit(ctx, 0x22, 0);
1397 /* SEEK */
1398 xf_emit(ctx, 0x15, 0);
1399 }
1400
1401 static void
1402 nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx)
1403 {
1404 /* Strand 0, right after dispatch */
1405 struct nouveau_device *device = ctx->device;
1406 int smallm2mf = 0;
1407 if (device->chipset < 0x92 || device->chipset == 0x98)
1408 smallm2mf = 1;
1409 /* SEEK */
1410 xf_emit (ctx, 1, 0); /* DMA_NOTIFY instance >> 4 */
1411 xf_emit (ctx, 1, 0); /* DMA_BUFFER_IN instance >> 4 */
1412 xf_emit (ctx, 1, 0); /* DMA_BUFFER_OUT instance >> 4 */
1413 xf_emit (ctx, 1, 0); /* OFFSET_IN */
1414 xf_emit (ctx, 1, 0); /* OFFSET_OUT */
1415 xf_emit (ctx, 1, 0); /* PITCH_IN */
1416 xf_emit (ctx, 1, 0); /* PITCH_OUT */
1417 xf_emit (ctx, 1, 0); /* LINE_LENGTH */
1418 xf_emit (ctx, 1, 0); /* LINE_COUNT */
1419 xf_emit (ctx, 1, 0x21); /* FORMAT: bits 0-4 INPUT_INC, bits 5-9 OUTPUT_INC */
1420 xf_emit (ctx, 1, 1); /* LINEAR_IN */
1421 xf_emit (ctx, 1, 0x2); /* TILING_MODE_IN: bits 0-2 y tiling, bits 3-5 z tiling */
1422 xf_emit (ctx, 1, 0x100); /* TILING_PITCH_IN */
1423 xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_IN */
1424 xf_emit (ctx, 1, 1); /* TILING_DEPTH_IN */
1425 xf_emit (ctx, 1, 0); /* TILING_POSITION_IN_Z */
1426 xf_emit (ctx, 1, 0); /* TILING_POSITION_IN */
1427 xf_emit (ctx, 1, 1); /* LINEAR_OUT */
1428 xf_emit (ctx, 1, 0x2); /* TILING_MODE_OUT: bits 0-2 y tiling, bits 3-5 z tiling */
1429 xf_emit (ctx, 1, 0x100); /* TILING_PITCH_OUT */
1430 xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_OUT */
1431 xf_emit (ctx, 1, 1); /* TILING_DEPTH_OUT */
1432 xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT_Z */
1433 xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT */
1434 xf_emit (ctx, 1, 0); /* OFFSET_IN_HIGH */
1435 xf_emit (ctx, 1, 0); /* OFFSET_OUT_HIGH */
1436 /* SEEK */
1437 if (smallm2mf)
1438 xf_emit(ctx, 0x40, 0); /* 20 * ffffffff, 3ffff */
1439 else
1440 xf_emit(ctx, 0x100, 0); /* 80 * ffffffff, 3ffff */
1441 xf_emit(ctx, 4, 0); /* 1f/7f, 0, 1f/7f, 0 [1f for smallm2mf, 7f otherwise] */
1442 /* SEEK */
1443 if (smallm2mf)
1444 xf_emit(ctx, 0x400, 0); /* ffffffff */
1445 else
1446 xf_emit(ctx, 0x800, 0); /* ffffffff */
1447 xf_emit(ctx, 4, 0); /* ff/1ff, 0, 0, 0 [ff for smallm2mf, 1ff otherwise] */
1448 /* SEEK */
1449 xf_emit(ctx, 0x40, 0); /* 20 * bits ffffffff, 3ffff */
1450 xf_emit(ctx, 0x6, 0); /* 1f, 0, 1f, 0, 1f, 0 */
1451 }
1452
1453 static void
1454 nv50_graph_construct_gene_ccache(struct nouveau_grctx *ctx)
1455 {
1456 struct nouveau_device *device = ctx->device;
1457 xf_emit(ctx, 2, 0); /* RO */
1458 xf_emit(ctx, 0x800, 0); /* ffffffff */
1459 switch (device->chipset) {
1460 case 0x50:
1461 case 0x92:
1462 case 0xa0:
1463 xf_emit(ctx, 0x2b, 0);
1464 break;
1465 case 0x84:
1466 xf_emit(ctx, 0x29, 0);
1467 break;
1468 case 0x94:
1469 case 0x96:
1470 case 0xa3:
1471 xf_emit(ctx, 0x27, 0);
1472 break;
1473 case 0x86:
1474 case 0x98:
1475 case 0xa5:
1476 case 0xa8:
1477 case 0xaa:
1478 case 0xac:
1479 case 0xaf:
1480 xf_emit(ctx, 0x25, 0);
1481 break;
1482 }
1483 /* CB bindings, 0x80 of them. first word is address >> 8, second is
1484 * size >> 4 | valid << 24 */
1485 xf_emit(ctx, 0x100, 0); /* ffffffff CB_DEF */
1486 xf_emit(ctx, 1, 0); /* 0000007f CB_ADDR_BUFFER */
1487 xf_emit(ctx, 1, 0); /* 0 */
1488 xf_emit(ctx, 0x30, 0); /* ff SET_PROGRAM_CB */
1489 xf_emit(ctx, 1, 0); /* 3f last SET_PROGRAM_CB */
1490 xf_emit(ctx, 4, 0); /* RO */
1491 xf_emit(ctx, 0x100, 0); /* ffffffff */
1492 xf_emit(ctx, 8, 0); /* 1f, 0, 0, ... */
1493 xf_emit(ctx, 8, 0); /* ffffffff */
1494 xf_emit(ctx, 4, 0); /* ffffffff */
1495 xf_emit(ctx, 1, 0); /* 3 */
1496 xf_emit(ctx, 1, 0); /* ffffffff */
1497 xf_emit(ctx, 1, 0); /* 0000ffff DMA_CODE_CB */
1498 xf_emit(ctx, 1, 0); /* 0000ffff DMA_TIC */
1499 xf_emit(ctx, 1, 0); /* 0000ffff DMA_TSC */
1500 xf_emit(ctx, 1, 0); /* 00000001 LINKED_TSC */
1501 xf_emit(ctx, 1, 0); /* 000000ff TIC_ADDRESS_HIGH */
1502 xf_emit(ctx, 1, 0); /* ffffffff TIC_ADDRESS_LOW */
1503 xf_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */
1504 xf_emit(ctx, 1, 0); /* 000000ff TSC_ADDRESS_HIGH */
1505 xf_emit(ctx, 1, 0); /* ffffffff TSC_ADDRESS_LOW */
1506 xf_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */
1507 xf_emit(ctx, 1, 0); /* 000000ff VP_ADDRESS_HIGH */
1508 xf_emit(ctx, 1, 0); /* ffffffff VP_ADDRESS_LOW */
1509 xf_emit(ctx, 1, 0); /* 00ffffff VP_START_ID */
1510 xf_emit(ctx, 1, 0); /* 000000ff CB_DEF_ADDRESS_HIGH */
1511 xf_emit(ctx, 1, 0); /* ffffffff CB_DEF_ADDRESS_LOW */
1512 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1513 xf_emit(ctx, 1, 0); /* 000000ff GP_ADDRESS_HIGH */
1514 xf_emit(ctx, 1, 0); /* ffffffff GP_ADDRESS_LOW */
1515 xf_emit(ctx, 1, 0); /* 00ffffff GP_START_ID */
1516 xf_emit(ctx, 1, 0); /* 000000ff FP_ADDRESS_HIGH */
1517 xf_emit(ctx, 1, 0); /* ffffffff FP_ADDRESS_LOW */
1518 xf_emit(ctx, 1, 0); /* 00ffffff FP_START_ID */
1519 }
1520
1521 static void
1522 nv50_graph_construct_gene_unk10xx(struct nouveau_grctx *ctx)
1523 {
1524 struct nouveau_device *device = ctx->device;
1525 int i;
1526 /* end of area 2 on pre-NVA0, area 1 on NVAx */
1527 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
1528 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
1529 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1530 xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */
1531 xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */
1532 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */
1533 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */
1534 if (device->chipset == 0x50)
1535 xf_emit(ctx, 1, 0x3ff);
1536 else
1537 xf_emit(ctx, 1, 0x7ff); /* 000007ff */
1538 xf_emit(ctx, 1, 0); /* 111/113 */
1539 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
1540 for (i = 0; i < 8; i++) {
1541 switch (device->chipset) {
1542 case 0x50:
1543 case 0x86:
1544 case 0x98:
1545 case 0xaa:
1546 case 0xac:
1547 xf_emit(ctx, 0xa0, 0); /* ffffffff */
1548 break;
1549 case 0x84:
1550 case 0x92:
1551 case 0x94:
1552 case 0x96:
1553 xf_emit(ctx, 0x120, 0);
1554 break;
1555 case 0xa5:
1556 case 0xa8:
1557 xf_emit(ctx, 0x100, 0); /* ffffffff */
1558 break;
1559 case 0xa0:
1560 case 0xa3:
1561 case 0xaf:
1562 xf_emit(ctx, 0x400, 0); /* ffffffff */
1563 break;
1564 }
1565 xf_emit(ctx, 4, 0); /* 3f, 0, 0, 0 */
1566 xf_emit(ctx, 4, 0); /* ffffffff */
1567 }
1568 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
1569 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
1570 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1571 xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */
1572 xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_TEMP */
1573 xf_emit(ctx, 1, 1); /* 00000001 RASTERIZE_ENABLE */
1574 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
1575 xf_emit(ctx, 1, 0x27); /* 000000ff UNK0FD4 */
1576 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */
1577 xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */
1578 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
1579 }
1580
1581 static void
1582 nv50_graph_construct_gene_unk34xx(struct nouveau_grctx *ctx)
1583 {
1584 struct nouveau_device *device = ctx->device;
1585 /* end of area 2 on pre-NVA0, area 1 on NVAx */
1586 xf_emit(ctx, 1, 0); /* 00000001 VIEWPORT_CLIP_RECTS_EN */
1587 xf_emit(ctx, 1, 0); /* 00000003 VIEWPORT_CLIP_MODE */
1588 xf_emit(ctx, 0x10, 0x04000000); /* 07ffffff VIEWPORT_CLIP_HORIZ*8, VIEWPORT_CLIP_VERT*8 */
1589 xf_emit(ctx, 1, 0); /* 00000001 POLYGON_STIPPLE_ENABLE */
1590 xf_emit(ctx, 0x20, 0); /* ffffffff POLYGON_STIPPLE */
1591 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */
1592 xf_emit(ctx, 1, 0); /* ffff0ff3 */
1593 xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0D64 */
1594 xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0DF4 */
1595 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */
1596 xf_emit(ctx, 1, 0); /* 00000007 */
1597 xf_emit(ctx, 1, 0x1fe21); /* 0001ffff tesla UNK0FAC */
1598 if (device->chipset >= 0xa0)
1599 xf_emit(ctx, 1, 0x0fac6881);
1600 if (IS_NVA3F(device->chipset)) {
1601 xf_emit(ctx, 1, 1);
1602 xf_emit(ctx, 3, 0);
1603 }
1604 }
1605
1606 static void
1607 nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx)
1608 {
1609 struct nouveau_device *device = ctx->device;
1610 /* middle of area 2 on pre-NVA0, beginning of area 2 on NVA0, area 7 on >NVA0 */
1611 if (device->chipset != 0x50) {
1612 xf_emit(ctx, 5, 0); /* ffffffff */
1613 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */
1614 xf_emit(ctx, 1, 0); /* 00000001 */
1615 xf_emit(ctx, 1, 0); /* 000003ff */
1616 xf_emit(ctx, 1, 0x804); /* 00000fff SEMANTIC_CLIP */
1617 xf_emit(ctx, 1, 0); /* 00000001 */
1618 xf_emit(ctx, 2, 4); /* 7f, ff */
1619 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
1620 }
1621 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
1622 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
1623 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
1624 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1625 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */
1626 xf_emit(ctx, 1, 0); /* 000000ff VP_CLIP_DISTANCE_ENABLE */
1627 if (device->chipset != 0x50)
1628 xf_emit(ctx, 1, 0); /* 3ff */
1629 xf_emit(ctx, 1, 0); /* 000000ff tesla UNK1940 */
1630 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0D7C */
1631 xf_emit(ctx, 1, 0x804); /* 00000fff SEMANTIC_CLIP */
1632 xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */
1633 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */
1634 if (device->chipset != 0x50)
1635 xf_emit(ctx, 1, 0x7f); /* 000000ff tesla UNK0FFC */
1636 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
1637 xf_emit(ctx, 1, 1); /* 00000001 SHADE_MODEL */
1638 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */
1639 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
1640 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
1641 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
1642 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
1643 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1644 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */
1645 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0D7C */
1646 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0F8C */
1647 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
1648 xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */
1649 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
1650 xf_emit(ctx, 4, 0); /* ffffffff NOPERSPECTIVE_BITMAP */
1651 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
1652 xf_emit(ctx, 1, 0); /* 0000000f */
1653 if (device->chipset == 0x50)
1654 xf_emit(ctx, 1, 0x3ff); /* 000003ff tesla UNK0D68 */
1655 else
1656 xf_emit(ctx, 1, 0x7ff); /* 000007ff tesla UNK0D68 */
1657 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */
1658 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */
1659 xf_emit(ctx, 0x30, 0); /* ffffffff VIEWPORT_SCALE: X0, Y0, Z0, X1, Y1, ... */
1660 xf_emit(ctx, 3, 0); /* f, 0, 0 */
1661 xf_emit(ctx, 3, 0); /* ffffffff last VIEWPORT_SCALE? */
1662 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
1663 xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */
1664 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
1665 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */
1666 xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */
1667 xf_emit(ctx, 1, 0); /* 00000001 */
1668 xf_emit(ctx, 0x30, 0); /* ffffffff VIEWPORT_TRANSLATE */
1669 xf_emit(ctx, 3, 0); /* f, 0, 0 */
1670 xf_emit(ctx, 3, 0); /* ffffffff */
1671 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
1672 xf_emit(ctx, 2, 0x88); /* 000001ff tesla UNK19D8 */
1673 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */
1674 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
1675 xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */
1676 xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */
1677 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */
1678 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */
1679 xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */
1680 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */
1681 xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */
1682 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
1683 xf_emit(ctx, 1, 0); /* 0000000f */
1684 xf_emit(ctx, 1, 0x3f800000); /* ffffffff LINE_WIDTH */
1685 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */
1686 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */
1687 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
1688 if (IS_NVA3F(device->chipset))
1689 xf_emit(ctx, 1, 0); /* 00000001 */
1690 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */
1691 xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */
1692 if (device->chipset != 0x50) {
1693 xf_emit(ctx, 1, 0); /* ffffffff */
1694 xf_emit(ctx, 1, 0); /* 00000001 */
1695 xf_emit(ctx, 1, 0); /* 000003ff */
1696 }
1697 xf_emit(ctx, 0x20, 0); /* 10xbits ffffffff, 3fffff. SCISSOR_* */
1698 xf_emit(ctx, 1, 0); /* f */
1699 xf_emit(ctx, 1, 0); /* 0? */
1700 xf_emit(ctx, 1, 0); /* ffffffff */
1701 xf_emit(ctx, 1, 0); /* 003fffff */
1702 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
1703 xf_emit(ctx, 1, 0x52); /* 000001ff SEMANTIC_PTSZ */
1704 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */
1705 xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */
1706 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
1707 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
1708 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
1709 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1710 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */
1711 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */
1712 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */
1713 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */
1714 xf_emit(ctx, 1, 0); /* 0000000f */
1715 }
1716
1717 static void
1718 nv50_graph_construct_gene_zcull(struct nouveau_grctx *ctx)
1719 {
1720 struct nouveau_device *device = ctx->device;
1721 /* end of strand 0 on pre-NVA0, beginning of strand 6 on NVAx */
1722 /* SEEK */
1723 xf_emit(ctx, 1, 0x3f); /* 0000003f UNK1590 */
1724 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */
1725 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
1726 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
1727 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */
1728 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */
1729 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */
1730 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */
1731 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */
1732 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */
1733 xf_emit(ctx, 2, 0x04000000); /* 07ffffff tesla UNK0D6C */
1734 xf_emit(ctx, 1, 0); /* ffff0ff3 */
1735 xf_emit(ctx, 1, 0); /* 00000001 CLIPID_ENABLE */
1736 xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */
1737 xf_emit(ctx, 1, 0); /* 00000001 */
1738 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */
1739 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
1740 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
1741 xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */
1742 xf_emit(ctx, 1, 0); /* 0000ffff */
1743 xf_emit(ctx, 1, 0); /* 00000001 UNK0FB0 */
1744 xf_emit(ctx, 1, 0); /* 00000001 POLYGON_STIPPLE_ENABLE */
1745 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */
1746 xf_emit(ctx, 1, 0); /* ffffffff */
1747 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */
1748 xf_emit(ctx, 1, 0); /* 000000ff CLEAR_STENCIL */
1749 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */
1750 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */
1751 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */
1752 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */
1753 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */
1754 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
1755 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */
1756 xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */
1757 xf_emit(ctx, 1, 0); /* 00000007 */
1758 if (device->chipset != 0x50)
1759 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1108 */
1760 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */
1761 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
1762 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
1763 xf_emit(ctx, 1, 0x1001); /* 00001fff ZETA_ARRAY_MODE */
1764 /* SEEK */
1765 xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */
1766 xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */
1767 xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */
1768 xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */
1769 xf_emit(ctx, 1, 0x10); /* 7f/ff/3ff VIEW_VOLUME_CLIP_CTRL */
1770 xf_emit(ctx, 1, 0); /* 00000001 VIEWPORT_CLIP_RECTS_EN */
1771 xf_emit(ctx, 1, 3); /* 00000003 FP_CTRL_UNK196C */
1772 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1968 */
1773 if (device->chipset != 0x50)
1774 xf_emit(ctx, 1, 0); /* 0fffffff tesla UNK1104 */
1775 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK151C */
1776 }
1777
1778 static void
1779 nv50_graph_construct_gene_clipid(struct nouveau_grctx *ctx)
1780 {
1781 /* middle of strand 0 on pre-NVA0 [after 24xx], middle of area 6 on NVAx */
1782 /* SEEK */
1783 xf_emit(ctx, 1, 0); /* 00000007 UNK0FB4 */
1784 /* SEEK */
1785 xf_emit(ctx, 4, 0); /* 07ffffff CLIPID_REGION_HORIZ */
1786 xf_emit(ctx, 4, 0); /* 07ffffff CLIPID_REGION_VERT */
1787 xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */
1788 xf_emit(ctx, 2, 0x04000000); /* 07ffffff UNK1508 */
1789 xf_emit(ctx, 1, 0); /* 00000001 CLIPID_ENABLE */
1790 xf_emit(ctx, 1, 0x80); /* 00003fff CLIPID_WIDTH */
1791 xf_emit(ctx, 1, 0); /* 000000ff CLIPID_ID */
1792 xf_emit(ctx, 1, 0); /* 000000ff CLIPID_ADDRESS_HIGH */
1793 xf_emit(ctx, 1, 0); /* ffffffff CLIPID_ADDRESS_LOW */
1794 xf_emit(ctx, 1, 0x80); /* 00003fff CLIPID_HEIGHT */
1795 xf_emit(ctx, 1, 0); /* 0000ffff DMA_CLIPID */
1796 }
1797
1798 static void
1799 nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx)
1800 {
1801 struct nouveau_device *device = ctx->device;
1802 int i;
1803 /* middle of strand 0 on pre-NVA0 [after m2mf], end of strand 2 on NVAx */
1804 /* SEEK */
1805 xf_emit(ctx, 0x33, 0);
1806 /* SEEK */
1807 xf_emit(ctx, 2, 0);
1808 /* SEEK */
1809 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1810 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
1811 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
1812 /* SEEK */
1813 if (IS_NVA3F(device->chipset)) {
1814 xf_emit(ctx, 4, 0); /* RO */
1815 xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */
1816 xf_emit(ctx, 1, 0); /* 1ff */
1817 xf_emit(ctx, 8, 0); /* 0? */
1818 xf_emit(ctx, 9, 0); /* ffffffff, 7ff */
1819
1820 xf_emit(ctx, 4, 0); /* RO */
1821 xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */
1822 xf_emit(ctx, 1, 0); /* 1ff */
1823 xf_emit(ctx, 8, 0); /* 0? */
1824 xf_emit(ctx, 9, 0); /* ffffffff, 7ff */
1825 } else {
1826 xf_emit(ctx, 0xc, 0); /* RO */
1827 /* SEEK */
1828 xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */
1829 xf_emit(ctx, 1, 0); /* 1ff */
1830 xf_emit(ctx, 8, 0); /* 0? */
1831
1832 /* SEEK */
1833 xf_emit(ctx, 0xc, 0); /* RO */
1834 /* SEEK */
1835 xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */
1836 xf_emit(ctx, 1, 0); /* 1ff */
1837 xf_emit(ctx, 8, 0); /* 0? */
1838 }
1839 /* SEEK */
1840 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1841 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
1842 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
1843 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
1844 if (device->chipset != 0x50)
1845 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */
1846 /* SEEK */
1847 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1848 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
1849 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */
1850 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */
1851 xf_emit(ctx, 1, 1); /* 00000001 */
1852 /* SEEK */
1853 if (device->chipset >= 0xa0)
1854 xf_emit(ctx, 2, 4); /* 000000ff */
1855 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */
1856 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */
1857 xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */
1858 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
1859 xf_emit(ctx, 1, 0x27); /* 000000ff SEMANTIC_PRIM_ID */
1860 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1861 xf_emit(ctx, 1, 0); /* 0000000f */
1862 xf_emit(ctx, 1, 1); /* 00000001 */
1863 for (i = 0; i < 10; i++) {
1864 /* SEEK */
1865 xf_emit(ctx, 0x40, 0); /* ffffffff */
1866 xf_emit(ctx, 0x10, 0); /* 3, 0, 0.... */
1867 xf_emit(ctx, 0x10, 0); /* ffffffff */
1868 }
1869 /* SEEK */
1870 xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_CTRL */
1871 xf_emit(ctx, 1, 1); /* 00000001 */
1872 xf_emit(ctx, 1, 0); /* ffffffff */
1873 xf_emit(ctx, 4, 0); /* ffffffff NOPERSPECTIVE_BITMAP */
1874 xf_emit(ctx, 0x10, 0); /* 00ffffff POINT_COORD_REPLACE_MAP */
1875 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */
1876 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
1877 if (device->chipset != 0x50)
1878 xf_emit(ctx, 1, 0); /* 000003ff */
1879 }
1880
1881 static void
1882 nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx)
1883 {
1884 struct nouveau_device *device = ctx->device;
1885 int acnt = 0x10, rep, i;
1886 /* beginning of strand 1 on pre-NVA0, strand 3 on NVAx */
1887 if (IS_NVA3F(device->chipset))
1888 acnt = 0x20;
1889 /* SEEK */
1890 if (device->chipset >= 0xa0) {
1891 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK13A4 */
1892 xf_emit(ctx, 1, 1); /* 00000fff tesla UNK1318 */
1893 }
1894 xf_emit(ctx, 1, 0); /* ffffffff VERTEX_BUFFER_FIRST */
1895 xf_emit(ctx, 1, 0); /* 00000001 PRIMITIVE_RESTART_ENABLE */
1896 xf_emit(ctx, 1, 0); /* 00000001 UNK0DE8 */
1897 xf_emit(ctx, 1, 0); /* ffffffff PRIMITIVE_RESTART_INDEX */
1898 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */
1899 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */
1900 xf_emit(ctx, acnt/8, 0); /* ffffffff VTX_ATR_MASK_UNK0DD0 */
1901 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */
1902 xf_emit(ctx, 1, 0x20); /* 0000ffff tesla UNK129C */
1903 xf_emit(ctx, 1, 0); /* 000000ff turing UNK370??? */
1904 xf_emit(ctx, 1, 0); /* 0000ffff turing USER_PARAM_COUNT */
1905 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
1906 /* SEEK */
1907 if (IS_NVA3F(device->chipset))
1908 xf_emit(ctx, 0xb, 0); /* RO */
1909 else if (device->chipset >= 0xa0)
1910 xf_emit(ctx, 0x9, 0); /* RO */
1911 else
1912 xf_emit(ctx, 0x8, 0); /* RO */
1913 /* SEEK */
1914 xf_emit(ctx, 1, 0); /* 00000001 EDGE_FLAG */
1915 xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */
1916 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1917 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */
1918 /* SEEK */
1919 xf_emit(ctx, 0xc, 0); /* RO */
1920 /* SEEK */
1921 xf_emit(ctx, 1, 0); /* 7f/ff */
1922 xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */
1923 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */
1924 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */
1925 xf_emit(ctx, 1, 4); /* 000001ff UNK1A28 */
1926 xf_emit(ctx, 1, 8); /* 000001ff UNK0DF0 */
1927 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1928 if (device->chipset == 0x50)
1929 xf_emit(ctx, 1, 0x3ff); /* 3ff tesla UNK0D68 */
1930 else
1931 xf_emit(ctx, 1, 0x7ff); /* 7ff tesla UNK0D68 */
1932 if (device->chipset == 0xa8)
1933 xf_emit(ctx, 1, 0x1e00); /* 7fff */
1934 /* SEEK */
1935 xf_emit(ctx, 0xc, 0); /* RO or close */
1936 /* SEEK */
1937 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */
1938 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */
1939 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */
1940 if (device->chipset > 0x50 && device->chipset < 0xa0)
1941 xf_emit(ctx, 2, 0); /* ffffffff */
1942 else
1943 xf_emit(ctx, 1, 0); /* ffffffff */
1944 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0FD8 */
1945 /* SEEK */
1946 if (IS_NVA3F(device->chipset)) {
1947 xf_emit(ctx, 0x10, 0); /* 0? */
1948 xf_emit(ctx, 2, 0); /* weird... */
1949 xf_emit(ctx, 2, 0); /* RO */
1950 } else {
1951 xf_emit(ctx, 8, 0); /* 0? */
1952 xf_emit(ctx, 1, 0); /* weird... */
1953 xf_emit(ctx, 2, 0); /* RO */
1954 }
1955 /* SEEK */
1956 xf_emit(ctx, 1, 0); /* ffffffff VB_ELEMENT_BASE */
1957 xf_emit(ctx, 1, 0); /* ffffffff UNK1438 */
1958 xf_emit(ctx, acnt, 0); /* 1 tesla UNK1000 */
1959 if (device->chipset >= 0xa0)
1960 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1118? */
1961 /* SEEK */
1962 xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_UNK90C */
1963 xf_emit(ctx, 1, 0); /* f/1f */
1964 /* SEEK */
1965 xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_UNK90C */
1966 xf_emit(ctx, 1, 0); /* f/1f */
1967 /* SEEK */
1968 xf_emit(ctx, acnt, 0); /* RO */
1969 xf_emit(ctx, 2, 0); /* RO */
1970 /* SEEK */
1971 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK111C? */
1972 xf_emit(ctx, 1, 0); /* RO */
1973 /* SEEK */
1974 xf_emit(ctx, 1, 0); /* 000000ff UNK15F4_ADDRESS_HIGH */
1975 xf_emit(ctx, 1, 0); /* ffffffff UNK15F4_ADDRESS_LOW */
1976 xf_emit(ctx, 1, 0); /* 000000ff UNK0F84_ADDRESS_HIGH */
1977 xf_emit(ctx, 1, 0); /* ffffffff UNK0F84_ADDRESS_LOW */
1978 /* SEEK */
1979 xf_emit(ctx, acnt, 0); /* 00003fff VERTEX_ARRAY_ATTRIB_OFFSET */
1980 xf_emit(ctx, 3, 0); /* f/1f */
1981 /* SEEK */
1982 xf_emit(ctx, acnt, 0); /* 00000fff VERTEX_ARRAY_STRIDE */
1983 xf_emit(ctx, 3, 0); /* f/1f */
1984 /* SEEK */
1985 xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_LOW */
1986 xf_emit(ctx, 3, 0); /* f/1f */
1987 /* SEEK */
1988 xf_emit(ctx, acnt, 0); /* 000000ff VERTEX_ARRAY_HIGH */
1989 xf_emit(ctx, 3, 0); /* f/1f */
1990 /* SEEK */
1991 xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_LIMIT_LOW */
1992 xf_emit(ctx, 3, 0); /* f/1f */
1993 /* SEEK */
1994 xf_emit(ctx, acnt, 0); /* 000000ff VERTEX_LIMIT_HIGH */
1995 xf_emit(ctx, 3, 0); /* f/1f */
1996 /* SEEK */
1997 if (IS_NVA3F(device->chipset)) {
1998 xf_emit(ctx, acnt, 0); /* f */
1999 xf_emit(ctx, 3, 0); /* f/1f */
2000 }
2001 /* SEEK */
2002 if (IS_NVA3F(device->chipset))
2003 xf_emit(ctx, 2, 0); /* RO */
2004 else
2005 xf_emit(ctx, 5, 0); /* RO */
2006 /* SEEK */
2007 xf_emit(ctx, 1, 0); /* ffff DMA_VTXBUF */
2008 /* SEEK */
2009 if (device->chipset < 0xa0) {
2010 xf_emit(ctx, 0x41, 0); /* RO */
2011 /* SEEK */
2012 xf_emit(ctx, 0x11, 0); /* RO */
2013 } else if (!IS_NVA3F(device->chipset))
2014 xf_emit(ctx, 0x50, 0); /* RO */
2015 else
2016 xf_emit(ctx, 0x58, 0); /* RO */
2017 /* SEEK */
2018 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */
2019 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */
2020 xf_emit(ctx, 1, 1); /* 1 UNK0DEC */
2021 /* SEEK */
2022 xf_emit(ctx, acnt*4, 0); /* ffffffff VTX_ATTR */
2023 xf_emit(ctx, 4, 0); /* f/1f, 0, 0, 0 */
2024 /* SEEK */
2025 if (IS_NVA3F(device->chipset))
2026 xf_emit(ctx, 0x1d, 0); /* RO */
2027 else
2028 xf_emit(ctx, 0x16, 0); /* RO */
2029 /* SEEK */
2030 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */
2031 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */
2032 /* SEEK */
2033 if (device->chipset < 0xa0)
2034 xf_emit(ctx, 8, 0); /* RO */
2035 else if (IS_NVA3F(device->chipset))
2036 xf_emit(ctx, 0xc, 0); /* RO */
2037 else
2038 xf_emit(ctx, 7, 0); /* RO */
2039 /* SEEK */
2040 xf_emit(ctx, 0xa, 0); /* RO */
2041 if (device->chipset == 0xa0)
2042 rep = 0xc;
2043 else
2044 rep = 4;
2045 for (i = 0; i < rep; i++) {
2046 /* SEEK */
2047 if (IS_NVA3F(device->chipset))
2048 xf_emit(ctx, 0x20, 0); /* ffffffff */
2049 xf_emit(ctx, 0x200, 0); /* ffffffff */
2050 xf_emit(ctx, 4, 0); /* 7f/ff, 0, 0, 0 */
2051 xf_emit(ctx, 4, 0); /* ffffffff */
2052 }
2053 /* SEEK */
2054 xf_emit(ctx, 1, 0); /* 113/111 */
2055 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */
2056 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */
2057 xf_emit(ctx, acnt/8, 0); /* ffffffff VTX_ATTR_MASK_UNK0DD0 */
2058 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */
2059 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
2060 /* SEEK */
2061 if (IS_NVA3F(device->chipset))
2062 xf_emit(ctx, 7, 0); /* weird... */
2063 else
2064 xf_emit(ctx, 5, 0); /* weird... */
2065 }
2066
2067 static void
2068 nv50_graph_construct_gene_eng2d(struct nouveau_grctx *ctx)
2069 {
2070 struct nouveau_device *device = ctx->device;
2071 /* middle of strand 1 on pre-NVA0 [after vfetch], middle of strand 6 on NVAx */
2072 /* SEEK */
2073 xf_emit(ctx, 2, 0); /* 0001ffff CLIP_X, CLIP_Y */
2074 xf_emit(ctx, 2, 0); /* 0000ffff CLIP_W, CLIP_H */
2075 xf_emit(ctx, 1, 0); /* 00000001 CLIP_ENABLE */
2076 if (device->chipset < 0xa0) {
2077 /* this is useless on everything but the original NV50,
2078 * guess they forgot to nuke it. Or just didn't bother. */
2079 xf_emit(ctx, 2, 0); /* 0000ffff IFC_CLIP_X, Y */
2080 xf_emit(ctx, 2, 1); /* 0000ffff IFC_CLIP_W, H */
2081 xf_emit(ctx, 1, 0); /* 00000001 IFC_CLIP_ENABLE */
2082 }
2083 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */
2084 xf_emit(ctx, 1, 0x100); /* 0001ffff DST_WIDTH */
2085 xf_emit(ctx, 1, 0x100); /* 0001ffff DST_HEIGHT */
2086 xf_emit(ctx, 1, 0x11); /* 3f[NV50]/7f[NV84+] DST_FORMAT */
2087 xf_emit(ctx, 1, 0); /* 0001ffff DRAW_POINT_X */
2088 xf_emit(ctx, 1, 8); /* 0000000f DRAW_UNK58C */
2089 xf_emit(ctx, 1, 0); /* 000fffff SIFC_DST_X_FRACT */
2090 xf_emit(ctx, 1, 0); /* 0001ffff SIFC_DST_X_INT */
2091 xf_emit(ctx, 1, 0); /* 000fffff SIFC_DST_Y_FRACT */
2092 xf_emit(ctx, 1, 0); /* 0001ffff SIFC_DST_Y_INT */
2093 xf_emit(ctx, 1, 0); /* 000fffff SIFC_DX_DU_FRACT */
2094 xf_emit(ctx, 1, 1); /* 0001ffff SIFC_DX_DU_INT */
2095 xf_emit(ctx, 1, 0); /* 000fffff SIFC_DY_DV_FRACT */
2096 xf_emit(ctx, 1, 1); /* 0001ffff SIFC_DY_DV_INT */
2097 xf_emit(ctx, 1, 1); /* 0000ffff SIFC_WIDTH */
2098 xf_emit(ctx, 1, 1); /* 0000ffff SIFC_HEIGHT */
2099 xf_emit(ctx, 1, 0xcf); /* 000000ff SIFC_FORMAT */
2100 xf_emit(ctx, 1, 2); /* 00000003 SIFC_BITMAP_UNK808 */
2101 xf_emit(ctx, 1, 0); /* 00000003 SIFC_BITMAP_LINE_PACK_MODE */
2102 xf_emit(ctx, 1, 0); /* 00000001 SIFC_BITMAP_LSB_FIRST */
2103 xf_emit(ctx, 1, 0); /* 00000001 SIFC_BITMAP_ENABLE */
2104 xf_emit(ctx, 1, 0); /* 0000ffff BLIT_DST_X */
2105 xf_emit(ctx, 1, 0); /* 0000ffff BLIT_DST_Y */
2106 xf_emit(ctx, 1, 0); /* 000fffff BLIT_DU_DX_FRACT */
2107 xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DU_DX_INT */
2108 xf_emit(ctx, 1, 0); /* 000fffff BLIT_DV_DY_FRACT */
2109 xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DV_DY_INT */
2110 xf_emit(ctx, 1, 1); /* 0000ffff BLIT_DST_W */
2111 xf_emit(ctx, 1, 1); /* 0000ffff BLIT_DST_H */
2112 xf_emit(ctx, 1, 0); /* 000fffff BLIT_SRC_X_FRACT */
2113 xf_emit(ctx, 1, 0); /* 0001ffff BLIT_SRC_X_INT */
2114 xf_emit(ctx, 1, 0); /* 000fffff BLIT_SRC_Y_FRACT */
2115 xf_emit(ctx, 1, 0); /* 00000001 UNK888 */
2116 xf_emit(ctx, 1, 4); /* 0000003f UNK884 */
2117 xf_emit(ctx, 1, 0); /* 00000007 UNK880 */
2118 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK0FB8 */
2119 xf_emit(ctx, 1, 0x15); /* 000000ff tesla UNK128C */
2120 xf_emit(ctx, 2, 0); /* 00000007, ffff0ff3 */
2121 xf_emit(ctx, 1, 0); /* 00000001 UNK260 */
2122 xf_emit(ctx, 1, 0x4444480); /* 1fffffff UNK870 */
2123 /* SEEK */
2124 xf_emit(ctx, 0x10, 0);
2125 /* SEEK */
2126 xf_emit(ctx, 0x27, 0);
2127 }
2128
2129 static void
2130 nv50_graph_construct_gene_csched(struct nouveau_grctx *ctx)
2131 {
2132 struct nouveau_device *device = ctx->device;
2133 /* middle of strand 1 on pre-NVA0 [after eng2d], middle of strand 0 on NVAx */
2134 /* SEEK */
2135 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY... what is it doing here??? */
2136 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */
2137 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */
2138 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
2139 xf_emit(ctx, 1, 0); /* 000003ff */
2140 /* SEEK */
2141 xf_emit(ctx, 1, 0); /* ffffffff turing UNK364 */
2142 xf_emit(ctx, 1, 0); /* 0000000f turing UNK36C */
2143 xf_emit(ctx, 1, 0); /* 0000ffff USER_PARAM_COUNT */
2144 xf_emit(ctx, 1, 0x100); /* 00ffffff turing UNK384 */
2145 xf_emit(ctx, 1, 0); /* 0000000f turing UNK2A0 */
2146 xf_emit(ctx, 1, 0); /* 0000ffff GRIDID */
2147 xf_emit(ctx, 1, 0x10001); /* ffffffff GRIDDIM_XY */
2148 xf_emit(ctx, 1, 0); /* ffffffff */
2149 xf_emit(ctx, 1, 0x10001); /* ffffffff BLOCKDIM_XY */
2150 xf_emit(ctx, 1, 1); /* 0000ffff BLOCKDIM_Z */
2151 xf_emit(ctx, 1, 0x10001); /* 00ffffff BLOCK_ALLOC */
2152 xf_emit(ctx, 1, 1); /* 00000001 LANES32 */
2153 xf_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */
2154 xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */
2155 /* SEEK */
2156 xf_emit(ctx, 0x40, 0); /* ffffffff USER_PARAM */
2157 switch (device->chipset) {
2158 case 0x50:
2159 case 0x92:
2160 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */
2161 xf_emit(ctx, 0x80, 0); /* fff */
2162 xf_emit(ctx, 2, 0); /* ff, fff */
2163 xf_emit(ctx, 0x10*2, 0); /* ffffffff, 1f */
2164 break;
2165 case 0x84:
2166 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */
2167 xf_emit(ctx, 0x60, 0); /* fff */
2168 xf_emit(ctx, 2, 0); /* ff, fff */
2169 xf_emit(ctx, 0xc*2, 0); /* ffffffff, 1f */
2170 break;
2171 case 0x94:
2172 case 0x96:
2173 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */
2174 xf_emit(ctx, 0x40, 0); /* fff */
2175 xf_emit(ctx, 2, 0); /* ff, fff */
2176 xf_emit(ctx, 8*2, 0); /* ffffffff, 1f */
2177 break;
2178 case 0x86:
2179 case 0x98:
2180 xf_emit(ctx, 4, 0); /* f, 0, 0, 0 */
2181 xf_emit(ctx, 0x10, 0); /* fff */
2182 xf_emit(ctx, 2, 0); /* ff, fff */
2183 xf_emit(ctx, 2*2, 0); /* ffffffff, 1f */
2184 break;
2185 case 0xa0:
2186 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */
2187 xf_emit(ctx, 0xf0, 0); /* fff */
2188 xf_emit(ctx, 2, 0); /* ff, fff */
2189 xf_emit(ctx, 0x1e*2, 0); /* ffffffff, 1f */
2190 break;
2191 case 0xa3:
2192 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */
2193 xf_emit(ctx, 0x60, 0); /* fff */
2194 xf_emit(ctx, 2, 0); /* ff, fff */
2195 xf_emit(ctx, 0xc*2, 0); /* ffffffff, 1f */
2196 break;
2197 case 0xa5:
2198 case 0xaf:
2199 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */
2200 xf_emit(ctx, 0x30, 0); /* fff */
2201 xf_emit(ctx, 2, 0); /* ff, fff */
2202 xf_emit(ctx, 6*2, 0); /* ffffffff, 1f */
2203 break;
2204 case 0xaa:
2205 xf_emit(ctx, 0x12, 0);
2206 break;
2207 case 0xa8:
2208 case 0xac:
2209 xf_emit(ctx, 4, 0); /* f, 0, 0, 0 */
2210 xf_emit(ctx, 0x10, 0); /* fff */
2211 xf_emit(ctx, 2, 0); /* ff, fff */
2212 xf_emit(ctx, 2*2, 0); /* ffffffff, 1f */
2213 break;
2214 }
2215 xf_emit(ctx, 1, 0); /* 0000000f */
2216 xf_emit(ctx, 1, 0); /* 00000000 */
2217 xf_emit(ctx, 1, 0); /* ffffffff */
2218 xf_emit(ctx, 1, 0); /* 0000001f */
2219 xf_emit(ctx, 4, 0); /* ffffffff */
2220 xf_emit(ctx, 1, 0); /* 00000003 turing UNK35C */
2221 xf_emit(ctx, 1, 0); /* ffffffff */
2222 xf_emit(ctx, 4, 0); /* ffffffff */
2223 xf_emit(ctx, 1, 0); /* 00000003 turing UNK35C */
2224 xf_emit(ctx, 1, 0); /* ffffffff */
2225 xf_emit(ctx, 1, 0); /* 000000ff */
2226 }
2227
2228 static void
2229 nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx)
2230 {
2231 struct nouveau_device *device = ctx->device;
2232 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */
2233 xf_emit(ctx, 1, 0x3f800000); /* ffffffff LINE_WIDTH */
2234 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */
2235 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1658 */
2236 xf_emit(ctx, 1, 0); /* 00000001 POLYGON_SMOOTH_ENABLE */
2237 xf_emit(ctx, 3, 0); /* 00000001 POLYGON_OFFSET_*_ENABLE */
2238 xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */
2239 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */
2240 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
2241 xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */
2242 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK165C */
2243 xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */
2244 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
2245 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */
2246 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */
2247 xf_emit(ctx, 1, 0); /* ffffffff POLYGON_OFFSET_UNITS */
2248 xf_emit(ctx, 1, 0); /* ffffffff POLYGON_OFFSET_FACTOR */
2249 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1668 */
2250 xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */
2251 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
2252 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */
2253 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */
2254 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
2255 xf_emit(ctx, 1, 0x11); /* 0000007f RT_FORMAT */
2256 xf_emit(ctx, 7, 0); /* 0000007f RT_FORMAT */
2257 xf_emit(ctx, 8, 0); /* 00000001 RT_HORIZ_LINEAR */
2258 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */
2259 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */
2260 xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */
2261 if (IS_NVA3F(device->chipset))
2262 xf_emit(ctx, 1, 3); /* 00000003 UNK16B4 */
2263 else if (device->chipset >= 0xa0)
2264 xf_emit(ctx, 1, 1); /* 00000001 UNK16B4 */
2265 xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */
2266 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0F90 */
2267 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */
2268 xf_emit(ctx, 2, 0x04000000); /* 07ffffff tesla UNK0D6C */
2269 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */
2270 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
2271 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */
2272 xf_emit(ctx, 1, 5); /* 0000000f UNK1408 */
2273 xf_emit(ctx, 1, 0x52); /* 000001ff SEMANTIC_PTSZ */
2274 xf_emit(ctx, 1, 0); /* ffffffff POINT_SIZE */
2275 xf_emit(ctx, 1, 0); /* 00000001 */
2276 xf_emit(ctx, 1, 0); /* 00000007 tesla UNK0FB4 */
2277 if (device->chipset != 0x50) {
2278 xf_emit(ctx, 1, 0); /* 3ff */
2279 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK1110 */
2280 }
2281 if (IS_NVA3F(device->chipset))
2282 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1928 */
2283 xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */
2284 xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */
2285 xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */
2286 xf_emit(ctx, 0x20, 0); /* 07ffffff VIEWPORT_HORIZ, then VIEWPORT_VERT. (W&0x3fff)<<13 | (X&0x1fff). */
2287 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK187C */
2288 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */
2289 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
2290 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
2291 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */
2292 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */
2293 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
2294 xf_emit(ctx, 1, 5); /* 0000000f tesla UNK1220 */
2295 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
2296 xf_emit(ctx, 1, 0); /* 000000ff tesla UNK1A20 */
2297 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
2298 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */
2299 xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */
2300 if (device->chipset != 0x50)
2301 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */
2302 if (device->chipset < 0xa0)
2303 xf_emit(ctx, 0x1c, 0); /* RO */
2304 else if (IS_NVA3F(device->chipset))
2305 xf_emit(ctx, 0x9, 0);
2306 xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */
2307 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */
2308 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */
2309 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */
2310 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */
2311 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */
2312 if (device->chipset != 0x50) {
2313 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */
2314 xf_emit(ctx, 1, 0); /* 3ff */
2315 }
2316 /* XXX: the following block could belong either to unk1cxx, or
2317 * to STRMOUT. Rather hard to tell. */
2318 if (device->chipset < 0xa0)
2319 xf_emit(ctx, 0x25, 0);
2320 else
2321 xf_emit(ctx, 0x3b, 0);
2322 }
2323
2324 static void
2325 nv50_graph_construct_gene_strmout(struct nouveau_grctx *ctx)
2326 {
2327 struct nouveau_device *device = ctx->device;
2328 xf_emit(ctx, 1, 0x102); /* 0000ffff STRMOUT_BUFFER_CTRL */
2329 xf_emit(ctx, 1, 0); /* ffffffff STRMOUT_PRIMITIVE_COUNT */
2330 xf_emit(ctx, 4, 4); /* 000000ff STRMOUT_NUM_ATTRIBS */
2331 if (device->chipset >= 0xa0) {
2332 xf_emit(ctx, 4, 0); /* ffffffff UNK1A8C */
2333 xf_emit(ctx, 4, 0); /* ffffffff UNK1780 */
2334 }
2335 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
2336 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
2337 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
2338 if (device->chipset == 0x50)
2339 xf_emit(ctx, 1, 0x3ff); /* 000003ff tesla UNK0D68 */
2340 else
2341 xf_emit(ctx, 1, 0x7ff); /* 000007ff tesla UNK0D68 */
2342 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
2343 /* SEEK */
2344 xf_emit(ctx, 1, 0x102); /* 0000ffff STRMOUT_BUFFER_CTRL */
2345 xf_emit(ctx, 1, 0); /* ffffffff STRMOUT_PRIMITIVE_COUNT */
2346 xf_emit(ctx, 4, 0); /* 000000ff STRMOUT_ADDRESS_HIGH */
2347 xf_emit(ctx, 4, 0); /* ffffffff STRMOUT_ADDRESS_LOW */
2348 xf_emit(ctx, 4, 4); /* 000000ff STRMOUT_NUM_ATTRIBS */
2349 if (device->chipset >= 0xa0) {
2350 xf_emit(ctx, 4, 0); /* ffffffff UNK1A8C */
2351 xf_emit(ctx, 4, 0); /* ffffffff UNK1780 */
2352 }
2353 xf_emit(ctx, 1, 0); /* 0000ffff DMA_STRMOUT */
2354 xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */
2355 xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */
2356 xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW QUERY_COUNTER */
2357 xf_emit(ctx, 2, 0); /* ffffffff */
2358 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
2359 /* SEEK */
2360 xf_emit(ctx, 0x20, 0); /* ffffffff STRMOUT_MAP */
2361 xf_emit(ctx, 1, 0); /* 0000000f */
2362 xf_emit(ctx, 1, 0); /* 00000000? */
2363 xf_emit(ctx, 2, 0); /* ffffffff */
2364 }
2365
2366 static void
2367 nv50_graph_construct_gene_ropm1(struct nouveau_grctx *ctx)
2368 {
2369 struct nouveau_device *device = ctx->device;
2370 xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0D64 */
2371 xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0DF4 */
2372 xf_emit(ctx, 1, 0); /* 00000007 */
2373 xf_emit(ctx, 1, 0); /* 000003ff */
2374 if (IS_NVA3F(device->chipset))
2375 xf_emit(ctx, 1, 0x11); /* 000000ff tesla UNK1968 */
2376 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
2377 }
2378
2379 static void
2380 nv50_graph_construct_gene_ropm2(struct nouveau_grctx *ctx)
2381 {
2382 struct nouveau_device *device = ctx->device;
2383 /* SEEK */
2384 xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */
2385 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
2386 xf_emit(ctx, 2, 0); /* ffffffff */
2387 xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */
2388 xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW, COUNTER */
2389 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */
2390 xf_emit(ctx, 1, 0); /* 7 */
2391 /* SEEK */
2392 xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */
2393 xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */
2394 xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW, COUNTER */
2395 xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0D64 */
2396 xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0DF4 */
2397 xf_emit(ctx, 1, 0); /* 00000001 eng2d UNK260 */
2398 xf_emit(ctx, 1, 0); /* ff/3ff */
2399 xf_emit(ctx, 1, 0); /* 00000007 */
2400 if (IS_NVA3F(device->chipset))
2401 xf_emit(ctx, 1, 0x11); /* 000000ff tesla UNK1968 */
2402 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
2403 }
2404
2405 static void
2406 nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx)
2407 {
2408 struct nouveau_device *device = ctx->device;
2409 int magic2;
2410 if (device->chipset == 0x50) {
2411 magic2 = 0x00003e60;
2412 } else if (!IS_NVA3F(device->chipset)) {
2413 magic2 = 0x001ffe67;
2414 } else {
2415 magic2 = 0x00087e67;
2416 }
2417 xf_emit(ctx, 1, 0); /* f/7 MUTISAMPLE_SAMPLES_LOG2 */
2418 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
2419 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */
2420 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */
2421 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */
2422 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */
2423 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */
2424 xf_emit(ctx, 1, 0); /* ffff0ff3 */
2425 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */
2426 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
2427 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */
2428 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
2429 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
2430 if (IS_NVA3F(device->chipset))
2431 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
2432 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */
2433 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */
2434 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */
2435 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */
2436 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
2437 if (device->chipset >= 0xa0 && !IS_NVAAF(device->chipset))
2438 xf_emit(ctx, 1, 0x15); /* 000000ff */
2439 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */
2440 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */
2441 xf_emit(ctx, 1, 0x10); /* 3ff/ff VIEW_VOLUME_CLIP_CTRL */
2442 xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */
2443 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
2444 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
2445 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
2446 if (device->chipset == 0x86 || device->chipset == 0x92 || device->chipset == 0x98 || device->chipset >= 0xa0) {
2447 xf_emit(ctx, 3, 0); /* ff, ffffffff, ffffffff */
2448 xf_emit(ctx, 1, 4); /* 7 */
2449 xf_emit(ctx, 1, 0x400); /* fffffff */
2450 xf_emit(ctx, 1, 0x300); /* ffff */
2451 xf_emit(ctx, 1, 0x1001); /* 1fff */
2452 if (device->chipset != 0xa0) {
2453 if (IS_NVA3F(device->chipset))
2454 xf_emit(ctx, 1, 0); /* 0000000f UNK15C8 */
2455 else
2456 xf_emit(ctx, 1, 0x15); /* ff */
2457 }
2458 }
2459 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
2460 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
2461 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */
2462 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */
2463 xf_emit(ctx, 1, 0); /* ffff0ff3 */
2464 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */
2465 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
2466 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */
2467 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
2468 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
2469 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */
2470 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */
2471 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
2472 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */
2473 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */
2474 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */
2475 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
2476 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
2477 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
2478 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
2479 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
2480 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */
2481 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */
2482 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */
2483 xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */
2484 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
2485 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */
2486 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
2487 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
2488 xf_emit(ctx, 1, 0); /* 0000000f */
2489 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */
2490 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */
2491 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */
2492 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */
2493 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
2494 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */
2495 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */
2496 xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */
2497 xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */
2498 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
2499 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
2500 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */
2501 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */
2502 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */
2503 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */
2504 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */
2505 xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */
2506 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
2507 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */
2508 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
2509 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
2510 xf_emit(ctx, 1, 0); /* 000000ff CLEAR_STENCIL */
2511 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */
2512 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */
2513 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */
2514 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */
2515 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */
2516 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
2517 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */
2518 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */
2519 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
2520 xf_emit(ctx, 1, 0x3f); /* 0000003f UNK1590 */
2521 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
2522 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
2523 xf_emit(ctx, 2, 0); /* ffff0ff3, ffff */
2524 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */
2525 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */
2526 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */
2527 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
2528 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
2529 xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */
2530 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */
2531 if (device->chipset >= 0xa0) {
2532 xf_emit(ctx, 2, 0);
2533 xf_emit(ctx, 1, 0x1001);
2534 xf_emit(ctx, 0xb, 0);
2535 } else {
2536 xf_emit(ctx, 1, 0); /* 00000007 */
2537 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
2538 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
2539 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */
2540 xf_emit(ctx, 1, 0); /* ffff0ff3 */
2541 }
2542 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */
2543 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */
2544 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */
2545 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */
2546 xf_emit(ctx, 1, 0x11); /* 3f/7f */
2547 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */
2548 if (device->chipset != 0x50) {
2549 xf_emit(ctx, 1, 0); /* 0000000f LOGIC_OP */
2550 xf_emit(ctx, 1, 0); /* 000000ff */
2551 }
2552 xf_emit(ctx, 1, 0); /* 00000007 OPERATION */
2553 xf_emit(ctx, 1, 0); /* ff/3ff */
2554 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */
2555 xf_emit(ctx, 2, 1); /* 00000007 BLEND_EQUATION_RGB, ALPHA */
2556 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */
2557 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */
2558 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */
2559 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */
2560 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */
2561 xf_emit(ctx, 1, 0); /* 00000001 */
2562 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */
2563 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
2564 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
2565 if (IS_NVA3F(device->chipset)) {
2566 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK12E4 */
2567 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */
2568 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */
2569 xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */
2570 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */
2571 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */
2572 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */
2573 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */
2574 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1140 */
2575 xf_emit(ctx, 2, 0); /* 00000001 */
2576 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
2577 xf_emit(ctx, 1, 0); /* 0000000f */
2578 xf_emit(ctx, 1, 0); /* 00000003 */
2579 xf_emit(ctx, 1, 0); /* ffffffff */
2580 xf_emit(ctx, 2, 0); /* 00000001 */
2581 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
2582 xf_emit(ctx, 1, 0); /* 00000001 */
2583 xf_emit(ctx, 1, 0); /* 000003ff */
2584 } else if (device->chipset >= 0xa0) {
2585 xf_emit(ctx, 2, 0); /* 00000001 */
2586 xf_emit(ctx, 1, 0); /* 00000007 */
2587 xf_emit(ctx, 1, 0); /* 00000003 */
2588 xf_emit(ctx, 1, 0); /* ffffffff */
2589 xf_emit(ctx, 2, 0); /* 00000001 */
2590 } else {
2591 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
2592 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1430 */
2593 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
2594 }
2595 xf_emit(ctx, 4, 0); /* ffffffff CLEAR_COLOR */
2596 xf_emit(ctx, 4, 0); /* ffffffff BLEND_COLOR A R G B */
2597 xf_emit(ctx, 1, 0); /* 00000fff eng2d UNK2B0 */
2598 if (device->chipset >= 0xa0)
2599 xf_emit(ctx, 2, 0); /* 00000001 */
2600 xf_emit(ctx, 1, 0); /* 000003ff */
2601 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */
2602 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */
2603 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */
2604 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */
2605 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */
2606 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */
2607 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */
2608 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */
2609 xf_emit(ctx, 1, 0); /* 00000001 UNK19C0 */
2610 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */
2611 xf_emit(ctx, 1, 0); /* 0000000f LOGIC_OP */
2612 if (device->chipset >= 0xa0)
2613 xf_emit(ctx, 1, 0); /* 00000001 UNK12E4? NVA3+ only? */
2614 if (IS_NVA3F(device->chipset)) {
2615 xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */
2616 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */
2617 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */
2618 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */
2619 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */
2620 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */
2621 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */
2622 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK15C4 */
2623 xf_emit(ctx, 1, 0); /* 00000001 */
2624 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1140 */
2625 }
2626 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */
2627 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */
2628 xf_emit(ctx, 1, 0); /* 00000007 PATTERN_COLOR_FORMAT */
2629 xf_emit(ctx, 2, 0); /* ffffffff PATTERN_MONO_COLOR */
2630 xf_emit(ctx, 1, 0); /* 00000001 PATTERN_MONO_FORMAT */
2631 xf_emit(ctx, 2, 0); /* ffffffff PATTERN_MONO_BITMAP */
2632 xf_emit(ctx, 1, 0); /* 00000003 PATTERN_SELECT */
2633 xf_emit(ctx, 1, 0); /* 000000ff ROP */
2634 xf_emit(ctx, 1, 0); /* ffffffff BETA1 */
2635 xf_emit(ctx, 1, 0); /* ffffffff BETA4 */
2636 xf_emit(ctx, 1, 0); /* 00000007 OPERATION */
2637 xf_emit(ctx, 0x50, 0); /* 10x ffffff, ffffff, ffffff, ffffff, 3 PATTERN */
2638 }
2639
2640 static void
2641 nv50_graph_construct_xfer_unk84xx(struct nouveau_grctx *ctx)
2642 {
2643 struct nouveau_device *device = ctx->device;
2644 int magic3;
2645 switch (device->chipset) {
2646 case 0x50:
2647 magic3 = 0x1000;
2648 break;
2649 case 0x86:
2650 case 0x98:
2651 case 0xa8:
2652 case 0xaa:
2653 case 0xac:
2654 case 0xaf:
2655 magic3 = 0x1e00;
2656 break;
2657 default:
2658 magic3 = 0;
2659 }
2660 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
2661 xf_emit(ctx, 1, 4); /* 7f/ff[NVA0+] VP_REG_ALLOC_RESULT */
2662 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
2663 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
2664 xf_emit(ctx, 1, 0); /* 111/113[NVA0+] */
2665 if (IS_NVA3F(device->chipset))
2666 xf_emit(ctx, 0x1f, 0); /* ffffffff */
2667 else if (device->chipset >= 0xa0)
2668 xf_emit(ctx, 0x0f, 0); /* ffffffff */
2669 else
2670 xf_emit(ctx, 0x10, 0); /* fffffff VP_RESULT_MAP_1 up */
2671 xf_emit(ctx, 2, 0); /* f/1f[NVA3], fffffff/ffffffff[NVA0+] */
2672 xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */
2673 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */
2674 if (device->chipset >= 0xa0)
2675 xf_emit(ctx, 1, 0x03020100); /* ffffffff */
2676 else
2677 xf_emit(ctx, 1, 0x00608080); /* fffffff VP_RESULT_MAP_0 */
2678 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
2679 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
2680 xf_emit(ctx, 2, 0); /* 111/113, 7f/ff */
2681 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */
2682 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
2683 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
2684 xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */
2685 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
2686 xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */
2687 if (magic3)
2688 xf_emit(ctx, 1, magic3); /* 00007fff tesla UNK141C */
2689 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */
2690 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
2691 xf_emit(ctx, 1, 0); /* 111/113 */
2692 xf_emit(ctx, 0x1f, 0); /* ffffffff GP_RESULT_MAP_1 up */
2693 xf_emit(ctx, 1, 0); /* 0000001f */
2694 xf_emit(ctx, 1, 0); /* ffffffff */
2695 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
2696 xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */
2697 xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */
2698 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
2699 xf_emit(ctx, 1, 0x03020100); /* ffffffff GP_RESULT_MAP_0 */
2700 xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */
2701 if (magic3)
2702 xf_emit(ctx, 1, magic3); /* 7fff tesla UNK141C */
2703 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */
2704 xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */
2705 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
2706 xf_emit(ctx, 1, 0); /* 111/113 */
2707 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
2708 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
2709 xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */
2710 xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */
2711 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
2712 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK13A0 */
2713 xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */
2714 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
2715 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
2716 xf_emit(ctx, 1, 0); /* 111/113 */
2717 if (device->chipset == 0x94 || device->chipset == 0x96)
2718 xf_emit(ctx, 0x1020, 0); /* 4 x (0x400 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */
2719 else if (device->chipset < 0xa0)
2720 xf_emit(ctx, 0xa20, 0); /* 4 x (0x280 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */
2721 else if (!IS_NVA3F(device->chipset))
2722 xf_emit(ctx, 0x210, 0); /* ffffffff */
2723 else
2724 xf_emit(ctx, 0x410, 0); /* ffffffff */
2725 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
2726 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
2727 xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */
2728 xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */
2729 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
2730 }
2731
2732 static void
2733 nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx)
2734 {
2735 struct nouveau_device *device = ctx->device;
2736 int magic1, magic2;
2737 if (device->chipset == 0x50) {
2738 magic1 = 0x3ff;
2739 magic2 = 0x00003e60;
2740 } else if (!IS_NVA3F(device->chipset)) {
2741 magic1 = 0x7ff;
2742 magic2 = 0x001ffe67;
2743 } else {
2744 magic1 = 0x7ff;
2745 magic2 = 0x00087e67;
2746 }
2747 xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */
2748 xf_emit(ctx, 1, 0); /* ffffffff ALPHA_TEST_REF */
2749 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */
2750 if (IS_NVA3F(device->chipset))
2751 xf_emit(ctx, 1, 1); /* 0000000f UNK16A0 */
2752 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
2753 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
2754 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */
2755 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */
2756 xf_emit(ctx, 4, 0); /* ffffffff BLEND_COLOR */
2757 xf_emit(ctx, 1, 0); /* 00000001 UNK19C0 */
2758 xf_emit(ctx, 1, 0); /* 00000001 UNK0FDC */
2759 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */
2760 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */
2761 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
2762 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
2763 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */
2764 xf_emit(ctx, 1, 0); /* ff[NV50]/3ff[NV84+] */
2765 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */
2766 xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */
2767 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */
2768 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */
2769 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
2770 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */
2771 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */
2772 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */
2773 xf_emit(ctx, 1, 0); /* 7 */
2774 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */
2775 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
2776 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
2777 xf_emit(ctx, 1, 0); /* ffffffff COLOR_KEY */
2778 xf_emit(ctx, 1, 0); /* 00000001 COLOR_KEY_ENABLE */
2779 xf_emit(ctx, 1, 0); /* 00000007 COLOR_KEY_FORMAT */
2780 xf_emit(ctx, 2, 0); /* ffffffff SIFC_BITMAP_COLOR */
2781 xf_emit(ctx, 1, 1); /* 00000001 SIFC_BITMAP_WRITE_BIT0_ENABLE */
2782 xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */
2783 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */
2784 if (IS_NVA3F(device->chipset)) {
2785 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK16B4 */
2786 xf_emit(ctx, 1, 0); /* 00000003 */
2787 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1298 */
2788 } else if (device->chipset >= 0xa0) {
2789 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK16B4 */
2790 xf_emit(ctx, 1, 0); /* 00000003 */
2791 } else {
2792 xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */
2793 }
2794 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
2795 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */
2796 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */
2797 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */
2798 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */
2799 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */
2800 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */
2801 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */
2802 if (IS_NVA3F(device->chipset)) {
2803 xf_emit(ctx, 1, 0); /* 00000001 UNK12E4 */
2804 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */
2805 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */
2806 xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */
2807 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_SRC_RGB */
2808 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_DST_RGB */
2809 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_SRC_ALPHA */
2810 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_DST_ALPHA */
2811 xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */
2812 }
2813 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */
2814 xf_emit(ctx, 1, 0); /* ffff0ff3 */
2815 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */
2816 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */
2817 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
2818 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */
2819 xf_emit(ctx, 1, 0); /* ff/3ff */
2820 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */
2821 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */
2822 xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */
2823 xf_emit(ctx, 1, 0); /* 7 */
2824 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */
2825 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */
2826 xf_emit(ctx, 1, 0); /* 00000007 OPERATION */
2827 xf_emit(ctx, 1, 0xcf); /* 000000ff SIFC_FORMAT */
2828 xf_emit(ctx, 1, 0xcf); /* 000000ff DRAW_COLOR_FORMAT */
2829 xf_emit(ctx, 1, 0xcf); /* 000000ff SRC_FORMAT */
2830 if (IS_NVA3F(device->chipset))
2831 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
2832 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
2833 xf_emit(ctx, 1, 0); /* 7/f[NVA3] MULTISAMPLE_SAMPLES_LOG2 */
2834 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */
2835 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */
2836 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */
2837 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */
2838 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */
2839 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */
2840 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */
2841 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */
2842 xf_emit(ctx, 1, 0); /* ffff0ff3 */
2843 xf_emit(ctx, 8, 1); /* 00000001 UNK19E0 */
2844 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */
2845 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */
2846 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
2847 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */
2848 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */
2849 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */
2850 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
2851 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
2852 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */
2853 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */
2854 if (IS_NVA3F(device->chipset))
2855 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
2856 if (device->chipset == 0x50)
2857 xf_emit(ctx, 1, 0); /* ff */
2858 else
2859 xf_emit(ctx, 3, 0); /* 1, 7, 3ff */
2860 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */
2861 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */
2862 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
2863 xf_emit(ctx, 1, 0); /* 00000007 */
2864 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */
2865 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
2866 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
2867 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
2868 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
2869 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
2870 xf_emit(ctx, 1, 0); /* ffff0ff3 */
2871 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */
2872 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */
2873 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
2874 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
2875 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
2876 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
2877 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */
2878 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */
2879 xf_emit(ctx, 1, 0); /* 000fffff BLIT_DU_DX_FRACT */
2880 xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DU_DX_INT */
2881 xf_emit(ctx, 1, 0); /* 000fffff BLIT_DV_DY_FRACT */
2882 xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DV_DY_INT */
2883 xf_emit(ctx, 1, 0); /* ff/3ff */
2884 xf_emit(ctx, 1, magic1); /* 3ff/7ff tesla UNK0D68 */
2885 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
2886 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */
2887 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
2888 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
2889 xf_emit(ctx, 1, 0); /* 00000007 */
2890 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
2891 if (IS_NVA3F(device->chipset))
2892 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
2893 xf_emit(ctx, 8, 0); /* 0000ffff DMA_COLOR */
2894 xf_emit(ctx, 1, 0); /* 0000ffff DMA_GLOBAL */
2895 xf_emit(ctx, 1, 0); /* 0000ffff DMA_LOCAL */
2896 xf_emit(ctx, 1, 0); /* 0000ffff DMA_STACK */
2897 xf_emit(ctx, 1, 0); /* ff/3ff */
2898 xf_emit(ctx, 1, 0); /* 0000ffff DMA_DST */
2899 xf_emit(ctx, 1, 0); /* 7 */
2900 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
2901 xf_emit(ctx, 1, 0); /* ffff0ff3 */
2902 xf_emit(ctx, 8, 0); /* 000000ff RT_ADDRESS_HIGH */
2903 xf_emit(ctx, 8, 0); /* ffffffff RT_LAYER_STRIDE */
2904 xf_emit(ctx, 8, 0); /* ffffffff RT_ADDRESS_LOW */
2905 xf_emit(ctx, 8, 8); /* 0000007f RT_TILE_MODE */
2906 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */
2907 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */
2908 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
2909 xf_emit(ctx, 8, 0x400); /* 0fffffff RT_HORIZ */
2910 xf_emit(ctx, 8, 0x300); /* 0000ffff RT_VERT */
2911 xf_emit(ctx, 1, 1); /* 00001fff RT_ARRAY_MODE */
2912 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */
2913 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */
2914 xf_emit(ctx, 1, 0x20); /* 00000fff DST_TILE_MODE */
2915 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */
2916 xf_emit(ctx, 1, 0x100); /* 0001ffff DST_HEIGHT */
2917 xf_emit(ctx, 1, 0); /* 000007ff DST_LAYER */
2918 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */
2919 xf_emit(ctx, 1, 0); /* ffffffff DST_ADDRESS_LOW */
2920 xf_emit(ctx, 1, 0); /* 000000ff DST_ADDRESS_HIGH */
2921 xf_emit(ctx, 1, 0x40); /* 0007ffff DST_PITCH */
2922 xf_emit(ctx, 1, 0x100); /* 0001ffff DST_WIDTH */
2923 xf_emit(ctx, 1, 0); /* 0000ffff */
2924 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK15AC */
2925 xf_emit(ctx, 1, 0); /* ff/3ff */
2926 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */
2927 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */
2928 xf_emit(ctx, 1, 0); /* 00000007 */
2929 if (IS_NVA3F(device->chipset))
2930 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
2931 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */
2932 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
2933 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
2934 xf_emit(ctx, 1, 0); /* ffff0ff3 */
2935 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */
2936 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
2937 xf_emit(ctx, 1, 0); /* 0000ffff DMA_ZETA */
2938 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
2939 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
2940 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
2941 xf_emit(ctx, 2, 0); /* ffff, ff/3ff */
2942 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */
2943 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
2944 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */
2945 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */
2946 xf_emit(ctx, 1, 0); /* 00000007 */
2947 xf_emit(ctx, 1, 0); /* ffffffff ZETA_LAYER_STRIDE */
2948 xf_emit(ctx, 1, 0); /* 000000ff ZETA_ADDRESS_HIGH */
2949 xf_emit(ctx, 1, 0); /* ffffffff ZETA_ADDRESS_LOW */
2950 xf_emit(ctx, 1, 4); /* 00000007 ZETA_TILE_MODE */
2951 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
2952 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
2953 xf_emit(ctx, 1, 0x400); /* 0fffffff ZETA_HORIZ */
2954 xf_emit(ctx, 1, 0x300); /* 0000ffff ZETA_VERT */
2955 xf_emit(ctx, 1, 0x1001); /* 00001fff ZETA_ARRAY_MODE */
2956 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
2957 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
2958 if (IS_NVA3F(device->chipset))
2959 xf_emit(ctx, 1, 0); /* 00000001 */
2960 xf_emit(ctx, 1, 0); /* ffff0ff3 */
2961 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */
2962 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */
2963 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
2964 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */
2965 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */
2966 xf_emit(ctx, 1, 0); /* ff/3ff */
2967 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */
2968 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */
2969 xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */
2970 xf_emit(ctx, 1, 0); /* 7 */
2971 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */
2972 if (IS_NVA3F(device->chipset)) {
2973 xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */
2974 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
2975 }
2976 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
2977 xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */
2978 xf_emit(ctx, 1, 0); /* ffff0ff3 */
2979 if (device->chipset >= 0xa0)
2980 xf_emit(ctx, 1, 0x0fac6881); /* fffffff */
2981 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */
2982 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
2983 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
2984 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
2985 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */
2986 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */
2987 xf_emit(ctx, 1, 0); /* ff/3ff */
2988 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */
2989 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
2990 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */
2991 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */
2992 xf_emit(ctx, 1, 0); /* 00000007 */
2993 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */
2994 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
2995 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
2996 if (IS_NVA3F(device->chipset)) {
2997 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
2998 xf_emit(ctx, 1, 0); /* 0000000f tesla UNK15C8 */
2999 }
3000 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
3001 if (device->chipset >= 0xa0) {
3002 xf_emit(ctx, 3, 0); /* 7/f, 1, ffff0ff3 */
3003 xf_emit(ctx, 1, 0xfac6881); /* fffffff */
3004 xf_emit(ctx, 4, 0); /* 1, 1, 1, 3ff */
3005 xf_emit(ctx, 1, 4); /* 7 */
3006 xf_emit(ctx, 1, 0); /* 1 */
3007 xf_emit(ctx, 2, 1); /* 1 */
3008 xf_emit(ctx, 2, 0); /* 7, f */
3009 xf_emit(ctx, 1, 1); /* 1 */
3010 xf_emit(ctx, 1, 0); /* 7/f */
3011 if (IS_NVA3F(device->chipset))
3012 xf_emit(ctx, 0x9, 0); /* 1 */
3013 else
3014 xf_emit(ctx, 0x8, 0); /* 1 */
3015 xf_emit(ctx, 1, 0); /* ffff0ff3 */
3016 xf_emit(ctx, 8, 1); /* 1 */
3017 xf_emit(ctx, 1, 0x11); /* 7f */
3018 xf_emit(ctx, 7, 0); /* 7f */
3019 xf_emit(ctx, 1, 0xfac6881); /* fffffff */
3020 xf_emit(ctx, 1, 0xf); /* f */
3021 xf_emit(ctx, 7, 0); /* f */
3022 xf_emit(ctx, 1, 0x11); /* 7f */
3023 xf_emit(ctx, 1, 1); /* 1 */
3024 xf_emit(ctx, 5, 0); /* 1, 7, 3ff, 3, 7 */
3025 if (IS_NVA3F(device->chipset)) {
3026 xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */
3027 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
3028 }
3029 }
3030 }
3031
3032 static void
3033 nv50_graph_construct_xfer_tex(struct nouveau_grctx *ctx)
3034 {
3035 struct nouveau_device *device = ctx->device;
3036 xf_emit(ctx, 2, 0); /* 1 LINKED_TSC. yes, 2. */
3037 if (device->chipset != 0x50)
3038 xf_emit(ctx, 1, 0); /* 3 */
3039 xf_emit(ctx, 1, 1); /* 1ffff BLIT_DU_DX_INT */
3040 xf_emit(ctx, 1, 0); /* fffff BLIT_DU_DX_FRACT */
3041 xf_emit(ctx, 1, 1); /* 1ffff BLIT_DV_DY_INT */
3042 xf_emit(ctx, 1, 0); /* fffff BLIT_DV_DY_FRACT */
3043 if (device->chipset == 0x50)
3044 xf_emit(ctx, 1, 0); /* 3 BLIT_CONTROL */
3045 else
3046 xf_emit(ctx, 2, 0); /* 3ff, 1 */
3047 xf_emit(ctx, 1, 0x2a712488); /* ffffffff SRC_TIC_0 */
3048 xf_emit(ctx, 1, 0); /* ffffffff SRC_TIC_1 */
3049 xf_emit(ctx, 1, 0x4085c000); /* ffffffff SRC_TIC_2 */
3050 xf_emit(ctx, 1, 0x40); /* ffffffff SRC_TIC_3 */
3051 xf_emit(ctx, 1, 0x100); /* ffffffff SRC_TIC_4 */
3052 xf_emit(ctx, 1, 0x10100); /* ffffffff SRC_TIC_5 */
3053 xf_emit(ctx, 1, 0x02800000); /* ffffffff SRC_TIC_6 */
3054 xf_emit(ctx, 1, 0); /* ffffffff SRC_TIC_7 */
3055 if (device->chipset == 0x50) {
3056 xf_emit(ctx, 1, 0); /* 00000001 turing UNK358 */
3057 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34? */
3058 xf_emit(ctx, 1, 0); /* 00000003 turing UNK37C tesla UNK1690 */
3059 xf_emit(ctx, 1, 0); /* 00000003 BLIT_CONTROL */
3060 xf_emit(ctx, 1, 0); /* 00000001 turing UNK32C tesla UNK0F94 */
3061 } else if (!IS_NVAAF(device->chipset)) {
3062 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34? */
3063 xf_emit(ctx, 1, 0); /* 00000003 */
3064 xf_emit(ctx, 1, 0); /* 000003ff */
3065 xf_emit(ctx, 1, 0); /* 00000003 */
3066 xf_emit(ctx, 1, 0); /* 000003ff */
3067 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1664 / turing UNK03E8 */
3068 xf_emit(ctx, 1, 0); /* 00000003 */
3069 xf_emit(ctx, 1, 0); /* 000003ff */
3070 } else {
3071 xf_emit(ctx, 0x6, 0);
3072 }
3073 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34 */
3074 xf_emit(ctx, 1, 0); /* 0000ffff DMA_TEXTURE */
3075 xf_emit(ctx, 1, 0); /* 0000ffff DMA_SRC */
3076 }
3077
3078 static void
3079 nv50_graph_construct_xfer_unk8cxx(struct nouveau_grctx *ctx)
3080 {
3081 struct nouveau_device *device = ctx->device;
3082 xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */
3083 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
3084 xf_emit(ctx, 2, 0); /* 7, ffff0ff3 */
3085 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
3086 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE */
3087 xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0D64 */
3088 xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0DF4 */
3089 xf_emit(ctx, 1, 1); /* 00000001 UNK15B4 */
3090 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */
3091 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */
3092 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK0F98 */
3093 if (IS_NVA3F(device->chipset))
3094 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
3095 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1668 */
3096 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */
3097 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */
3098 xf_emit(ctx, 1, 0); /* 00000001 POLYGON_SMOOTH_ENABLE */
3099 xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */
3100 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
3101 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1658 */
3102 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */
3103 xf_emit(ctx, 1, 0); /* ffff0ff3 */
3104 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
3105 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE */
3106 xf_emit(ctx, 1, 1); /* 00000001 UNK15B4 */
3107 xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */
3108 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK165C */
3109 xf_emit(ctx, 1, 0x30201000); /* ffffffff tesla UNK1670 */
3110 xf_emit(ctx, 1, 0x70605040); /* ffffffff tesla UNK1670 */
3111 xf_emit(ctx, 1, 0xb8a89888); /* ffffffff tesla UNK1670 */
3112 xf_emit(ctx, 1, 0xf8e8d8c8); /* ffffffff tesla UNK1670 */
3113 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */
3114 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */
3115 }
3116
3117 static void
3118 nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx)
3119 {
3120 struct nouveau_device *device = ctx->device;
3121 if (device->chipset < 0xa0) {
3122 nv50_graph_construct_xfer_unk84xx(ctx);
3123 nv50_graph_construct_xfer_tprop(ctx);
3124 nv50_graph_construct_xfer_tex(ctx);
3125 nv50_graph_construct_xfer_unk8cxx(ctx);
3126 } else {
3127 nv50_graph_construct_xfer_tex(ctx);
3128 nv50_graph_construct_xfer_tprop(ctx);
3129 nv50_graph_construct_xfer_unk8cxx(ctx);
3130 nv50_graph_construct_xfer_unk84xx(ctx);
3131 }
3132 }
3133
3134 static void
3135 nv50_graph_construct_xfer_mpc(struct nouveau_grctx *ctx)
3136 {
3137 struct nouveau_device *device = ctx->device;
3138 int i, mpcnt = 2;
3139 switch (device->chipset) {
3140 case 0x98:
3141 case 0xaa:
3142 mpcnt = 1;
3143 break;
3144 case 0x50:
3145 case 0x84:
3146 case 0x86:
3147 case 0x92:
3148 case 0x94:
3149 case 0x96:
3150 case 0xa8:
3151 case 0xac:
3152 mpcnt = 2;
3153 break;
3154 case 0xa0:
3155 case 0xa3:
3156 case 0xa5:
3157 case 0xaf:
3158 mpcnt = 3;
3159 break;
3160 }
3161 for (i = 0; i < mpcnt; i++) {
3162 xf_emit(ctx, 1, 0); /* ff */
3163 xf_emit(ctx, 1, 0x80); /* ffffffff tesla UNK1404 */
3164 xf_emit(ctx, 1, 0x80007004); /* ffffffff tesla UNK12B0 */
3165 xf_emit(ctx, 1, 0x04000400); /* ffffffff */
3166 if (device->chipset >= 0xa0)
3167 xf_emit(ctx, 1, 0xc0); /* 00007fff tesla UNK152C */
3168 xf_emit(ctx, 1, 0x1000); /* 0000ffff tesla UNK0D60 */
3169 xf_emit(ctx, 1, 0); /* ff/3ff */
3170 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
3171 if (device->chipset == 0x86 || device->chipset == 0x98 || device->chipset == 0xa8 || IS_NVAAF(device->chipset)) {
3172 xf_emit(ctx, 1, 0xe00); /* 7fff */
3173 xf_emit(ctx, 1, 0x1e00); /* 7fff */
3174 }
3175 xf_emit(ctx, 1, 1); /* 000000ff VP_REG_ALLOC_TEMP */
3176 xf_emit(ctx, 1, 0); /* 00000001 LINKED_TSC */
3177 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
3178 if (device->chipset == 0x50)
3179 xf_emit(ctx, 2, 0x1000); /* 7fff tesla UNK141C */
3180 xf_emit(ctx, 1, 1); /* 000000ff GP_REG_ALLOC_TEMP */
3181 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
3182 xf_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */
3183 xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */
3184 if (IS_NVAAF(device->chipset))
3185 xf_emit(ctx, 0xb, 0); /* RO */
3186 else if (device->chipset >= 0xa0)
3187 xf_emit(ctx, 0xc, 0); /* RO */
3188 else
3189 xf_emit(ctx, 0xa, 0); /* RO */
3190 }
3191 xf_emit(ctx, 1, 0x08100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
3192 xf_emit(ctx, 1, 0); /* ff/3ff */
3193 if (device->chipset >= 0xa0) {
3194 xf_emit(ctx, 1, 0x1fe21); /* 0003ffff tesla UNK0FAC */
3195 }
3196 xf_emit(ctx, 3, 0); /* 7fff, 0, 0 */
3197 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
3198 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
3199 xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */
3200 xf_emit(ctx, 1, 1); /* 00000001 LANES32 */
3201 xf_emit(ctx, 1, 0x10001); /* 00ffffff BLOCK_ALLOC */
3202 xf_emit(ctx, 1, 0x10001); /* ffffffff BLOCKDIM_XY */
3203 xf_emit(ctx, 1, 1); /* 0000ffff BLOCKDIM_Z */
3204 xf_emit(ctx, 1, 0); /* ffffffff SHARED_SIZE */
3205 xf_emit(ctx, 1, 0x1fe21); /* 1ffff/3ffff[NVA0+] tesla UNk0FAC */
3206 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34 */
3207 if (IS_NVA3F(device->chipset))
3208 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
3209 xf_emit(ctx, 1, 0); /* ff/3ff */
3210 xf_emit(ctx, 1, 0); /* 1 LINKED_TSC */
3211 xf_emit(ctx, 1, 0); /* ff FP_ADDRESS_HIGH */
3212 xf_emit(ctx, 1, 0); /* ffffffff FP_ADDRESS_LOW */
3213 xf_emit(ctx, 1, 0x08100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
3214 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */
3215 xf_emit(ctx, 1, 0); /* 000000ff FRAG_COLOR_CLAMP_EN */
3216 xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */
3217 xf_emit(ctx, 1, 0x11); /* 0000007f RT_FORMAT */
3218 xf_emit(ctx, 7, 0); /* 0000007f RT_FORMAT */
3219 xf_emit(ctx, 1, 0); /* 00000007 */
3220 xf_emit(ctx, 1, 0xfac6881); /* 0fffffff RT_CONTROL */
3221 xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */
3222 if (IS_NVA3F(device->chipset))
3223 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK16B4 */
3224 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */
3225 xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */
3226 xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */
3227 xf_emit(ctx, 1, 4); /* ffffffff tesla UNK1400 */
3228 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */
3229 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */
3230 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */
3231 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */
3232 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */
3233 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */
3234 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */
3235 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */
3236 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */
3237 if (IS_NVA3F(device->chipset)) {
3238 xf_emit(ctx, 1, 0); /* 00000001 UNK12E4 */
3239 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */
3240 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */
3241 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */
3242 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */
3243 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */
3244 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */
3245 xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */
3246 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1928 */
3247 xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */
3248 }
3249 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0F90 */
3250 xf_emit(ctx, 1, 4); /* 000000ff FP_RESULT_COUNT */
3251 /* XXX: demagic this part some day */
3252 if (device->chipset == 0x50)
3253 xf_emit(ctx, 0x3a0, 0);
3254 else if (device->chipset < 0x94)
3255 xf_emit(ctx, 0x3a2, 0);
3256 else if (device->chipset == 0x98 || device->chipset == 0xaa)
3257 xf_emit(ctx, 0x39f, 0);
3258 else
3259 xf_emit(ctx, 0x3a3, 0);
3260 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */
3261 xf_emit(ctx, 1, 0); /* 7 OPERATION */
3262 xf_emit(ctx, 1, 1); /* 1 DST_LINEAR */
3263 xf_emit(ctx, 0x2d, 0);
3264 }
3265
3266 static void
3267 nv50_graph_construct_xfer2(struct nouveau_grctx *ctx)
3268 {
3269 struct nouveau_device *device = ctx->device;
3270 int i;
3271 u32 offset;
3272 u32 units = nv_rd32 (ctx->device, 0x1540);
3273 int size = 0;
3274
3275 offset = (ctx->ctxvals_pos+0x3f)&~0x3f;
3276
3277 if (device->chipset < 0xa0) {
3278 for (i = 0; i < 8; i++) {
3279 ctx->ctxvals_pos = offset + i;
3280 /* that little bugger belongs to csched. No idea
3281 * what it's doing here. */
3282 if (i == 0)
3283 xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */
3284 if (units & (1 << i))
3285 nv50_graph_construct_xfer_mpc(ctx);
3286 if ((ctx->ctxvals_pos-offset)/8 > size)
3287 size = (ctx->ctxvals_pos-offset)/8;
3288 }
3289 } else {
3290 /* Strand 0: TPs 0, 1 */
3291 ctx->ctxvals_pos = offset;
3292 /* that little bugger belongs to csched. No idea
3293 * what it's doing here. */
3294 xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */
3295 if (units & (1 << 0))
3296 nv50_graph_construct_xfer_mpc(ctx);
3297 if (units & (1 << 1))
3298 nv50_graph_construct_xfer_mpc(ctx);
3299 if ((ctx->ctxvals_pos-offset)/8 > size)
3300 size = (ctx->ctxvals_pos-offset)/8;
3301
3302 /* Strand 1: TPs 2, 3 */
3303 ctx->ctxvals_pos = offset + 1;
3304 if (units & (1 << 2))
3305 nv50_graph_construct_xfer_mpc(ctx);
3306 if (units & (1 << 3))
3307 nv50_graph_construct_xfer_mpc(ctx);
3308 if ((ctx->ctxvals_pos-offset)/8 > size)
3309 size = (ctx->ctxvals_pos-offset)/8;
3310
3311 /* Strand 2: TPs 4, 5, 6 */
3312 ctx->ctxvals_pos = offset + 2;
3313 if (units & (1 << 4))
3314 nv50_graph_construct_xfer_mpc(ctx);
3315 if (units & (1 << 5))
3316 nv50_graph_construct_xfer_mpc(ctx);
3317 if (units & (1 << 6))
3318 nv50_graph_construct_xfer_mpc(ctx);
3319 if ((ctx->ctxvals_pos-offset)/8 > size)
3320 size = (ctx->ctxvals_pos-offset)/8;
3321
3322 /* Strand 3: TPs 7, 8, 9 */
3323 ctx->ctxvals_pos = offset + 3;
3324 if (units & (1 << 7))
3325 nv50_graph_construct_xfer_mpc(ctx);
3326 if (units & (1 << 8))
3327 nv50_graph_construct_xfer_mpc(ctx);
3328 if (units & (1 << 9))
3329 nv50_graph_construct_xfer_mpc(ctx);
3330 if ((ctx->ctxvals_pos-offset)/8 > size)
3331 size = (ctx->ctxvals_pos-offset)/8;
3332 }
3333 ctx->ctxvals_pos = offset + size * 8;
3334 ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f;
3335 cp_lsr (ctx, offset);
3336 cp_out (ctx, CP_SET_XFER_POINTER);
3337 cp_lsr (ctx, size);
3338 cp_out (ctx, CP_SEEK_2);
3339 cp_out (ctx, CP_XFER_2);
3340 cp_wait(ctx, XFER, BUSY);
3341 }
Linux kernel - Deliverables
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