drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c

   1 /*
   2  * Copyright 2013 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs <bskeggs@redhat.com>
  23  */
  24
  25 #include "ctxnvc0.h"
  26
  27 /*******************************************************************************
  28  * PGRAPH context register lists
  29  ******************************************************************************/
  30
  31 static const struct nvc0_graph_init
  32 nvd7_grctx_init_ds_0[] = {
  33         { 0x405800,   1, 0x04, 0x0f8000bf },
  34         { 0x405830,   1, 0x04, 0x02180324 },
  35         { 0x405834,   1, 0x04, 0x08000000 },
  36         { 0x405838,   1, 0x04, 0x00000000 },
  37         { 0x405854,   1, 0x04, 0x00000000 },
  38         { 0x405870,   4, 0x04, 0x00000001 },
  39         { 0x405a00,   2, 0x04, 0x00000000 },
  40         { 0x405a18,   1, 0x04, 0x00000000 },
  41         {}
  42 };
  43
  44 static const struct nvc0_graph_init
  45 nvd7_grctx_init_pd_0[] = {
  46         { 0x406020,   1, 0x04, 0x000103c1 },
  47         { 0x406028,   4, 0x04, 0x00000001 },
  48         { 0x4064a8,   1, 0x04, 0x00000000 },
  49         { 0x4064ac,   1, 0x04, 0x00003fff },
  50         { 0x4064b4,   3, 0x04, 0x00000000 },
  51         { 0x4064c0,   1, 0x04, 0x801a0078 },
  52         { 0x4064c4,   1, 0x04, 0x00c9ffff },
  53         { 0x4064d0,   8, 0x04, 0x00000000 },
  54         {}
  55 };
  56
  57 static const struct nvc0_graph_pack
  58 nvd7_grctx_pack_hub[] = {
  59         { nvc0_grctx_init_main_0 },
  60         { nvd9_grctx_init_fe_0 },
  61         { nvc0_grctx_init_pri_0 },
  62         { nvc0_grctx_init_memfmt_0 },
  63         { nvd7_grctx_init_ds_0 },
  64         { nvd7_grctx_init_pd_0 },
  65         { nvc0_grctx_init_rstr2d_0 },
  66         { nvc0_grctx_init_scc_0 },
  67         { nvd9_grctx_init_be_0 },
  68         {}
  69 };
  70
  71 static const struct nvc0_graph_init
  72 nvd7_grctx_init_setup_0[] = {
  73         { 0x418800,   1, 0x04, 0x7006860a },
  74         { 0x418808,   3, 0x04, 0x00000000 },
  75         { 0x418828,   1, 0x04, 0x00008442 },
  76         { 0x418830,   1, 0x04, 0x10000001 },
  77         { 0x4188d8,   1, 0x04, 0x00000008 },
  78         { 0x4188e0,   1, 0x04, 0x01000000 },
  79         { 0x4188e8,   5, 0x04, 0x00000000 },
  80         { 0x4188fc,   1, 0x04, 0x20100018 },
  81         {}
  82 };
  83
  84 static const struct nvc0_graph_pack
  85 nvd7_grctx_pack_gpc[] = {
  86         { nvc0_grctx_init_gpc_unk_0 },
  87         { nvd9_grctx_init_prop_0 },
  88         { nvd9_grctx_init_gpc_unk_1 },
  89         { nvd7_grctx_init_setup_0 },
  90         { nvc0_grctx_init_zcull_0 },
  91         { nvd9_grctx_init_crstr_0 },
  92         { nvc1_grctx_init_gpm_0 },
  93         { nvc0_grctx_init_gcc_0 },
  94         {}
  95 };
  96
  97 const struct nvc0_graph_init
  98 nvd7_grctx_init_pe_0[] = {
  99         { 0x419848,   1, 0x04, 0x00000000 },
 100         { 0x419864,   1, 0x04, 0x00000129 },
 101         { 0x419888,   1, 0x04, 0x00000000 },
 102         {}
 103 };
 104
 105 static const struct nvc0_graph_init
 106 nvd7_grctx_init_tex_0[] = {
 107         { 0x419a00,   1, 0x04, 0x000001f0 },
 108         { 0x419a04,   1, 0x04, 0x00000001 },
 109         { 0x419a08,   1, 0x04, 0x00000023 },
 110         { 0x419a0c,   1, 0x04, 0x00020000 },
 111         { 0x419a10,   1, 0x04, 0x00000000 },
 112         { 0x419a14,   1, 0x04, 0x00000200 },
 113         { 0x419a1c,   1, 0x04, 0x00008000 },
 114         { 0x419a20,   1, 0x04, 0x00000800 },
 115         { 0x419ac4,   1, 0x04, 0x0017f440 },
 116         {}
 117 };
 118
 119 static const struct nvc0_graph_init
 120 nvd7_grctx_init_mpc_0[] = {
 121         { 0x419c00,   1, 0x04, 0x0000000a },
 122         { 0x419c04,   1, 0x04, 0x00000006 },
 123         { 0x419c08,   1, 0x04, 0x00000002 },
 124         { 0x419c20,   1, 0x04, 0x00000000 },
 125         { 0x419c24,   1, 0x04, 0x00084210 },
 126         { 0x419c28,   1, 0x04, 0x3efbefbe },
 127         {}
 128 };
 129
 130 static const struct nvc0_graph_pack
 131 nvd7_grctx_pack_tpc[] = {
 132         { nvd7_grctx_init_pe_0 },
 133         { nvd7_grctx_init_tex_0 },
 134         { nvd7_grctx_init_mpc_0 },
 135         { nvc4_grctx_init_l1c_0 },
 136         { nvd9_grctx_init_sm_0 },
 137         {}
 138 };
 139
 140 static const struct nvc0_graph_init
 141 nvd7_grctx_init_pes_0[] = {
 142         { 0x41be24,   1, 0x04, 0x00000002 },
 143         {}
 144 };
 145
 146 static const struct nvc0_graph_init
 147 nvd7_grctx_init_cbm_0[] = {
 148         { 0x41bec0,   1, 0x04, 0x12180000 },
 149         { 0x41bec4,   1, 0x04, 0x00003fff },
 150         { 0x41bee4,   1, 0x04, 0x03240218 },
 151         {}
 152 };
 153
 154 const struct nvc0_graph_init
 155 nvd7_grctx_init_wwdx_0[] = {
 156         { 0x41bf00,   1, 0x04, 0x0a418820 },
 157         { 0x41bf04,   1, 0x04, 0x062080e6 },
 158         { 0x41bf08,   1, 0x04, 0x020398a4 },
 159         { 0x41bf0c,   1, 0x04, 0x0e629062 },
 160         { 0x41bf10,   1, 0x04, 0x0a418820 },
 161         { 0x41bf14,   1, 0x04, 0x000000e6 },
 162         { 0x41bfd0,   1, 0x04, 0x00900103 },
 163         { 0x41bfe0,   1, 0x04, 0x00400001 },
 164         { 0x41bfe4,   1, 0x04, 0x00000000 },
 165         {}
 166 };
 167
 168 static const struct nvc0_graph_pack
 169 nvd7_grctx_pack_ppc[] = {
 170         { nvd7_grctx_init_pes_0 },
 171         { nvd7_grctx_init_cbm_0 },
 172         { nvd7_grctx_init_wwdx_0 },
 173         {}
 174 };
 175
 176 /*******************************************************************************
 177  * PGRAPH context implementation
 178  ******************************************************************************/
 179
 180 static void
 181 nvd7_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
 182 {
 183         u32 magic[GPC_MAX][2];
 184         u32 offset;
 185         int gpc;
 186
 187         mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
 188         mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
 189         mmio_list(0x40800c, 0x00000000,  8, 1);
 190         mmio_list(0x408010, 0x80000000,  0, 0);
 191         mmio_list(0x419004, 0x00000000,  8, 1);
 192         mmio_list(0x419008, 0x00000000,  0, 0);
 193         mmio_list(0x418810, 0x80000000, 12, 2);
 194         mmio_list(0x419848, 0x10000000, 12, 2);
 195
 196         mmio_list(0x405830, 0x02180324,  0, 0);
 197         mmio_list(0x4064c4, 0x00c9ffff,  0, 0);
 198
 199         for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) {
 200                 u16 magic0 = 0x0218 * priv->tpc_nr[gpc];
 201                 u16 magic1 = 0x0324 * priv->tpc_nr[gpc];
 202                 magic[gpc][0]  = 0x10000000 | (magic0 << 16) | offset;
 203                 magic[gpc][1]  = 0x00000000 | (magic1 << 16);
 204                 offset += 0x0324 * priv->tpc_nr[gpc];
 205         }
 206
 207         for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 208                 mmio_list(GPC_UNIT(gpc, 0x30c0), magic[gpc][0], 0, 0);
 209                 mmio_list(GPC_UNIT(gpc, 0x30e4), magic[gpc][1] | offset, 0, 0);
 210                 offset += 0x07ff * priv->tpc_nr[gpc];
 211         }
 212         mmio_list(0x17e91c, 0x03060609, 0, 0); /* different from kepler */
 213 }
 214
 215 void
 216 nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
 217 {
 218         struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
 219         int i;
 220
 221         nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
 222
 223         nvc0_graph_mmio(priv, oclass->hub);
 224         nvc0_graph_mmio(priv, oclass->gpc);
 225         nvc0_graph_mmio(priv, oclass->zcull);
 226         nvc0_graph_mmio(priv, oclass->tpc);
 227         nvc0_graph_mmio(priv, oclass->ppc);
 228
 229         nv_wr32(priv, 0x404154, 0x00000000);
 230
 231         oclass->bundle(info);
 232         oclass->mods(priv, info);
 233         oclass->unkn(priv);
 234
 235         nvc0_grctx_generate_tpcid(priv);
 236         nvc0_grctx_generate_r406028(priv);
 237         nvc0_grctx_generate_r4060a8(priv);
 238         nve4_grctx_generate_r418bb8(priv);
 239         nvc0_grctx_generate_r406800(priv);
 240
 241         for (i = 0; i < 8; i++)
 242                 nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
 243
 244         nvc0_graph_icmd(priv, oclass->icmd);
 245         nv_wr32(priv, 0x404154, 0x00000400);
 246         nvc0_graph_mthd(priv, oclass->mthd);
 247         nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
 248 }
 249
 250 struct nouveau_oclass *
 251 nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) {
 252         .base.handle = NV_ENGCTX(GR, 0xd7),
 253         .base.ofuncs = &(struct nouveau_ofuncs) {
 254                 .ctor = nvc0_graph_context_ctor,
 255                 .dtor = nvc0_graph_context_dtor,
 256                 .init = _nouveau_graph_context_init,
 257                 .fini = _nouveau_graph_context_fini,
 258                 .rd32 = _nouveau_graph_context_rd32,
 259                 .wr32 = _nouveau_graph_context_wr32,
 260         },
 261         .main  = nvd7_grctx_generate_main,
 262         .mods  = nvd7_grctx_generate_mods,
 263         .unkn  = nve4_grctx_generate_unkn,
 264         .hub   = nvd7_grctx_pack_hub,
 265         .gpc   = nvd7_grctx_pack_gpc,
 266         .zcull = nvc0_grctx_pack_zcull,
 267         .tpc   = nvd7_grctx_pack_tpc,
 268         .ppc   = nvd7_grctx_pack_ppc,
 269         .icmd  = nvd9_grctx_pack_icmd,
 270         .mthd  = nvd9_grctx_pack_mthd,
 271         .bundle = nvc0_grctx_generate_bundle,
 272         .bundle_size = 0x1800,
 273 }.base;