drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc

   1 /* fuc microcode for nve0 PGRAPH/GPC
   2  *
   3  * Copyright 2011 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Ben Skeggs
  24  */
  25
  26 /* To build:
  27  *    m4 nve0_grgpc.fuc | envyas -a -w -m fuc -V nva3 -o nve0_grgpc.fuc.h
  28  */
  29
  30 /* TODO
  31  * - bracket certain functions with scratch writes, useful for debugging
  32  * - watchdog timer around ctx operations
  33  */
  34
  35 .section #nve0_grgpc_data
  36 include(`nve0.fuc')
  37 gpc_id:                 .b32 0
  38 gpc_mmio_list_head:     .b32 0
  39 gpc_mmio_list_tail:     .b32 0
  40
  41 tpc_count:              .b32 0
  42 tpc_mask:               .b32 0
  43 tpc_mmio_list_head:     .b32 0
  44 tpc_mmio_list_tail:     .b32 0
  45
  46 cmd_queue:              queue_init
  47
  48 // chipset descriptions
  49 chipsets:
  50 .b8  0xe4 0 0 0
  51 .b16 #nve4_gpc_mmio_head
  52 .b16 #nve4_gpc_mmio_tail
  53 .b16 #nve4_tpc_mmio_head
  54 .b16 #nve4_tpc_mmio_tail
  55 .b8  0xe7 0 0 0
  56 .b16 #nve4_gpc_mmio_head
  57 .b16 #nve4_gpc_mmio_tail
  58 .b16 #nve4_tpc_mmio_head
  59 .b16 #nve4_tpc_mmio_tail
  60 .b8  0xe6 0 0 0
  61 .b16 #nve4_gpc_mmio_head
  62 .b16 #nve4_gpc_mmio_tail
  63 .b16 #nve4_tpc_mmio_head
  64 .b16 #nve4_tpc_mmio_tail
  65 .b8  0xf0 0 0 0
  66 .b16 #nvf0_gpc_mmio_head
  67 .b16 #nvf0_gpc_mmio_tail
  68 .b16 #nvf0_tpc_mmio_head
  69 .b16 #nvf0_tpc_mmio_tail
  70 .b8  0 0 0 0
  71
  72 // GPC mmio lists
  73 nve4_gpc_mmio_head:
  74 mmctx_data(0x000380, 1)
  75 mmctx_data(0x000400, 2)
  76 mmctx_data(0x00040c, 3)
  77 mmctx_data(0x000450, 9)
  78 mmctx_data(0x000600, 1)
  79 mmctx_data(0x000684, 1)
  80 mmctx_data(0x000700, 5)
  81 mmctx_data(0x000800, 1)
  82 mmctx_data(0x000808, 3)
  83 mmctx_data(0x000828, 1)
  84 mmctx_data(0x000830, 1)
  85 mmctx_data(0x0008d8, 1)
  86 mmctx_data(0x0008e0, 1)
  87 mmctx_data(0x0008e8, 6)
  88 mmctx_data(0x00091c, 1)
  89 mmctx_data(0x000924, 3)
  90 mmctx_data(0x000b00, 1)
  91 mmctx_data(0x000b08, 6)
  92 mmctx_data(0x000bb8, 1)
  93 mmctx_data(0x000c08, 1)
  94 mmctx_data(0x000c10, 8)
  95 mmctx_data(0x000c40, 1)
  96 mmctx_data(0x000c6c, 1)
  97 mmctx_data(0x000c80, 1)
  98 mmctx_data(0x000c8c, 1)
  99 mmctx_data(0x001000, 3)
 100 mmctx_data(0x001014, 1)
 101 mmctx_data(0x003024, 1)
 102 mmctx_data(0x0030c0, 2)
 103 mmctx_data(0x0030e4, 1)
 104 mmctx_data(0x003100, 6)
 105 mmctx_data(0x0031d0, 1)
 106 mmctx_data(0x0031e0, 2)
 107 nve4_gpc_mmio_tail:
 108
 109 nvf0_gpc_mmio_head:
 110 mmctx_data(0x000380, 1)
 111 mmctx_data(0x000400, 2)
 112 mmctx_data(0x00040c, 3)
 113 mmctx_data(0x000450, 9)
 114 mmctx_data(0x000600, 1)
 115 mmctx_data(0x000684, 1)
 116 mmctx_data(0x000700, 5)
 117 mmctx_data(0x000800, 1)
 118 mmctx_data(0x000808, 3)
 119 mmctx_data(0x000828, 1)
 120 mmctx_data(0x000830, 1)
 121 mmctx_data(0x0008d8, 1)
 122 mmctx_data(0x0008e0, 1)
 123 mmctx_data(0x0008e8, 6)
 124 mmctx_data(0x00091c, 1)
 125 mmctx_data(0x000924, 3)
 126 mmctx_data(0x000b00, 1)
 127 mmctx_data(0x000b08, 6)
 128 mmctx_data(0x000bb8, 1)
 129 mmctx_data(0x000c08, 1)
 130 mmctx_data(0x000c10, 8)
 131 mmctx_data(0x000c40, 1)
 132 mmctx_data(0x000c6c, 1)
 133 mmctx_data(0x000c80, 1)
 134 mmctx_data(0x000c8c, 1)
 135 mmctx_data(0x000d24, 1)
 136 mmctx_data(0x001000, 3)
 137 mmctx_data(0x001014, 1)
 138 nvf0_gpc_mmio_tail:
 139
 140 // TPC mmio lists
 141 nve4_tpc_mmio_head:
 142 mmctx_data(0x000048, 1)
 143 mmctx_data(0x000064, 1)
 144 mmctx_data(0x000088, 1)
 145 mmctx_data(0x000200, 6)
 146 mmctx_data(0x00021c, 2)
 147 mmctx_data(0x000230, 1)
 148 mmctx_data(0x0002c4, 1)
 149 mmctx_data(0x000400, 3)
 150 mmctx_data(0x000420, 3)
 151 mmctx_data(0x0004e8, 1)
 152 mmctx_data(0x0004f4, 1)
 153 mmctx_data(0x000604, 4)
 154 mmctx_data(0x000644, 22)
 155 mmctx_data(0x0006ac, 2)
 156 mmctx_data(0x0006c8, 1)
 157 mmctx_data(0x000730, 8)
 158 mmctx_data(0x000758, 1)
 159 mmctx_data(0x000770, 1)
 160 mmctx_data(0x000778, 2)
 161 nve4_tpc_mmio_tail:
 162
 163 nvf0_tpc_mmio_head:
 164 mmctx_data(0x000048, 1)
 165 mmctx_data(0x000064, 1)
 166 mmctx_data(0x000088, 1)
 167 mmctx_data(0x000200, 6)
 168 mmctx_data(0x00021c, 2)
 169 mmctx_data(0x000230, 1)
 170 mmctx_data(0x0002c4, 1)
 171 mmctx_data(0x000400, 3)
 172 mmctx_data(0x000420, 3)
 173 mmctx_data(0x0004e8, 1)
 174 mmctx_data(0x0004f4, 1)
 175 mmctx_data(0x000604, 4)
 176 mmctx_data(0x000644, 22)
 177 mmctx_data(0x0006ac, 2)
 178 mmctx_data(0x0006b8, 1)
 179 mmctx_data(0x0006c8, 1)
 180 mmctx_data(0x000730, 8)
 181 mmctx_data(0x000758, 1)
 182 mmctx_data(0x000770, 1)
 183 mmctx_data(0x000778, 2)
 184 nvf0_tpc_mmio_tail:
 185
 186 .section #nve0_grgpc_code
 187 bra #init
 188 define(`include_code')
 189 include(`nve0.fuc')
 190
 191 // reports an exception to the host
 192 //
 193 // In: $r15 error code (see nve0.fuc)
 194 //
 195 error:
 196         push $r14
 197         mov $r14 -0x67ec        // 0x9814
 198         sethi $r14 0x400000
 199         call #nv_wr32           // HUB_CTXCTL_CC_SCRATCH[5] = error code
 200         add b32 $r14 0x41c
 201         mov $r15 1
 202         call #nv_wr32           // HUB_CTXCTL_INTR_UP_SET
 203         pop $r14
 204         ret
 205
 206 // GPC fuc initialisation, executed by triggering ucode start, will
 207 // fall through to main loop after completion.
 208 //
 209 // Input:
 210 //   CC_SCRATCH[0]: chipset (PMC_BOOT_0 read returns 0x0bad0bad... sigh)
 211 //   CC_SCRATCH[1]: context base
 212 //
 213 // Output:
 214 //   CC_SCRATCH[0]:
 215 //           31:31: set to signal completion
 216 //   CC_SCRATCH[1]:
 217 //            31:0: GPC context size
 218 //
 219 init:
 220         clear b32 $r0
 221         mov $sp $r0
 222
 223         // enable fifo access
 224         mov $r1 0x1200
 225         mov $r2 2
 226         iowr I[$r1 + 0x000] $r2         // FIFO_ENABLE
 227
 228         // setup i0 handler, and route all interrupts to it
 229         mov $r1 #ih
 230         mov $iv0 $r1
 231         mov $r1 0x400
 232         iowr I[$r1 + 0x300] $r0         // INTR_DISPATCH
 233
 234         // enable fifo interrupt
 235         mov $r2 4
 236         iowr I[$r1 + 0x000] $r2         // INTR_EN_SET
 237
 238         // enable interrupts
 239         bset $flags ie0
 240
 241         // figure out which GPC we are, and how many TPCs we have
 242         mov $r1 0x608
 243         shl b32 $r1 6
 244         iord $r2 I[$r1 + 0x000]         // UNITS
 245         mov $r3 1
 246         and $r2 0x1f
 247         shl b32 $r3 $r2
 248         sub b32 $r3 1
 249         st b32 D[$r0 + #tpc_count] $r2
 250         st b32 D[$r0 + #tpc_mask] $r3
 251         add b32 $r1 0x400
 252         iord $r2 I[$r1 + 0x000]         // MYINDEX
 253         st b32 D[$r0 + #gpc_id] $r2
 254
 255         // find context data for this chipset
 256         mov $r2 0x800
 257         shl b32 $r2 6
 258         iord $r2 I[$r2 + 0x000]         // CC_SCRATCH[0]
 259         mov $r1 #chipsets - 12
 260         init_find_chipset:
 261                 add b32 $r1 12
 262                 ld b32 $r3 D[$r1 + 0x00]
 263                 cmpu b32 $r3 $r2
 264                 bra e #init_context
 265                 cmpu b32 $r3 0
 266                 bra ne #init_find_chipset
 267                 // unknown chipset
 268                 ret
 269
 270         // initialise context base, and size tracking
 271         init_context:
 272         mov $r2 0x800
 273         shl b32 $r2 6
 274         iord $r2 I[$r2 + 0x100] // CC_SCRATCH[1], initial base
 275         clear b32 $r3           // track GPC context size here
 276
 277         // set mmctx base addresses now so we don't have to do it later,
 278         // they don't currently ever change
 279         mov $r4 0x700
 280         shl b32 $r4 6
 281         shr b32 $r5 $r2 8
 282         iowr I[$r4 + 0x000] $r5         // MMCTX_SAVE_SWBASE
 283         iowr I[$r4 + 0x100] $r5         // MMCTX_LOAD_SWBASE
 284
 285         // calculate GPC mmio context size, store the chipset-specific
 286         // mmio list pointers somewhere we can get at them later without
 287         // re-parsing the chipset list
 288         clear b32 $r14
 289         clear b32 $r15
 290         ld b16 $r14 D[$r1 + 4]
 291         ld b16 $r15 D[$r1 + 6]
 292         st b16 D[$r0 + #gpc_mmio_list_head] $r14
 293         st b16 D[$r0 + #gpc_mmio_list_tail] $r15
 294         call #mmctx_size
 295         add b32 $r2 $r15
 296         add b32 $r3 $r15
 297
 298         // calculate per-TPC mmio context size, store the list pointers
 299         ld b16 $r14 D[$r1 + 8]
 300         ld b16 $r15 D[$r1 + 10]
 301         st b16 D[$r0 + #tpc_mmio_list_head] $r14
 302         st b16 D[$r0 + #tpc_mmio_list_tail] $r15
 303         call #mmctx_size
 304         ld b32 $r14 D[$r0 + #tpc_count]
 305         mulu $r14 $r15
 306         add b32 $r2 $r14
 307         add b32 $r3 $r14
 308
 309         // round up base/size to 256 byte boundary (for strand SWBASE)
 310         add b32 $r4 0x1300
 311         shr b32 $r3 2
 312         iowr I[$r4 + 0x000] $r3         // MMCTX_LOAD_COUNT, wtf for?!?
 313         shr b32 $r2 8
 314         shr b32 $r3 6
 315         add b32 $r2 1
 316         add b32 $r3 1
 317         shl b32 $r2 8
 318         shl b32 $r3 8
 319
 320         // calculate size of strand context data
 321         mov b32 $r15 $r2
 322         call #strand_ctx_init
 323         add b32 $r3 $r15
 324
 325         // save context size, and tell HUB we're done
 326         mov $r1 0x800
 327         shl b32 $r1 6
 328         iowr I[$r1 + 0x100] $r3         // CC_SCRATCH[1]  = context size
 329         add b32 $r1 0x800
 330         clear b32 $r2
 331         bset $r2 31
 332         iowr I[$r1 + 0x000] $r2         // CC_SCRATCH[0] |= 0x80000000
 333
 334 // Main program loop, very simple, sleeps until woken up by the interrupt
 335 // handler, pulls a command from the queue and executes its handler
 336 //
 337 main:
 338         bset $flags $p0
 339         sleep $p0
 340         mov $r13 #cmd_queue
 341         call #queue_get
 342         bra $p1 #main
 343
 344         // 0x0000-0x0003 are all context transfers
 345         cmpu b32 $r14 0x04
 346         bra nc #main_not_ctx_xfer
 347                 // fetch $flags and mask off $p1/$p2
 348                 mov $r1 $flags
 349                 mov $r2 0x0006
 350                 not b32 $r2
 351                 and $r1 $r2
 352                 // set $p1/$p2 according to transfer type
 353                 shl b32 $r14 1
 354                 or $r1 $r14
 355                 mov $flags $r1
 356                 // transfer context data
 357                 call #ctx_xfer
 358                 bra #main
 359
 360         main_not_ctx_xfer:
 361         shl b32 $r15 $r14 16
 362         or $r15 E_BAD_COMMAND
 363         call #error
 364         bra #main
 365
 366 // interrupt handler
 367 ih:
 368         push $r8
 369         mov $r8 $flags
 370         push $r8
 371         push $r9
 372         push $r10
 373         push $r11
 374         push $r13
 375         push $r14
 376         push $r15
 377
 378         // incoming fifo command?
 379         iord $r10 I[$r0 + 0x200]        // INTR
 380         and $r11 $r10 0x00000004
 381         bra e #ih_no_fifo
 382                 // queue incoming fifo command for later processing
 383                 mov $r11 0x1900
 384                 mov $r13 #cmd_queue
 385                 iord $r14 I[$r11 + 0x100]       // FIFO_CMD
 386                 iord $r15 I[$r11 + 0x000]       // FIFO_DATA
 387                 call #queue_put
 388                 add b32 $r11 0x400
 389                 mov $r14 1
 390                 iowr I[$r11 + 0x000] $r14       // FIFO_ACK
 391
 392         // ack, and wake up main()
 393         ih_no_fifo:
 394         iowr I[$r0 + 0x100] $r10        // INTR_ACK
 395
 396         pop $r15
 397         pop $r14
 398         pop $r13
 399         pop $r11
 400         pop $r10
 401         pop $r9
 402         pop $r8
 403         mov $flags $r8
 404         pop $r8
 405         bclr $flags $p0
 406         iret
 407
 408 // Set this GPC's bit in HUB_BAR, used to signal completion of various
 409 // activities to the HUB fuc
 410 //
 411 hub_barrier_done:
 412         mov $r15 1
 413         ld b32 $r14 D[$r0 + #gpc_id]
 414         shl b32 $r15 $r14
 415         mov $r14 -0x6be8        // 0x409418 - HUB_BAR_SET
 416         sethi $r14 0x400000
 417         call #nv_wr32
 418         ret
 419
 420 // Disables various things, waits a bit, and re-enables them..
 421 //
 422 // Not sure how exactly this helps, perhaps "ENABLE" is not such a
 423 // good description for the bits we turn off?  Anyways, without this,
 424 // funny things happen.
 425 //
 426 ctx_redswitch:
 427         mov $r14 0x614
 428         shl b32 $r14 6
 429         mov $r15 0x020
 430         iowr I[$r14] $r15       // GPC_RED_SWITCH = POWER
 431         mov $r15 8
 432         ctx_redswitch_delay:
 433                 sub b32 $r15 1
 434                 bra ne #ctx_redswitch_delay
 435         mov $r15 0xa20
 436         iowr I[$r14] $r15       // GPC_RED_SWITCH = UNK11, ENABLE, POWER
 437         ret
 438
 439 // Transfer GPC context data between GPU and storage area
 440 //
 441 // In: $r15 context base address
 442 //     $p1 clear on save, set on load
 443 //     $p2 set if opposite direction done/will be done, so:
 444 //              on save it means: "a load will follow this save"
 445 //              on load it means: "a save preceeded this load"
 446 //
 447 ctx_xfer:
 448         // set context base address
 449         mov $r1 0xa04
 450         shl b32 $r1 6
 451         iowr I[$r1 + 0x000] $r15// MEM_BASE
 452         bra not $p1 #ctx_xfer_not_load
 453                 call #ctx_redswitch
 454         ctx_xfer_not_load:
 455
 456         // strands
 457         mov $r1 0x4afc
 458         sethi $r1 0x20000
 459         mov $r2 0xc
 460         iowr I[$r1] $r2         // STRAND_CMD(0x3f) = 0x0c
 461         call #strand_wait
 462         mov $r2 0x47fc
 463         sethi $r2 0x20000
 464         iowr I[$r2] $r0         // STRAND_FIRST_GENE(0x3f) = 0x00
 465         xbit $r2 $flags $p1
 466         add b32 $r2 3
 467         iowr I[$r1] $r2         // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)
 468
 469         // mmio context
 470         xbit $r10 $flags $p1    // direction
 471         or $r10 2               // first
 472         mov $r11 0x0000
 473         sethi $r11 0x500000
 474         ld b32 $r12 D[$r0 + #gpc_id]
 475         shl b32 $r12 15
 476         add b32 $r11 $r12       // base = NV_PGRAPH_GPCn
 477         ld b32 $r12 D[$r0 + #gpc_mmio_list_head]
 478         ld b32 $r13 D[$r0 + #gpc_mmio_list_tail]
 479         mov $r14 0              // not multi
 480         call #mmctx_xfer
 481
 482         // per-TPC mmio context
 483         xbit $r10 $flags $p1    // direction
 484         or $r10 4               // last
 485         mov $r11 0x4000
 486         sethi $r11 0x500000     // base = NV_PGRAPH_GPC0_TPC0
 487         ld b32 $r12 D[$r0 + #gpc_id]
 488         shl b32 $r12 15
 489         add b32 $r11 $r12       // base = NV_PGRAPH_GPCn_TPC0
 490         ld b32 $r12 D[$r0 + #tpc_mmio_list_head]
 491         ld b32 $r13 D[$r0 + #tpc_mmio_list_tail]
 492         ld b32 $r15 D[$r0 + #tpc_mask]
 493         mov $r14 0x800          // stride = 0x800
 494         call #mmctx_xfer
 495
 496         // wait for strands to finish
 497         call #strand_wait
 498
 499         // if load, or a save without a load following, do some
 500         // unknown stuff that's done after finishing a block of
 501         // strand commands
 502         bra $p1 #ctx_xfer_post
 503         bra not $p2 #ctx_xfer_done
 504         ctx_xfer_post:
 505                 mov $r1 0x4afc
 506                 sethi $r1 0x20000
 507                 mov $r2 0xd
 508                 iowr I[$r1] $r2         // STRAND_CMD(0x3f) = 0x0d
 509                 call #strand_wait
 510
 511         // mark completion in HUB's barrier
 512         ctx_xfer_done:
 513         call #hub_barrier_done
 514         ret
 515
 516 .align 256