1 uint32_t nve0_grgpc_data
[] = {
4 /* 0x0004: gpc_mmio_list_head */
6 /* 0x0008: gpc_mmio_list_tail */
8 /* 0x000c: tpc_count */
10 /* 0x0010: tpc_mask */
12 /* 0x0014: tpc_mmio_list_head */
14 /* 0x0018: tpc_mmio_list_tail */
16 /* 0x001c: cmd_queue */
35 /* 0x0064: chipsets */
46 /* 0x008c: nve4_gpc_mmio_head */
80 /* 0x0110: nve4_gpc_mmio_tail */
81 /* 0x0110: nve4_tpc_mmio_head */
100 /* 0x0158: nve4_tpc_mmio_tail */
101 /* 0x0158: nve6_tpc_mmio_head */
123 uint32_t nve0_grgpc_code
[] = {
125 /* 0x0004: queue_put */
132 /* 0x001c: queue_put_next */
140 /* 0x0039: queue_get */
152 /* 0x0066: queue_get_done */
154 /* 0x0068: nv_rd32 */
159 /* 0x0078: nv_rd32_wait */
165 /* 0x008d: nv_wr32 */
171 /* 0x00a3: nv_wr32_wait */
175 /* 0x00ae: watchdog_reset */
180 /* 0x00bd: watchdog_clear */
184 /* 0x00c9: wait_donez */
191 /* 0x00e2: wait_done_wait_donez */
200 /* 0x0103: wait_doneo */
208 /* 0x011c: wait_done_wait_doneo */
217 /* 0x013d: mmctx_size */
218 /* 0x013f: nv_mmctx_size_loop */
227 /* 0x015c: mmctx_xfer */
237 /* 0x0180: mmctx_base_disabled */
241 /* 0x018f: mmctx_multi_disabled */
249 /* 0x01a8: mmctx_exec_loop */
250 /* 0x01a8: mmctx_wait_free */
259 /* 0x01c9: mmctx_fini_wait */
265 /* 0x01de: mmctx_stop */
270 /* 0x01ed: mmctx_stop_wait */
273 /* 0x01f6: mmctx_done */
278 /* 0x0207: strand_wait */
282 /* 0x0213: strand_pre */
288 /* 0x0226: strand_post */
294 /* 0x0239: strand_set */
305 /* 0x0263: strand_ctx_init */
328 /* 0x02ba: ctx_init_strand_loop */
372 /* 0x035f: init_find_chipset */
378 /* 0x0373: init_context */
428 /* 0x0431: main_not_ctx_xfer */
447 /* 0x0474: ih_no_fifo */
454 /* 0x048f: hub_barrier_done */
461 /* 0x04a4: ctx_redswitch */
466 /* 0x04b4: ctx_redswitch_delay */
470 /* 0x04c3: ctx_xfer */
476 /* 0x04d4: ctx_xfer_not_load */
506 /* 0x054b: ctx_xfer_post */
512 /* 0x055c: ctx_xfer_done */
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