drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #ifndef __NVC0_GRAPH_H__
  26 #define __NVC0_GRAPH_H__
  27
  28 #include <core/client.h>
  29 #include <core/handle.h>
  30 #include <core/gpuobj.h>
  31 #include <core/option.h>
  32
  33 #include <subdev/fb.h>
  34 #include <subdev/vm.h>
  35 #include <subdev/bar.h>
  36 #include <subdev/timer.h>
  37
  38 #include <engine/graph.h>
  39
  40 #define GPC_MAX 4
  41 #define TPC_MAX 32
  42
  43 #define ROP_BCAST(r)      (0x408800 + (r))
  44 #define ROP_UNIT(u, r)    (0x410000 + (u) * 0x400 + (r))
  45 #define GPC_BCAST(r)      (0x418000 + (r))
  46 #define GPC_UNIT(t, r)    (0x500000 + (t) * 0x8000 + (r))
  47 #define TPC_UNIT(t, m, r) (0x504000 + (t) * 0x8000 + (m) * 0x800 + (r))
  48
  49 struct nvc0_graph_data {
  50         u32 size;
  51         u32 align;
  52         u32 access;
  53 };
  54
  55 struct nvc0_graph_mmio {
  56         u32 addr;
  57         u32 data;
  58         u32 shift;
  59         u32 buffer;
  60 };
  61
  62 struct nvc0_graph_fuc {
  63         u32 *data;
  64         u32  size;
  65 };
  66
  67 struct nvc0_graph_priv {
  68         struct nouveau_graph base;
  69
  70         struct nvc0_graph_fuc fuc409c;
  71         struct nvc0_graph_fuc fuc409d;
  72         struct nvc0_graph_fuc fuc41ac;
  73         struct nvc0_graph_fuc fuc41ad;
  74         bool firmware;
  75
  76         u8 rop_nr;
  77         u8 gpc_nr;
  78         u8 tpc_nr[GPC_MAX];
  79         u8 tpc_total;
  80
  81         struct nouveau_gpuobj *unk4188b4;
  82         struct nouveau_gpuobj *unk4188b8;
  83
  84         struct nvc0_graph_data mmio_data[4];
  85         struct nvc0_graph_mmio mmio_list[4096/8];
  86         u32  size;
  87         u32 *data;
  88
  89         u8 magic_not_rop_nr;
  90 };
  91
  92 struct nvc0_graph_chan {
  93         struct nouveau_graph_chan base;
  94
  95         struct nouveau_gpuobj *mmio;
  96         struct nouveau_vma mmio_vma;
  97         int mmio_nr;
  98         struct {
  99                 struct nouveau_gpuobj *mem;
 100                 struct nouveau_vma vma;
 101         } data[4];
 102 };
 103
 104 static inline u32
 105 nvc0_graph_class(void *obj)
 106 {
 107         struct nouveau_device *device = nv_device(obj);
 108
 109         switch (device->chipset) {
 110         case 0xc0:
 111         case 0xc3:
 112         case 0xc4:
 113         case 0xce: /* guess, mmio trace shows only 0x9097 state */
 114         case 0xcf: /* guess, mmio trace shows only 0x9097 state */
 115                 return 0x9097;
 116         case 0xc1:
 117                 return 0x9197;
 118         case 0xc8:
 119         case 0xd9:
 120                 return 0x9297;
 121         case 0xe4:
 122         case 0xe7:
 123                 return 0xa097;
 124         default:
 125                 return 0;
 126         }
 127 }
 128
 129 void nv_icmd(struct nvc0_graph_priv *priv, u32 icmd, u32 data);
 130
 131 static inline void
 132 nv_mthd(struct nvc0_graph_priv *priv, u32 class, u32 mthd, u32 data)
 133 {
 134         nv_wr32(priv, 0x40448c, data);
 135         nv_wr32(priv, 0x404488, 0x80000000 | (mthd << 14) | class);
 136 }
 137
 138 struct nvc0_grctx {
 139         struct nvc0_graph_priv *priv;
 140         struct nvc0_graph_data *data;
 141         struct nvc0_graph_mmio *mmio;
 142         struct nouveau_gpuobj *chan;
 143         int buffer_nr;
 144         u64 buffer[4];
 145         u64 addr;
 146 };
 147
 148 int  nvc0_grctx_generate(struct nvc0_graph_priv *);
 149 int  nvc0_grctx_init(struct nvc0_graph_priv *, struct nvc0_grctx *);
 150 void nvc0_grctx_data(struct nvc0_grctx *, u32, u32, u32);
 151 void nvc0_grctx_mmio(struct nvc0_grctx *, u32, u32, u32, u32);
 152 int  nvc0_grctx_fini(struct nvc0_grctx *);
 153
 154 int  nve0_grctx_generate(struct nvc0_graph_priv *);
 155
 156 #define mmio_data(s,a,p) nvc0_grctx_data(&info, (s), (a), (p))
 157 #define mmio_list(r,d,s,b) nvc0_grctx_mmio(&info, (r), (d), (s), (b))
 158
 159 void nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *);
 160 int  nvc0_graph_ctor_fw(struct nvc0_graph_priv *, const char *,
 161                         struct nvc0_graph_fuc *);
 162 void nvc0_graph_dtor(struct nouveau_object *);
 163 void nvc0_graph_init_fw(struct nvc0_graph_priv *, u32 base,
 164                         struct nvc0_graph_fuc *, struct nvc0_graph_fuc *);
 165 int  nvc0_graph_context_ctor(struct nouveau_object *, struct nouveau_object *,
 166                              struct nouveau_oclass *, void *, u32,
 167                              struct nouveau_object **);
 168 void nvc0_graph_context_dtor(struct nouveau_object *);
 169
 170 #endif