Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / engine / graph / nvd9.c
1 /*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24
25 #include "nvc0.h"
26
27 /*******************************************************************************
28 * PGRAPH engine/subdev functions
29 ******************************************************************************/
30
31 struct nvc0_graph_init
32 nvd9_graph_init_unk64xx[] = {
33 { 0x4064f0, 3, 0x04, 0x00000000 },
34 {}
35 };
36
37 struct nvc0_graph_init
38 nvd9_graph_init_unk58xx[] = {
39 { 0x405844, 1, 0x04, 0x00ffffff },
40 { 0x405850, 1, 0x04, 0x00000000 },
41 { 0x405900, 1, 0x04, 0x00002834 },
42 { 0x405908, 1, 0x04, 0x00000000 },
43 { 0x405928, 1, 0x04, 0x00000000 },
44 { 0x40592c, 1, 0x04, 0x00000000 },
45 {}
46 };
47
48 static struct nvc0_graph_init
49 nvd9_graph_init_gpc[] = {
50 { 0x418408, 1, 0x04, 0x00000000 },
51 { 0x4184a0, 1, 0x04, 0x00000000 },
52 { 0x4184a4, 2, 0x04, 0x00000000 },
53 { 0x418604, 1, 0x04, 0x00000000 },
54 { 0x418680, 1, 0x04, 0x00000000 },
55 { 0x418714, 1, 0x04, 0x00000000 },
56 { 0x418384, 1, 0x04, 0x00000000 },
57 { 0x418814, 3, 0x04, 0x00000000 },
58 { 0x418b04, 1, 0x04, 0x00000000 },
59 { 0x4188c8, 2, 0x04, 0x00000000 },
60 { 0x4188d0, 1, 0x04, 0x00010000 },
61 { 0x4188d4, 1, 0x04, 0x00000001 },
62 { 0x418910, 1, 0x04, 0x00010001 },
63 { 0x418914, 1, 0x04, 0x00000301 },
64 { 0x418918, 1, 0x04, 0x00800000 },
65 { 0x418980, 1, 0x04, 0x77777770 },
66 { 0x418984, 3, 0x04, 0x77777777 },
67 { 0x418c04, 1, 0x04, 0x00000000 },
68 { 0x418c64, 1, 0x04, 0x00000000 },
69 { 0x418c68, 1, 0x04, 0x00000000 },
70 { 0x418c88, 1, 0x04, 0x00000000 },
71 { 0x418cb4, 2, 0x04, 0x00000000 },
72 { 0x418d00, 1, 0x04, 0x00000000 },
73 { 0x418d28, 1, 0x04, 0x00000000 },
74 { 0x418d2c, 1, 0x04, 0x00000000 },
75 { 0x418f00, 1, 0x04, 0x00000000 },
76 { 0x418f08, 1, 0x04, 0x00000000 },
77 { 0x418f20, 2, 0x04, 0x00000000 },
78 { 0x418e00, 1, 0x04, 0x00000003 },
79 { 0x418e08, 1, 0x04, 0x00000000 },
80 { 0x418e1c, 1, 0x04, 0x00000000 },
81 { 0x418e20, 1, 0x04, 0x00000000 },
82 { 0x41900c, 1, 0x04, 0x00000000 },
83 { 0x419018, 1, 0x04, 0x00000000 },
84 {}
85 };
86
87 static struct nvc0_graph_init
88 nvd9_graph_init_tpc[] = {
89 { 0x419d08, 2, 0x04, 0x00000000 },
90 { 0x419d10, 1, 0x04, 0x00000014 },
91 { 0x419ab0, 1, 0x04, 0x00000000 },
92 { 0x419ac8, 1, 0x04, 0x00000000 },
93 { 0x419ab8, 1, 0x04, 0x000000e7 },
94 { 0x419abc, 2, 0x04, 0x00000000 },
95 { 0x419ab4, 1, 0x04, 0x00000000 },
96 { 0x41980c, 1, 0x04, 0x00000010 },
97 { 0x419810, 1, 0x04, 0x00000000 },
98 { 0x419814, 1, 0x04, 0x00000004 },
99 { 0x419844, 1, 0x04, 0x00000000 },
100 { 0x41984c, 1, 0x04, 0x0000a918 },
101 { 0x419850, 4, 0x04, 0x00000000 },
102 { 0x419880, 1, 0x04, 0x00000002 },
103 { 0x419c98, 1, 0x04, 0x00000000 },
104 { 0x419ca8, 1, 0x04, 0x80000000 },
105 { 0x419cb4, 1, 0x04, 0x00000000 },
106 { 0x419cb8, 1, 0x04, 0x00008bf4 },
107 { 0x419cbc, 1, 0x04, 0x28137606 },
108 { 0x419cc0, 2, 0x04, 0x00000000 },
109 { 0x419bd4, 1, 0x04, 0x00800000 },
110 { 0x419bdc, 1, 0x04, 0x00000000 },
111 { 0x419bf8, 1, 0x04, 0x00000000 },
112 { 0x419bfc, 1, 0x04, 0x00000000 },
113 { 0x419d2c, 1, 0x04, 0x00000000 },
114 { 0x419d48, 1, 0x04, 0x00000000 },
115 { 0x419d4c, 1, 0x04, 0x00000000 },
116 { 0x419c0c, 1, 0x04, 0x00000000 },
117 { 0x419e00, 1, 0x04, 0x00000000 },
118 { 0x419ea0, 1, 0x04, 0x00000000 },
119 { 0x419ea4, 1, 0x04, 0x00000100 },
120 { 0x419ea8, 1, 0x04, 0x02001100 },
121 { 0x419eac, 1, 0x04, 0x11100702 },
122 { 0x419eb0, 1, 0x04, 0x00000003 },
123 { 0x419eb4, 4, 0x04, 0x00000000 },
124 { 0x419ec8, 1, 0x04, 0x0e063818 },
125 { 0x419ecc, 1, 0x04, 0x0e060e06 },
126 { 0x419ed0, 1, 0x04, 0x00003818 },
127 { 0x419ed4, 1, 0x04, 0x011104f1 },
128 { 0x419edc, 1, 0x04, 0x00000000 },
129 { 0x419f00, 1, 0x04, 0x00000000 },
130 { 0x419f2c, 1, 0x04, 0x00000000 },
131 {}
132 };
133
134 static struct nvc0_graph_init *
135 nvd9_graph_init_mmio[] = {
136 nvc0_graph_init_regs,
137 nvc0_graph_init_unk40xx,
138 nvc0_graph_init_unk44xx,
139 nvc0_graph_init_unk78xx,
140 nvc0_graph_init_unk60xx,
141 nvd9_graph_init_unk64xx,
142 nvd9_graph_init_unk58xx,
143 nvc0_graph_init_unk80xx,
144 nvd9_graph_init_gpc,
145 nvd9_graph_init_tpc,
146 nvc0_graph_init_unk88xx,
147 nvc0_graph_tpc_0,
148 NULL
149 };
150
151 struct nouveau_oclass *
152 nvd9_graph_oclass = &(struct nvc0_graph_oclass) {
153 .base.handle = NV_ENGINE(GR, 0xd9),
154 .base.ofuncs = &(struct nouveau_ofuncs) {
155 .ctor = nvc0_graph_ctor,
156 .dtor = nvc0_graph_dtor,
157 .init = nvc0_graph_init,
158 .fini = _nouveau_graph_fini,
159 },
160 .cclass = &nvd9_grctx_oclass,
161 .sclass = nvc8_graph_sclass,
162 .mmio = nvd9_graph_init_mmio,
163 .fecs.ucode = &nvc0_graph_fecs_ucode,
164 .gpccs.ucode = &nvc0_graph_gpccs_ucode,
165 }.base;
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