2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "fuc/hubnve0.fuc.h"
27 #include "fuc/gpcnve0.fuc.h"
29 /*******************************************************************************
30 * Graphics object classes
31 ******************************************************************************/
33 static struct nouveau_oclass
34 nve0_graph_sclass
[] = {
35 { 0x902d, &nouveau_object_ofuncs
},
36 { 0xa040, &nouveau_object_ofuncs
},
37 { 0xa097, &nouveau_object_ofuncs
},
38 { 0xa0c0, &nouveau_object_ofuncs
},
42 /*******************************************************************************
44 ******************************************************************************/
46 static struct nouveau_oclass
48 .handle
= NV_ENGCTX(GR
, 0xe0),
49 .ofuncs
= &(struct nouveau_ofuncs
) {
50 .ctor
= nvc0_graph_context_ctor
,
51 .dtor
= nvc0_graph_context_dtor
,
52 .init
= _nouveau_graph_context_init
,
53 .fini
= _nouveau_graph_context_fini
,
54 .rd32
= _nouveau_graph_context_rd32
,
55 .wr32
= _nouveau_graph_context_wr32
,
59 /*******************************************************************************
60 * PGRAPH engine/subdev functions
61 ******************************************************************************/
64 nve0_graph_ctxctl_isr(struct nvc0_graph_priv
*priv
)
66 u32 ustat
= nv_rd32(priv
, 0x409c18);
68 if (ustat
& 0x00000001)
69 nv_error(priv
, "CTXCTRL ucode error\n");
70 if (ustat
& 0x00080000)
71 nv_error(priv
, "CTXCTRL watchdog timeout\n");
72 if (ustat
& ~0x00080001)
73 nv_error(priv
, "CTXCTRL 0x%08x\n", ustat
);
75 nvc0_graph_ctxctl_debug(priv
);
76 nv_wr32(priv
, 0x409c20, ustat
);
79 static const struct nouveau_enum nve0_mp_warp_error
[] = {
81 { 0x01, "STACK_MISMATCH" },
82 { 0x05, "MISALIGNED_PC" },
83 { 0x08, "MISALIGNED_GPR" },
84 { 0x09, "INVALID_OPCODE" },
85 { 0x0d, "GPR_OUT_OF_BOUNDS" },
86 { 0x0e, "MEM_OUT_OF_BOUNDS" },
87 { 0x0f, "UNALIGNED_MEM_ACCESS" },
88 { 0x11, "INVALID_PARAM" },
92 static const struct nouveau_enum nve0_mp_global_error
[] = {
93 { 2, "MULTIPLE_WARP_ERRORS" },
94 { 3, "OUT_OF_STACK_SPACE" },
98 static const struct nouveau_enum nve0_gpc_rop_error
[] = {
99 { 1, "RT_PITCH_OVERRUN" },
100 { 4, "RT_WIDTH_OVERRUN" },
101 { 5, "RT_HEIGHT_OVERRUN" },
102 { 7, "ZETA_STORAGE_TYPE_MISMATCH" },
103 { 8, "RT_STORAGE_TYPE_MISMATCH" },
104 { 10, "RT_LINEAR_MISMATCH" },
108 static const struct nouveau_enum nve0_sked_error
[] = {
109 { 7, "CONSTANT_BUFFER_SIZE" },
110 { 9, "LOCAL_MEMORY_SIZE_POS" },
111 { 10, "LOCAL_MEMORY_SIZE_NEG" },
112 { 11, "WARP_CSTACK_SIZE" },
113 { 12, "TOTAL_TEMP_SIZE" },
114 { 13, "REGISTER_COUNT" },
115 { 18, "TOTAL_THREADS" },
116 { 20, "PROGRAM_OFFSET" },
117 { 21, "SHARED_MEMORY_SIZE" },
118 { 25, "SHARED_CONFIG_TOO_SMALL" },
119 { 26, "TOTAL_REGISTER_COUNT" },
124 nve0_graph_mp_trap(struct nvc0_graph_priv
*priv
, int gpc
, int tpc
)
126 u32 werr
= nv_rd32(priv
, TPC_UNIT(gpc
, tpc
, 0x648));
127 u32 gerr
= nv_rd32(priv
, TPC_UNIT(gpc
, tpc
, 0x650));
130 nv_error(priv
, "GPC%i/TPC%i/MP trap:", gpc
, tpc
);
132 for (i
= 0; i
<= 31; ++i
) {
133 if (!(gerr
& (1 << i
)))
136 nouveau_enum_print(nve0_mp_global_error
, i
);
141 nouveau_enum_print(nve0_mp_warp_error
, werr
& 0xffff);
145 /* disable MP trap to avoid spam */
146 nv_mask(priv
, TPC_UNIT(gpc
, tpc
, 0x50c), 0x2, 0x0);
148 /* TODO: figure out how to resume after an MP trap */
152 nve0_graph_tpc_trap(struct nvc0_graph_priv
*priv
, int gpc
, int tpc
)
154 u32 stat
= nv_rd32(priv
, TPC_UNIT(gpc
, tpc
, 0x508));
157 u32 trap
= nv_rd32(priv
, TPC_UNIT(gpc
, tpc
, 0x224));
158 nv_error(priv
, "GPC%i/TPC%i/TEX trap: %08x\n",
161 nv_wr32(priv
, TPC_UNIT(gpc
, tpc
, 0x224), 0xc0000000);
166 nve0_graph_mp_trap(priv
, gpc
, tpc
);
171 u32 trap
= nv_rd32(priv
, TPC_UNIT(gpc
, tpc
, 0x084));
172 nv_error(priv
, "GPC%i/TPC%i/POLY trap: %08x\n",
175 nv_wr32(priv
, TPC_UNIT(gpc
, tpc
, 0x084), 0xc0000000);
180 u32 trap
= nv_rd32(priv
, TPC_UNIT(gpc
, tpc
, 0x48c));
181 nv_error(priv
, "GPC%i/TPC%i/L1C trap: %08x\n",
184 nv_wr32(priv
, TPC_UNIT(gpc
, tpc
, 0x48c), 0xc0000000);
189 nv_error(priv
, "GPC%i/TPC%i: unknown stat %08x\n",
195 nve0_graph_gpc_trap(struct nvc0_graph_priv
*priv
)
197 const u32 mask
= nv_rd32(priv
, 0x400118);
200 for (gpc
= 0; gpc
< 4; ++gpc
) {
204 if (!(mask
& (1 << gpc
)))
206 stat
= nv_rd32(priv
, GPC_UNIT(gpc
, 0x2c90));
212 trap
[0] = nv_rd32(priv
, GPC_UNIT(gpc
, 0x0420));
213 trap
[1] = nv_rd32(priv
, GPC_UNIT(gpc
, 0x0434));
214 trap
[2] = nv_rd32(priv
, GPC_UNIT(gpc
, 0x0438));
215 trap
[3] = nv_rd32(priv
, GPC_UNIT(gpc
, 0x043c));
217 nv_error(priv
, "GPC%i/PROP trap:", gpc
);
218 for (i
= 0; i
<= 29; ++i
) {
219 if (!(trap
[0] & (1 << i
)))
222 nouveau_enum_print(nve0_gpc_rop_error
, i
);
226 nv_error(priv
, "x = %u, y = %u, "
227 "format = %x, storage type = %x\n",
230 (trap
[2] >> 8) & 0x3f,
233 nv_wr32(priv
, GPC_UNIT(gpc
, 0x0420), 0xc0000000);
238 u32 trap
= nv_rd32(priv
, GPC_UNIT(gpc
, 0x0900));
239 nv_error(priv
, "GPC%i/ZCULL trap: %08x\n", gpc
,
241 nv_wr32(priv
, GPC_UNIT(gpc
, 0x0900), 0xc0000000);
246 u32 trap
= nv_rd32(priv
, GPC_UNIT(gpc
, 0x1028));
247 nv_error(priv
, "GPC%i/CCACHE trap: %08x\n", gpc
,
249 nv_wr32(priv
, GPC_UNIT(gpc
, 0x1028), 0xc0000000);
254 u32 trap
= nv_rd32(priv
, GPC_UNIT(gpc
, 0x0824));
255 nv_error(priv
, "GPC%i/ESETUP trap %08x\n", gpc
,
257 nv_wr32(priv
, GPC_UNIT(gpc
, 0x0824), 0xc0000000);
261 for (tpc
= 0; tpc
< 8; ++tpc
) {
262 if (stat
& (1 << (16 + tpc
)))
263 nve0_graph_tpc_trap(priv
, gpc
, tpc
);
268 nv_error(priv
, "GPC%i: unknown stat %08x\n",
276 nve0_graph_trap_isr(struct nvc0_graph_priv
*priv
, int chid
, u64 inst
,
277 struct nouveau_object
*engctx
)
279 u32 trap
= nv_rd32(priv
, 0x400108);
283 if (trap
& 0x00000001) {
284 u32 stat
= nv_rd32(priv
, 0x404000);
285 nv_error(priv
, "DISPATCH ch %d [0x%010llx %s] 0x%08x\n",
286 chid
, inst
, nouveau_client_name(engctx
), stat
);
287 nv_wr32(priv
, 0x404000, 0xc0000000);
288 nv_wr32(priv
, 0x400108, 0x00000001);
292 if (trap
& 0x00000010) {
293 u32 stat
= nv_rd32(priv
, 0x405840);
294 nv_error(priv
, "SHADER ch %d [0x%010llx %s] 0x%08x\n",
295 chid
, inst
, nouveau_client_name(engctx
), stat
);
296 nv_wr32(priv
, 0x405840, 0xc0000000);
297 nv_wr32(priv
, 0x400108, 0x00000010);
301 if (trap
& 0x00000100) {
302 u32 stat
= nv_rd32(priv
, 0x407020);
303 nv_error(priv
, "SKED ch %d [0x%010llx %s]:",
304 chid
, inst
, nouveau_client_name(engctx
));
306 for (i
= 0; i
<= 29; ++i
) {
307 if (!(stat
& (1 << i
)))
310 nouveau_enum_print(nve0_sked_error
, i
);
314 if (stat
& 0x3fffffff)
315 nv_wr32(priv
, 0x407020, 0x40000000);
316 nv_wr32(priv
, 0x400108, 0x00000100);
320 if (trap
& 0x01000000) {
321 nv_error(priv
, "GPC ch %d [0x%010llx %s]:\n",
322 chid
, inst
, nouveau_client_name(engctx
));
323 nve0_graph_gpc_trap(priv
);
327 if (trap
& 0x02000000) {
328 for (rop
= 0; rop
< priv
->rop_nr
; rop
++) {
329 u32 statz
= nv_rd32(priv
, ROP_UNIT(rop
, 0x070));
330 u32 statc
= nv_rd32(priv
, ROP_UNIT(rop
, 0x144));
332 "ROP%d ch %d [0x%010llx %s] 0x%08x 0x%08x\n",
333 rop
, chid
, inst
, nouveau_client_name(engctx
),
335 nv_wr32(priv
, ROP_UNIT(rop
, 0x070), 0xc0000000);
336 nv_wr32(priv
, ROP_UNIT(rop
, 0x144), 0xc0000000);
338 nv_wr32(priv
, 0x400108, 0x02000000);
343 nv_error(priv
, "TRAP ch %d [0x%010llx %s] 0x%08x\n",
344 chid
, inst
, nouveau_client_name(engctx
), trap
);
345 nv_wr32(priv
, 0x400108, trap
);
350 nve0_graph_intr(struct nouveau_subdev
*subdev
)
352 struct nouveau_fifo
*pfifo
= nouveau_fifo(subdev
);
353 struct nouveau_engine
*engine
= nv_engine(subdev
);
354 struct nouveau_object
*engctx
;
355 struct nouveau_handle
*handle
;
356 struct nvc0_graph_priv
*priv
= (void *)subdev
;
357 u64 inst
= nv_rd32(priv
, 0x409b00) & 0x0fffffff;
358 u32 stat
= nv_rd32(priv
, 0x400100);
359 u32 addr
= nv_rd32(priv
, 0x400704);
360 u32 mthd
= (addr
& 0x00003ffc);
361 u32 subc
= (addr
& 0x00070000) >> 16;
362 u32 data
= nv_rd32(priv
, 0x400708);
363 u32 code
= nv_rd32(priv
, 0x400110);
364 u32
class = nv_rd32(priv
, 0x404200 + (subc
* 4));
367 engctx
= nouveau_engctx_get(engine
, inst
);
368 chid
= pfifo
->chid(pfifo
, engctx
);
370 if (stat
& 0x00000010) {
371 handle
= nouveau_handle_get_class(engctx
, class);
372 if (!handle
|| nv_call(handle
->object
, mthd
, data
)) {
374 "ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
375 chid
, inst
, nouveau_client_name(engctx
), subc
,
378 nouveau_handle_put(handle
);
379 nv_wr32(priv
, 0x400100, 0x00000010);
383 if (stat
& 0x00000020) {
385 "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
386 chid
, inst
, nouveau_client_name(engctx
), subc
, class,
388 nv_wr32(priv
, 0x400100, 0x00000020);
392 if (stat
& 0x00100000) {
393 nv_error(priv
, "DATA_ERROR [");
394 nouveau_enum_print(nv50_data_error_names
, code
);
395 pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
396 chid
, inst
, nouveau_client_name(engctx
), subc
, class,
398 nv_wr32(priv
, 0x400100, 0x00100000);
402 if (stat
& 0x00200000) {
403 nve0_graph_trap_isr(priv
, chid
, inst
, engctx
);
404 nv_wr32(priv
, 0x400100, 0x00200000);
408 if (stat
& 0x00080000) {
409 nve0_graph_ctxctl_isr(priv
);
410 nv_wr32(priv
, 0x400100, 0x00080000);
415 nv_error(priv
, "unknown stat 0x%08x\n", stat
);
416 nv_wr32(priv
, 0x400100, stat
);
419 nv_wr32(priv
, 0x400500, 0x00010001);
420 nouveau_engctx_put(engctx
);
424 nve0_graph_ctor(struct nouveau_object
*parent
, struct nouveau_object
*engine
,
425 struct nouveau_oclass
*oclass
, void *data
, u32 size
,
426 struct nouveau_object
**pobject
)
428 struct nouveau_device
*device
= nv_device(parent
);
429 struct nvc0_graph_priv
*priv
;
432 ret
= nouveau_graph_create(parent
, engine
, oclass
, true, &priv
);
433 *pobject
= nv_object(priv
);
437 nv_subdev(priv
)->unit
= 0x18001000;
438 nv_subdev(priv
)->intr
= nve0_graph_intr
;
439 nv_engine(priv
)->cclass
= &nve0_graph_cclass
;
440 nv_engine(priv
)->sclass
= nve0_graph_sclass
;
442 priv
->base
.units
= nvc0_graph_units
;
444 if (nouveau_boolopt(device
->cfgopt
, "NvGrUseFW", false)) {
445 nv_info(priv
, "using external firmware\n");
446 if (nvc0_graph_ctor_fw(priv
, "fuc409c", &priv
->fuc409c
) ||
447 nvc0_graph_ctor_fw(priv
, "fuc409d", &priv
->fuc409d
) ||
448 nvc0_graph_ctor_fw(priv
, "fuc41ac", &priv
->fuc41ac
) ||
449 nvc0_graph_ctor_fw(priv
, "fuc41ad", &priv
->fuc41ad
))
451 priv
->firmware
= true;
454 ret
= nouveau_gpuobj_new(nv_object(priv
), NULL
, 0x1000, 256, 0,
459 ret
= nouveau_gpuobj_new(nv_object(priv
), NULL
, 0x1000, 256, 0,
464 for (i
= 0; i
< 0x1000; i
+= 4) {
465 nv_wo32(priv
->unk4188b4
, i
, 0x00000010);
466 nv_wo32(priv
->unk4188b8
, i
, 0x00000010);
469 priv
->gpc_nr
= nv_rd32(priv
, 0x409604) & 0x0000001f;
470 priv
->rop_nr
= (nv_rd32(priv
, 0x409604) & 0x001f0000) >> 16;
471 for (i
= 0; i
< priv
->gpc_nr
; i
++) {
472 priv
->tpc_nr
[i
] = nv_rd32(priv
, GPC_UNIT(i
, 0x2608));
473 priv
->tpc_total
+= priv
->tpc_nr
[i
];
476 switch (nv_device(priv
)->chipset
) {
478 if (priv
->tpc_total
== 8)
479 priv
->magic_not_rop_nr
= 3;
481 if (priv
->tpc_total
== 7)
482 priv
->magic_not_rop_nr
= 1;
486 priv
->magic_not_rop_nr
= 1;
496 nve0_graph_init_obj418880(struct nvc0_graph_priv
*priv
)
500 nv_wr32(priv
, GPC_BCAST(0x0880), 0x00000000);
501 nv_wr32(priv
, GPC_BCAST(0x08a4), 0x00000000);
502 for (i
= 0; i
< 4; i
++)
503 nv_wr32(priv
, GPC_BCAST(0x0888) + (i
* 4), 0x00000000);
504 nv_wr32(priv
, GPC_BCAST(0x08b4), priv
->unk4188b4
->addr
>> 8);
505 nv_wr32(priv
, GPC_BCAST(0x08b8), priv
->unk4188b8
->addr
>> 8);
509 nve0_graph_init_regs(struct nvc0_graph_priv
*priv
)
511 nv_wr32(priv
, 0x400080, 0x003083c2);
512 nv_wr32(priv
, 0x400088, 0x0001ffe7);
513 nv_wr32(priv
, 0x40008c, 0x00000000);
514 nv_wr32(priv
, 0x400090, 0x00000030);
515 nv_wr32(priv
, 0x40013c, 0x003901f7);
516 nv_wr32(priv
, 0x400140, 0x00000100);
517 nv_wr32(priv
, 0x400144, 0x00000000);
518 nv_wr32(priv
, 0x400148, 0x00000110);
519 nv_wr32(priv
, 0x400138, 0x00000000);
520 nv_wr32(priv
, 0x400130, 0x00000000);
521 nv_wr32(priv
, 0x400134, 0x00000000);
522 nv_wr32(priv
, 0x400124, 0x00000002);
526 nve0_graph_init_units(struct nvc0_graph_priv
*priv
)
528 nv_wr32(priv
, 0x409ffc, 0x00000000);
529 nv_wr32(priv
, 0x409c14, 0x00003e3e);
530 nv_wr32(priv
, 0x409c24, 0x000f0000);
532 nv_wr32(priv
, 0x404000, 0xc0000000);
533 nv_wr32(priv
, 0x404600, 0xc0000000);
534 nv_wr32(priv
, 0x408030, 0xc0000000);
535 nv_wr32(priv
, 0x404490, 0xc0000000);
536 nv_wr32(priv
, 0x406018, 0xc0000000);
537 nv_wr32(priv
, 0x407020, 0xc0000000);
538 nv_wr32(priv
, 0x405840, 0xc0000000);
539 nv_wr32(priv
, 0x405844, 0x00ffffff);
541 nv_mask(priv
, 0x419cc0, 0x00000008, 0x00000008);
542 nv_mask(priv
, 0x419eb4, 0x00001000, 0x00001000);
547 nve0_graph_init_gpc_0(struct nvc0_graph_priv
*priv
)
549 const u32 magicgpc918
= DIV_ROUND_UP(0x00800000, priv
->tpc_total
);
550 u32 data
[TPC_MAX
/ 8];
554 nv_wr32(priv
, GPC_UNIT(0, 0x3018), 0x00000001);
556 memset(data
, 0x00, sizeof(data
));
557 memcpy(tpcnr
, priv
->tpc_nr
, sizeof(priv
->tpc_nr
));
558 for (i
= 0, gpc
= -1; i
< priv
->tpc_total
; i
++) {
560 gpc
= (gpc
+ 1) % priv
->gpc_nr
;
561 } while (!tpcnr
[gpc
]);
562 tpc
= priv
->tpc_nr
[gpc
] - tpcnr
[gpc
]--;
564 data
[i
/ 8] |= tpc
<< ((i
% 8) * 4);
567 nv_wr32(priv
, GPC_BCAST(0x0980), data
[0]);
568 nv_wr32(priv
, GPC_BCAST(0x0984), data
[1]);
569 nv_wr32(priv
, GPC_BCAST(0x0988), data
[2]);
570 nv_wr32(priv
, GPC_BCAST(0x098c), data
[3]);
572 for (gpc
= 0; gpc
< priv
->gpc_nr
; gpc
++) {
573 nv_wr32(priv
, GPC_UNIT(gpc
, 0x0914), priv
->magic_not_rop_nr
<< 8 |
575 nv_wr32(priv
, GPC_UNIT(gpc
, 0x0910), 0x00040000 | priv
->tpc_total
);
576 nv_wr32(priv
, GPC_UNIT(gpc
, 0x0918), magicgpc918
);
579 nv_wr32(priv
, GPC_BCAST(0x3fd4), magicgpc918
);
580 nv_wr32(priv
, GPC_BCAST(0x08ac), nv_rd32(priv
, 0x100800));
584 nve0_graph_init_gpc_1(struct nvc0_graph_priv
*priv
)
588 for (gpc
= 0; gpc
< priv
->gpc_nr
; gpc
++) {
589 nv_wr32(priv
, GPC_UNIT(gpc
, 0x3038), 0xc0000000);
590 nv_wr32(priv
, GPC_UNIT(gpc
, 0x0420), 0xc0000000);
591 nv_wr32(priv
, GPC_UNIT(gpc
, 0x0900), 0xc0000000);
592 nv_wr32(priv
, GPC_UNIT(gpc
, 0x1028), 0xc0000000);
593 nv_wr32(priv
, GPC_UNIT(gpc
, 0x0824), 0xc0000000);
594 for (tpc
= 0; tpc
< priv
->tpc_nr
[gpc
]; tpc
++) {
595 nv_wr32(priv
, TPC_UNIT(gpc
, tpc
, 0x508), 0xffffffff);
596 nv_wr32(priv
, TPC_UNIT(gpc
, tpc
, 0x50c), 0xffffffff);
597 nv_wr32(priv
, TPC_UNIT(gpc
, tpc
, 0x224), 0xc0000000);
598 nv_wr32(priv
, TPC_UNIT(gpc
, tpc
, 0x48c), 0xc0000000);
599 nv_wr32(priv
, TPC_UNIT(gpc
, tpc
, 0x084), 0xc0000000);
600 nv_wr32(priv
, TPC_UNIT(gpc
, tpc
, 0x644), 0x001ffffe);
601 nv_wr32(priv
, TPC_UNIT(gpc
, tpc
, 0x64c), 0x0000000f);
603 nv_wr32(priv
, GPC_UNIT(gpc
, 0x2c90), 0xffffffff);
604 nv_wr32(priv
, GPC_UNIT(gpc
, 0x2c94), 0xffffffff);
609 nve0_graph_init_rop(struct nvc0_graph_priv
*priv
)
613 for (rop
= 0; rop
< priv
->rop_nr
; rop
++) {
614 nv_wr32(priv
, ROP_UNIT(rop
, 0x144), 0xc0000000);
615 nv_wr32(priv
, ROP_UNIT(rop
, 0x070), 0xc0000000);
616 nv_wr32(priv
, ROP_UNIT(rop
, 0x204), 0xffffffff);
617 nv_wr32(priv
, ROP_UNIT(rop
, 0x208), 0xffffffff);
622 nve0_graph_init_ctxctl(struct nvc0_graph_priv
*priv
)
627 if (priv
->firmware
) {
628 /* load fuc microcode */
629 r000260
= nv_mask(priv
, 0x000260, 0x00000001, 0x00000000);
630 nvc0_graph_init_fw(priv
, 0x409000, &priv
->fuc409c
, &priv
->fuc409d
);
631 nvc0_graph_init_fw(priv
, 0x41a000, &priv
->fuc41ac
, &priv
->fuc41ad
);
632 nv_wr32(priv
, 0x000260, r000260
);
634 /* start both of them running */
635 nv_wr32(priv
, 0x409840, 0xffffffff);
636 nv_wr32(priv
, 0x41a10c, 0x00000000);
637 nv_wr32(priv
, 0x40910c, 0x00000000);
638 nv_wr32(priv
, 0x41a100, 0x00000002);
639 nv_wr32(priv
, 0x409100, 0x00000002);
640 if (!nv_wait(priv
, 0x409800, 0x00000001, 0x00000001))
641 nv_error(priv
, "0x409800 wait failed\n");
643 nv_wr32(priv
, 0x409840, 0xffffffff);
644 nv_wr32(priv
, 0x409500, 0x7fffffff);
645 nv_wr32(priv
, 0x409504, 0x00000021);
647 nv_wr32(priv
, 0x409840, 0xffffffff);
648 nv_wr32(priv
, 0x409500, 0x00000000);
649 nv_wr32(priv
, 0x409504, 0x00000010);
650 if (!nv_wait_ne(priv
, 0x409800, 0xffffffff, 0x00000000)) {
651 nv_error(priv
, "fuc09 req 0x10 timeout\n");
654 priv
->size
= nv_rd32(priv
, 0x409800);
656 nv_wr32(priv
, 0x409840, 0xffffffff);
657 nv_wr32(priv
, 0x409500, 0x00000000);
658 nv_wr32(priv
, 0x409504, 0x00000016);
659 if (!nv_wait_ne(priv
, 0x409800, 0xffffffff, 0x00000000)) {
660 nv_error(priv
, "fuc09 req 0x16 timeout\n");
664 nv_wr32(priv
, 0x409840, 0xffffffff);
665 nv_wr32(priv
, 0x409500, 0x00000000);
666 nv_wr32(priv
, 0x409504, 0x00000025);
667 if (!nv_wait_ne(priv
, 0x409800, 0xffffffff, 0x00000000)) {
668 nv_error(priv
, "fuc09 req 0x25 timeout\n");
672 nv_wr32(priv
, 0x409800, 0x00000000);
673 nv_wr32(priv
, 0x409500, 0x00000001);
674 nv_wr32(priv
, 0x409504, 0x00000030);
675 if (!nv_wait_ne(priv
, 0x409800, 0xffffffff, 0x00000000)) {
676 nv_error(priv
, "fuc09 req 0x30 timeout\n");
680 nv_wr32(priv
, 0x409810, 0xb00095c8);
681 nv_wr32(priv
, 0x409800, 0x00000000);
682 nv_wr32(priv
, 0x409500, 0x00000001);
683 nv_wr32(priv
, 0x409504, 0x00000031);
684 if (!nv_wait_ne(priv
, 0x409800, 0xffffffff, 0x00000000)) {
685 nv_error(priv
, "fuc09 req 0x31 timeout\n");
689 nv_wr32(priv
, 0x409810, 0x00080420);
690 nv_wr32(priv
, 0x409800, 0x00000000);
691 nv_wr32(priv
, 0x409500, 0x00000001);
692 nv_wr32(priv
, 0x409504, 0x00000032);
693 if (!nv_wait_ne(priv
, 0x409800, 0xffffffff, 0x00000000)) {
694 nv_error(priv
, "fuc09 req 0x32 timeout\n");
698 nv_wr32(priv
, 0x409614, 0x00000070);
699 nv_wr32(priv
, 0x409614, 0x00000770);
700 nv_wr32(priv
, 0x40802c, 0x00000001);
702 if (priv
->data
== NULL
) {
703 int ret
= nve0_grctx_generate(priv
);
705 nv_error(priv
, "failed to construct context\n");
713 /* load HUB microcode */
714 r000260
= nv_mask(priv
, 0x000260, 0x00000001, 0x00000000);
715 nv_wr32(priv
, 0x4091c0, 0x01000000);
716 for (i
= 0; i
< sizeof(nve0_grhub_data
) / 4; i
++)
717 nv_wr32(priv
, 0x4091c4, nve0_grhub_data
[i
]);
719 nv_wr32(priv
, 0x409180, 0x01000000);
720 for (i
= 0; i
< sizeof(nve0_grhub_code
) / 4; i
++) {
722 nv_wr32(priv
, 0x409188, i
>> 6);
723 nv_wr32(priv
, 0x409184, nve0_grhub_code
[i
]);
726 /* load GPC microcode */
727 nv_wr32(priv
, 0x41a1c0, 0x01000000);
728 for (i
= 0; i
< sizeof(nve0_grgpc_data
) / 4; i
++)
729 nv_wr32(priv
, 0x41a1c4, nve0_grgpc_data
[i
]);
731 nv_wr32(priv
, 0x41a180, 0x01000000);
732 for (i
= 0; i
< sizeof(nve0_grgpc_code
) / 4; i
++) {
734 nv_wr32(priv
, 0x41a188, i
>> 6);
735 nv_wr32(priv
, 0x41a184, nve0_grgpc_code
[i
]);
737 nv_wr32(priv
, 0x000260, r000260
);
739 /* start HUB ucode running, it'll init the GPCs */
740 nv_wr32(priv
, 0x409800, nv_device(priv
)->chipset
);
741 nv_wr32(priv
, 0x40910c, 0x00000000);
742 nv_wr32(priv
, 0x409100, 0x00000002);
743 if (!nv_wait(priv
, 0x409800, 0x80000000, 0x80000000)) {
744 nv_error(priv
, "HUB_INIT timed out\n");
745 nvc0_graph_ctxctl_debug(priv
);
749 priv
->size
= nv_rd32(priv
, 0x409804);
750 if (priv
->data
== NULL
) {
751 int ret
= nve0_grctx_generate(priv
);
753 nv_error(priv
, "failed to construct context\n");
762 nve0_graph_init(struct nouveau_object
*object
)
764 struct nvc0_graph_priv
*priv
= (void *)object
;
767 ret
= nouveau_graph_init(&priv
->base
);
771 nve0_graph_init_obj418880(priv
);
772 nve0_graph_init_regs(priv
);
773 nve0_graph_init_gpc_0(priv
);
775 nv_wr32(priv
, 0x400500, 0x00010001);
776 nv_wr32(priv
, 0x400100, 0xffffffff);
777 nv_wr32(priv
, 0x40013c, 0xffffffff);
779 nve0_graph_init_units(priv
);
780 nve0_graph_init_gpc_1(priv
);
781 nve0_graph_init_rop(priv
);
783 nv_wr32(priv
, 0x400108, 0xffffffff);
784 nv_wr32(priv
, 0x400138, 0xffffffff);
785 nv_wr32(priv
, 0x400118, 0xffffffff);
786 nv_wr32(priv
, 0x400130, 0xffffffff);
787 nv_wr32(priv
, 0x40011c, 0xffffffff);
788 nv_wr32(priv
, 0x400134, 0xffffffff);
789 nv_wr32(priv
, 0x400054, 0x34ce3464);
791 ret
= nve0_graph_init_ctxctl(priv
);
798 struct nouveau_oclass
799 nve0_graph_oclass
= {
800 .handle
= NV_ENGINE(GR
, 0xe0),
801 .ofuncs
= &(struct nouveau_ofuncs
) {
802 .ctor
= nve0_graph_ctor
,
803 .dtor
= nvc0_graph_dtor
,
804 .init
= nve0_graph_init
,
805 .fini
= _nouveau_graph_fini
,