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c80132c8f01e42d37938629ef5a6e8a9a3bb38f6
[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / engine / graph / nve0.c
1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include "nvc0.h"
26 #include "fuc/hubnve0.fuc.h"
27 #include "fuc/gpcnve0.fuc.h"
28
29 /*******************************************************************************
30 * Graphics object classes
31 ******************************************************************************/
32
33 static struct nouveau_oclass
34 nve0_graph_sclass[] = {
35 { 0x902d, &nouveau_object_ofuncs },
36 { 0xa040, &nouveau_object_ofuncs },
37 { 0xa097, &nouveau_object_ofuncs },
38 { 0xa0c0, &nouveau_object_ofuncs },
39 {}
40 };
41
42 /*******************************************************************************
43 * PGRAPH context
44 ******************************************************************************/
45
46 static struct nouveau_oclass
47 nve0_graph_cclass = {
48 .handle = NV_ENGCTX(GR, 0xe0),
49 .ofuncs = &(struct nouveau_ofuncs) {
50 .ctor = nvc0_graph_context_ctor,
51 .dtor = nvc0_graph_context_dtor,
52 .init = _nouveau_graph_context_init,
53 .fini = _nouveau_graph_context_fini,
54 .rd32 = _nouveau_graph_context_rd32,
55 .wr32 = _nouveau_graph_context_wr32,
56 },
57 };
58
59 /*******************************************************************************
60 * PGRAPH engine/subdev functions
61 ******************************************************************************/
62
63 static void
64 nve0_graph_ctxctl_isr(struct nvc0_graph_priv *priv)
65 {
66 u32 ustat = nv_rd32(priv, 0x409c18);
67
68 if (ustat & 0x00000001)
69 nv_error(priv, "CTXCTRL ucode error\n");
70 if (ustat & 0x00080000)
71 nv_error(priv, "CTXCTRL watchdog timeout\n");
72 if (ustat & ~0x00080001)
73 nv_error(priv, "CTXCTRL 0x%08x\n", ustat);
74
75 nvc0_graph_ctxctl_debug(priv);
76 nv_wr32(priv, 0x409c20, ustat);
77 }
78
79 static const struct nouveau_enum nve0_mp_warp_error[] = {
80 { 0x00, "NO_ERROR" },
81 { 0x01, "STACK_MISMATCH" },
82 { 0x05, "MISALIGNED_PC" },
83 { 0x08, "MISALIGNED_GPR" },
84 { 0x09, "INVALID_OPCODE" },
85 { 0x0d, "GPR_OUT_OF_BOUNDS" },
86 { 0x0e, "MEM_OUT_OF_BOUNDS" },
87 { 0x0f, "UNALIGNED_MEM_ACCESS" },
88 { 0x11, "INVALID_PARAM" },
89 {}
90 };
91
92 static const struct nouveau_bitfield nve0_mp_global_error[] = {
93 { 0x00000004, "MULTIPLE_WARP_ERRORS" },
94 { 0x00000008, "OUT_OF_STACK_SPACE" },
95 {}
96 };
97
98 static const struct nouveau_enum nve0_gpc_rop_error[] = {
99 { 1, "RT_PITCH_OVERRUN" },
100 { 4, "RT_WIDTH_OVERRUN" },
101 { 5, "RT_HEIGHT_OVERRUN" },
102 { 7, "ZETA_STORAGE_TYPE_MISMATCH" },
103 { 8, "RT_STORAGE_TYPE_MISMATCH" },
104 { 10, "RT_LINEAR_MISMATCH" },
105 {}
106 };
107
108 static const struct nouveau_enum nve0_sked_error[] = {
109 { 7, "CONSTANT_BUFFER_SIZE" },
110 { 9, "LOCAL_MEMORY_SIZE_POS" },
111 { 10, "LOCAL_MEMORY_SIZE_NEG" },
112 { 11, "WARP_CSTACK_SIZE" },
113 { 12, "TOTAL_TEMP_SIZE" },
114 { 13, "REGISTER_COUNT" },
115 { 18, "TOTAL_THREADS" },
116 { 20, "PROGRAM_OFFSET" },
117 { 21, "SHARED_MEMORY_SIZE" },
118 { 25, "SHARED_CONFIG_TOO_SMALL" },
119 { 26, "TOTAL_REGISTER_COUNT" },
120 {}
121 };
122
123 static void
124 nve0_graph_mp_trap(struct nvc0_graph_priv *priv, int gpc, int tpc)
125 {
126 u32 werr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x648));
127 u32 gerr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x650));
128
129 nv_error(priv, "GPC%i/TPC%i/MP trap:", gpc, tpc);
130 nouveau_bitfield_print(nve0_mp_global_error, gerr);
131 if (werr) {
132 pr_cont(" ");
133 nouveau_enum_print(nve0_mp_warp_error, werr & 0xffff);
134 }
135 pr_cont("\n");
136
137 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x648), 0x00000000);
138 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x650), gerr);
139 }
140
141 static void
142 nve0_graph_tpc_trap(struct nvc0_graph_priv *priv, int gpc, int tpc)
143 {
144 u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x508));
145
146 if (stat & 0x1) {
147 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x224));
148 nv_error(priv, "GPC%i/TPC%i/TEX trap: %08x\n",
149 gpc, tpc, trap);
150
151 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
152 stat &= ~0x1;
153 }
154
155 if (stat & 0x2) {
156 nve0_graph_mp_trap(priv, gpc, tpc);
157 stat &= ~0x2;
158 }
159
160 if (stat & 0x4) {
161 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x084));
162 nv_error(priv, "GPC%i/TPC%i/POLY trap: %08x\n",
163 gpc, tpc, trap);
164
165 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
166 stat &= ~0x4;
167 }
168
169 if (stat & 0x8) {
170 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x48c));
171 nv_error(priv, "GPC%i/TPC%i/L1C trap: %08x\n",
172 gpc, tpc, trap);
173
174 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
175 stat &= ~0x8;
176 }
177
178 if (stat) {
179 nv_error(priv, "GPC%i/TPC%i: unknown stat %08x\n",
180 gpc, tpc, stat);
181 }
182 }
183
184 static void
185 nve0_graph_gpc_trap(struct nvc0_graph_priv *priv)
186 {
187 const u32 mask = nv_rd32(priv, 0x400118);
188 int gpc;
189
190 for (gpc = 0; gpc < 4; ++gpc) {
191 u32 stat;
192 int tpc;
193
194 if (!(mask & (1 << gpc)))
195 continue;
196 stat = nv_rd32(priv, GPC_UNIT(gpc, 0x2c90));
197
198 if (stat & 0x0001) {
199 u32 trap[4];
200 int i;
201
202 trap[0] = nv_rd32(priv, GPC_UNIT(gpc, 0x0420));
203 trap[1] = nv_rd32(priv, GPC_UNIT(gpc, 0x0434));
204 trap[2] = nv_rd32(priv, GPC_UNIT(gpc, 0x0438));
205 trap[3] = nv_rd32(priv, GPC_UNIT(gpc, 0x043c));
206
207 nv_error(priv, "GPC%i/PROP trap:", gpc);
208 for (i = 0; i <= 29; ++i) {
209 if (!(trap[0] & (1 << i)))
210 continue;
211 pr_cont(" ");
212 nouveau_enum_print(nve0_gpc_rop_error, i);
213 }
214 pr_cont("\n");
215
216 nv_error(priv, "x = %u, y = %u, "
217 "format = %x, storage type = %x\n",
218 trap[1] & 0xffff,
219 trap[1] >> 16,
220 (trap[2] >> 8) & 0x3f,
221 trap[3] & 0xff);
222
223 nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
224 stat &= ~0x0001;
225 }
226
227 if (stat & 0x0002) {
228 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0900));
229 nv_error(priv, "GPC%i/ZCULL trap: %08x\n", gpc,
230 trap);
231 nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
232 stat &= ~0x0002;
233 }
234
235 if (stat & 0x0004) {
236 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x1028));
237 nv_error(priv, "GPC%i/CCACHE trap: %08x\n", gpc,
238 trap);
239 nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
240 stat &= ~0x0004;
241 }
242
243 if (stat & 0x0008) {
244 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0824));
245 nv_error(priv, "GPC%i/ESETUP trap %08x\n", gpc,
246 trap);
247 nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
248 stat &= ~0x0008;
249 }
250
251 for (tpc = 0; tpc < 8; ++tpc) {
252 if (stat & (1 << (16 + tpc)))
253 nve0_graph_tpc_trap(priv, gpc, tpc);
254 }
255 stat &= ~0xff0000;
256
257 if (stat) {
258 nv_error(priv, "GPC%i: unknown stat %08x\n",
259 gpc, stat);
260 }
261 }
262 }
263
264
265 static void
266 nve0_graph_trap_isr(struct nvc0_graph_priv *priv, int chid, u64 inst,
267 struct nouveau_object *engctx)
268 {
269 u32 trap = nv_rd32(priv, 0x400108);
270 int i;
271 int rop;
272
273 if (trap & 0x00000001) {
274 u32 stat = nv_rd32(priv, 0x404000);
275 nv_error(priv, "DISPATCH ch %d [0x%010llx %s] 0x%08x\n",
276 chid, inst, nouveau_client_name(engctx), stat);
277 nv_wr32(priv, 0x404000, 0xc0000000);
278 nv_wr32(priv, 0x400108, 0x00000001);
279 trap &= ~0x00000001;
280 }
281
282 if (trap & 0x00000010) {
283 u32 stat = nv_rd32(priv, 0x405840);
284 nv_error(priv, "SHADER ch %d [0x%010llx %s] 0x%08x\n",
285 chid, inst, nouveau_client_name(engctx), stat);
286 nv_wr32(priv, 0x405840, 0xc0000000);
287 nv_wr32(priv, 0x400108, 0x00000010);
288 trap &= ~0x00000010;
289 }
290
291 if (trap & 0x00000100) {
292 u32 stat = nv_rd32(priv, 0x407020);
293 nv_error(priv, "SKED ch %d [0x%010llx %s]:",
294 chid, inst, nouveau_client_name(engctx));
295
296 for (i = 0; i <= 29; ++i) {
297 if (!(stat & (1 << i)))
298 continue;
299 pr_cont(" ");
300 nouveau_enum_print(nve0_sked_error, i);
301 }
302 pr_cont("\n");
303
304 if (stat & 0x3fffffff)
305 nv_wr32(priv, 0x407020, 0x40000000);
306 nv_wr32(priv, 0x400108, 0x00000100);
307 trap &= ~0x00000100;
308 }
309
310 if (trap & 0x01000000) {
311 nv_error(priv, "GPC ch %d [0x%010llx %s]:\n",
312 chid, inst, nouveau_client_name(engctx));
313 nve0_graph_gpc_trap(priv);
314 trap &= ~0x01000000;
315 }
316
317 if (trap & 0x02000000) {
318 for (rop = 0; rop < priv->rop_nr; rop++) {
319 u32 statz = nv_rd32(priv, ROP_UNIT(rop, 0x070));
320 u32 statc = nv_rd32(priv, ROP_UNIT(rop, 0x144));
321 nv_error(priv,
322 "ROP%d ch %d [0x%010llx %s] 0x%08x 0x%08x\n",
323 rop, chid, inst, nouveau_client_name(engctx),
324 statz, statc);
325 nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
326 nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
327 }
328 nv_wr32(priv, 0x400108, 0x02000000);
329 trap &= ~0x02000000;
330 }
331
332 if (trap) {
333 nv_error(priv, "TRAP ch %d [0x%010llx %s] 0x%08x\n",
334 chid, inst, nouveau_client_name(engctx), trap);
335 nv_wr32(priv, 0x400108, trap);
336 }
337 }
338
339 static void
340 nve0_graph_intr(struct nouveau_subdev *subdev)
341 {
342 struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
343 struct nouveau_engine *engine = nv_engine(subdev);
344 struct nouveau_object *engctx;
345 struct nouveau_handle *handle;
346 struct nvc0_graph_priv *priv = (void *)subdev;
347 u64 inst = nv_rd32(priv, 0x409b00) & 0x0fffffff;
348 u32 stat = nv_rd32(priv, 0x400100);
349 u32 addr = nv_rd32(priv, 0x400704);
350 u32 mthd = (addr & 0x00003ffc);
351 u32 subc = (addr & 0x00070000) >> 16;
352 u32 data = nv_rd32(priv, 0x400708);
353 u32 code = nv_rd32(priv, 0x400110);
354 u32 class = nv_rd32(priv, 0x404200 + (subc * 4));
355 int chid;
356
357 engctx = nouveau_engctx_get(engine, inst);
358 chid = pfifo->chid(pfifo, engctx);
359
360 if (stat & 0x00000010) {
361 handle = nouveau_handle_get_class(engctx, class);
362 if (!handle || nv_call(handle->object, mthd, data)) {
363 nv_error(priv,
364 "ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
365 chid, inst, nouveau_client_name(engctx), subc,
366 class, mthd, data);
367 }
368 nouveau_handle_put(handle);
369 nv_wr32(priv, 0x400100, 0x00000010);
370 stat &= ~0x00000010;
371 }
372
373 if (stat & 0x00000020) {
374 nv_error(priv,
375 "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
376 chid, inst, nouveau_client_name(engctx), subc, class,
377 mthd, data);
378 nv_wr32(priv, 0x400100, 0x00000020);
379 stat &= ~0x00000020;
380 }
381
382 if (stat & 0x00100000) {
383 nv_error(priv, "DATA_ERROR [");
384 nouveau_enum_print(nv50_data_error_names, code);
385 pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
386 chid, inst, nouveau_client_name(engctx), subc, class,
387 mthd, data);
388 nv_wr32(priv, 0x400100, 0x00100000);
389 stat &= ~0x00100000;
390 }
391
392 if (stat & 0x00200000) {
393 nve0_graph_trap_isr(priv, chid, inst, engctx);
394 nv_wr32(priv, 0x400100, 0x00200000);
395 stat &= ~0x00200000;
396 }
397
398 if (stat & 0x00080000) {
399 nve0_graph_ctxctl_isr(priv);
400 nv_wr32(priv, 0x400100, 0x00080000);
401 stat &= ~0x00080000;
402 }
403
404 if (stat) {
405 nv_error(priv, "unknown stat 0x%08x\n", stat);
406 nv_wr32(priv, 0x400100, stat);
407 }
408
409 nv_wr32(priv, 0x400500, 0x00010001);
410 nouveau_engctx_put(engctx);
411 }
412
413 static int
414 nve0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
415 struct nouveau_oclass *oclass, void *data, u32 size,
416 struct nouveau_object **pobject)
417 {
418 struct nouveau_device *device = nv_device(parent);
419 struct nvc0_graph_priv *priv;
420 int ret, i;
421
422 ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
423 *pobject = nv_object(priv);
424 if (ret)
425 return ret;
426
427 nv_subdev(priv)->unit = 0x18001000;
428 nv_subdev(priv)->intr = nve0_graph_intr;
429 nv_engine(priv)->cclass = &nve0_graph_cclass;
430 nv_engine(priv)->sclass = nve0_graph_sclass;
431
432 priv->base.units = nvc0_graph_units;
433
434 if (nouveau_boolopt(device->cfgopt, "NvGrUseFW", false)) {
435 nv_info(priv, "using external firmware\n");
436 if (nvc0_graph_ctor_fw(priv, "fuc409c", &priv->fuc409c) ||
437 nvc0_graph_ctor_fw(priv, "fuc409d", &priv->fuc409d) ||
438 nvc0_graph_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) ||
439 nvc0_graph_ctor_fw(priv, "fuc41ad", &priv->fuc41ad))
440 return -EINVAL;
441 priv->firmware = true;
442 }
443
444 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
445 &priv->unk4188b4);
446 if (ret)
447 return ret;
448
449 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
450 &priv->unk4188b8);
451 if (ret)
452 return ret;
453
454 for (i = 0; i < 0x1000; i += 4) {
455 nv_wo32(priv->unk4188b4, i, 0x00000010);
456 nv_wo32(priv->unk4188b8, i, 0x00000010);
457 }
458
459 priv->gpc_nr = nv_rd32(priv, 0x409604) & 0x0000001f;
460 priv->rop_nr = (nv_rd32(priv, 0x409604) & 0x001f0000) >> 16;
461 for (i = 0; i < priv->gpc_nr; i++) {
462 priv->tpc_nr[i] = nv_rd32(priv, GPC_UNIT(i, 0x2608));
463 priv->tpc_total += priv->tpc_nr[i];
464 }
465
466 switch (nv_device(priv)->chipset) {
467 case 0xe4:
468 if (priv->tpc_total == 8)
469 priv->magic_not_rop_nr = 3;
470 else
471 if (priv->tpc_total == 7)
472 priv->magic_not_rop_nr = 1;
473 break;
474 case 0xe7:
475 case 0xe6:
476 priv->magic_not_rop_nr = 1;
477 break;
478 default:
479 break;
480 }
481
482 return 0;
483 }
484
485 static void
486 nve0_graph_init_obj418880(struct nvc0_graph_priv *priv)
487 {
488 int i;
489
490 nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000);
491 nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000);
492 for (i = 0; i < 4; i++)
493 nv_wr32(priv, GPC_BCAST(0x0888) + (i * 4), 0x00000000);
494 nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
495 nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
496 }
497
498 static void
499 nve0_graph_init_regs(struct nvc0_graph_priv *priv)
500 {
501 nv_wr32(priv, 0x400080, 0x003083c2);
502 nv_wr32(priv, 0x400088, 0x0001ffe7);
503 nv_wr32(priv, 0x40008c, 0x00000000);
504 nv_wr32(priv, 0x400090, 0x00000030);
505 nv_wr32(priv, 0x40013c, 0x003901f7);
506 nv_wr32(priv, 0x400140, 0x00000100);
507 nv_wr32(priv, 0x400144, 0x00000000);
508 nv_wr32(priv, 0x400148, 0x00000110);
509 nv_wr32(priv, 0x400138, 0x00000000);
510 nv_wr32(priv, 0x400130, 0x00000000);
511 nv_wr32(priv, 0x400134, 0x00000000);
512 nv_wr32(priv, 0x400124, 0x00000002);
513 }
514
515 static void
516 nve0_graph_init_unk40xx(struct nvc0_graph_priv *priv)
517 {
518 nv_wr32(priv, 0x40415c, 0x00000000);
519 nv_wr32(priv, 0x404170, 0x00000000);
520 }
521
522 static void
523 nve0_graph_init_unk44xx(struct nvc0_graph_priv *priv)
524 {
525 nv_wr32(priv, 0x404488, 0x00000000);
526 nv_wr32(priv, 0x40448c, 0x00000000);
527 }
528
529 static void
530 nve0_graph_init_unk78xx(struct nvc0_graph_priv *priv)
531 {
532 nv_wr32(priv, 0x407808, 0x00000000);
533 }
534
535 static void
536 nve0_graph_init_unk60xx(struct nvc0_graph_priv *priv)
537 {
538 nv_wr32(priv, 0x406024, 0x00000000);
539 }
540
541 static void
542 nve0_graph_init_unk64xx(struct nvc0_graph_priv *priv)
543 {
544 nv_wr32(priv, 0x4064f0, 0x00000000);
545 nv_wr32(priv, 0x4064f4, 0x00000000);
546 nv_wr32(priv, 0x4064f8, 0x00000000);
547 }
548
549 static void
550 nve0_graph_init_unk58xx(struct nvc0_graph_priv *priv)
551 {
552 nv_wr32(priv, 0x405844, 0x00ffffff);
553 nv_wr32(priv, 0x405850, 0x00000000);
554 nv_wr32(priv, 0x405900, 0x0000ff34);
555 nv_wr32(priv, 0x405908, 0x00000000);
556 nv_wr32(priv, 0x405928, 0x00000000);
557 nv_wr32(priv, 0x40592c, 0x00000000);
558 }
559
560 static void
561 nve0_graph_init_unk80xx(struct nvc0_graph_priv *priv)
562 {
563 nv_wr32(priv, 0x40803c, 0x00000000);
564 }
565
566 static void
567 nve0_graph_init_unk70xx(struct nvc0_graph_priv *priv)
568 {
569 nv_wr32(priv, 0x407010, 0x00000000);
570 }
571
572 static void
573 nve0_graph_init_unk5bxx(struct nvc0_graph_priv *priv)
574 {
575 nv_wr32(priv, 0x405b50, 0x00000000);
576 }
577
578 static void
579 nve0_graph_init_gpc(struct nvc0_graph_priv *priv)
580 {
581 nv_wr32(priv, 0x418408, 0x00000000);
582 nv_wr32(priv, 0x4184a0, 0x00000000);
583 nv_wr32(priv, 0x4184a4, 0x00000000);
584 nv_wr32(priv, 0x4184a8, 0x00000000);
585 nv_wr32(priv, 0x418604, 0x00000000);
586 nv_wr32(priv, 0x418680, 0x00000000);
587 nv_wr32(priv, 0x418714, 0x00000000);
588 nv_wr32(priv, 0x418384, 0x00000000);
589 nv_wr32(priv, 0x418814, 0x00000000);
590 nv_wr32(priv, 0x418818, 0x00000000);
591 nv_wr32(priv, 0x41881c, 0x00000000);
592 nv_wr32(priv, 0x418b04, 0x00000000);
593 nv_wr32(priv, 0x4188c8, 0x00000000);
594 nv_wr32(priv, 0x4188cc, 0x00000000);
595 nv_wr32(priv, 0x4188d0, 0x00010000);
596 nv_wr32(priv, 0x4188d4, 0x00000001);
597 nv_wr32(priv, 0x418910, 0x00010001);
598 nv_wr32(priv, 0x418914, 0x00000301);
599 nv_wr32(priv, 0x418918, 0x00800000);
600 nv_wr32(priv, 0x418980, 0x77777770);
601 nv_wr32(priv, 0x418984, 0x77777777);
602 nv_wr32(priv, 0x418988, 0x77777777);
603 nv_wr32(priv, 0x41898c, 0x77777777);
604 nv_wr32(priv, 0x418c04, 0x00000000);
605 nv_wr32(priv, 0x418c64, 0x00000000);
606 nv_wr32(priv, 0x418c68, 0x00000000);
607 nv_wr32(priv, 0x418c88, 0x00000000);
608 nv_wr32(priv, 0x418cb4, 0x00000000);
609 nv_wr32(priv, 0x418cb8, 0x00000000);
610 nv_wr32(priv, 0x418d00, 0x00000000);
611 nv_wr32(priv, 0x418d28, 0x00000000);
612 nv_wr32(priv, 0x418d2c, 0x00000000);
613 nv_wr32(priv, 0x418f00, 0x00000000);
614 nv_wr32(priv, 0x418f08, 0x00000000);
615 nv_wr32(priv, 0x418f20, 0x00000000);
616 nv_wr32(priv, 0x418f24, 0x00000000);
617 nv_wr32(priv, 0x418e00, 0x00000060);
618 nv_wr32(priv, 0x418e08, 0x00000000);
619 nv_wr32(priv, 0x418e1c, 0x00000000);
620 nv_wr32(priv, 0x418e20, 0x00000000);
621 nv_wr32(priv, 0x41900c, 0x00000000);
622 nv_wr32(priv, 0x419018, 0x00000000);
623 }
624
625 static void
626 nve0_graph_init_tpc(struct nvc0_graph_priv *priv)
627 {
628 nv_wr32(priv, 0x419d0c, 0x00000000);
629 nv_wr32(priv, 0x419d10, 0x00000014);
630 nv_wr32(priv, 0x419ab0, 0x00000000);
631 nv_wr32(priv, 0x419ac8, 0x00000000);
632 nv_wr32(priv, 0x419ab8, 0x000000e7);
633 nv_wr32(priv, 0x419abc, 0x00000000);
634 nv_wr32(priv, 0x419ac0, 0x00000000);
635 nv_wr32(priv, 0x419ab4, 0x00000000);
636 nv_wr32(priv, 0x41980c, 0x00000010);
637 nv_wr32(priv, 0x419844, 0x00000000);
638 nv_wr32(priv, 0x419850, 0x00000004);
639 nv_wr32(priv, 0x419854, 0x00000000);
640 nv_wr32(priv, 0x419858, 0x00000000);
641 nv_wr32(priv, 0x419c98, 0x00000000);
642 nv_wr32(priv, 0x419ca8, 0x00000000);
643 nv_wr32(priv, 0x419cb0, 0x01000000);
644 nv_wr32(priv, 0x419cb4, 0x00000000);
645 nv_wr32(priv, 0x419cb8, 0x00b08bea);
646 nv_wr32(priv, 0x419c84, 0x00010384);
647 nv_wr32(priv, 0x419cbc, 0x28137646);
648 nv_wr32(priv, 0x419cc0, 0x00000000);
649 nv_wr32(priv, 0x419cc4, 0x00000000);
650 nv_wr32(priv, 0x419c80, 0x00020232);
651 nv_wr32(priv, 0x419c0c, 0x00000000);
652 nv_wr32(priv, 0x419e00, 0x00000000);
653 nv_wr32(priv, 0x419ea0, 0x00000000);
654 nv_wr32(priv, 0x419ee4, 0x00000000);
655 nv_wr32(priv, 0x419ea4, 0x00000100);
656 nv_wr32(priv, 0x419ea8, 0x00000000);
657 nv_wr32(priv, 0x419eb4, 0x00000000);
658 nv_wr32(priv, 0x419eb8, 0x00000000);
659 nv_wr32(priv, 0x419ebc, 0x00000000);
660 nv_wr32(priv, 0x419ec0, 0x00000000);
661 nv_wr32(priv, 0x419edc, 0x00000000);
662 nv_wr32(priv, 0x419f00, 0x00000000);
663 nv_wr32(priv, 0x419f74, 0x00000555);
664 }
665
666 static void
667 nve0_graph_init_tpcunk(struct nvc0_graph_priv *priv)
668 {
669 nv_wr32(priv, 0x41be04, 0x00000000);
670 nv_wr32(priv, 0x41be08, 0x00000004);
671 nv_wr32(priv, 0x41be0c, 0x00000000);
672 nv_wr32(priv, 0x41be10, 0x003b8bc7);
673 nv_wr32(priv, 0x41be14, 0x00000000);
674 nv_wr32(priv, 0x41be18, 0x00000000);
675 nv_wr32(priv, 0x41bfd4, 0x00800000);
676 nv_wr32(priv, 0x41bfdc, 0x00000000);
677 nv_wr32(priv, 0x41bff8, 0x00000000);
678 nv_wr32(priv, 0x41bffc, 0x00000000);
679 nv_wr32(priv, 0x41becc, 0x00000000);
680 nv_wr32(priv, 0x41bee8, 0x00000000);
681 nv_wr32(priv, 0x41beec, 0x00000000);
682 }
683
684 static void
685 nve0_graph_init_unk88xx(struct nvc0_graph_priv *priv)
686 {
687 nv_wr32(priv, 0x40880c, 0x00000000);
688 nv_wr32(priv, 0x408850, 0x00000004);
689 nv_wr32(priv, 0x408910, 0x00000000);
690 nv_wr32(priv, 0x408914, 0x00000000);
691 nv_wr32(priv, 0x408918, 0x00000000);
692 nv_wr32(priv, 0x40891c, 0x00000000);
693 nv_wr32(priv, 0x408920, 0x00000000);
694 nv_wr32(priv, 0x408924, 0x00000000);
695 nv_wr32(priv, 0x408928, 0x00000000);
696 nv_wr32(priv, 0x40892c, 0x00000000);
697 nv_wr32(priv, 0x408930, 0x00000000);
698 nv_wr32(priv, 0x408950, 0x00000000);
699 nv_wr32(priv, 0x408954, 0x0000ffff);
700 nv_wr32(priv, 0x408958, 0x00000034);
701 nv_wr32(priv, 0x408984, 0x00000000);
702 nv_wr32(priv, 0x408988, 0x08040201);
703 nv_wr32(priv, 0x40898c, 0x80402010);
704 }
705
706 static void
707 nve0_graph_init_units(struct nvc0_graph_priv *priv)
708 {
709 nv_wr32(priv, 0x409ffc, 0x00000000);
710 nv_wr32(priv, 0x409c14, 0x00003e3e);
711 switch (nv_device(priv)->chipset) {
712 case 0xe7:
713 case 0xe6:
714 nv_wr32(priv, 0x409c24, 0x000f0001);
715 break;
716 default:
717 nv_wr32(priv, 0x409c24, 0x000f0000);
718 break;
719 }
720
721 nv_wr32(priv, 0x404000, 0xc0000000);
722 nv_wr32(priv, 0x404600, 0xc0000000);
723 nv_wr32(priv, 0x408030, 0xc0000000);
724 nv_wr32(priv, 0x404490, 0xc0000000);
725 nv_wr32(priv, 0x406018, 0xc0000000);
726 switch (nv_device(priv)->chipset) {
727 case 0xe7:
728 case 0xe6:
729 nv_wr32(priv, 0x407020, 0x40000000);
730 break;
731 default:
732 nv_wr32(priv, 0x407020, 0xc0000000);
733 break;
734 }
735 nv_wr32(priv, 0x405840, 0xc0000000);
736 nv_wr32(priv, 0x405844, 0x00ffffff);
737
738 nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008);
739 nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000);
740
741 }
742
743 static void
744 nve0_graph_init_gpc_0(struct nvc0_graph_priv *priv)
745 {
746 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
747 u32 data[TPC_MAX / 8];
748 u8 tpcnr[GPC_MAX];
749 int i, gpc, tpc;
750
751 nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001);
752
753 memset(data, 0x00, sizeof(data));
754 memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
755 for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
756 do {
757 gpc = (gpc + 1) % priv->gpc_nr;
758 } while (!tpcnr[gpc]);
759 tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
760
761 data[i / 8] |= tpc << ((i % 8) * 4);
762 }
763
764 nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
765 nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
766 nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
767 nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
768
769 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
770 nv_wr32(priv, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 |
771 priv->tpc_nr[gpc]);
772 nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tpc_total);
773 nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
774 }
775
776 nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
777 nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
778 }
779
780 static void
781 nve0_graph_init_gpc_1(struct nvc0_graph_priv *priv)
782 {
783 int gpc, tpc;
784
785 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
786 nv_wr32(priv, GPC_UNIT(gpc, 0x3038), 0xc0000000);
787 nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
788 nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
789 nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
790 nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
791 for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
792 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
793 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
794 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
795 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
796 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
797 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
798 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
799 }
800 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
801 nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
802 }
803 }
804
805 static void
806 nve0_graph_init_rop(struct nvc0_graph_priv *priv)
807 {
808 int rop;
809
810 for (rop = 0; rop < priv->rop_nr; rop++) {
811 nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
812 nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
813 nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff);
814 nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff);
815 }
816 }
817
818 static int
819 nve0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
820 {
821 u32 r000260;
822 int i;
823
824 if (priv->firmware) {
825 /* load fuc microcode */
826 r000260 = nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
827 nvc0_graph_init_fw(priv, 0x409000, &priv->fuc409c, &priv->fuc409d);
828 nvc0_graph_init_fw(priv, 0x41a000, &priv->fuc41ac, &priv->fuc41ad);
829 nv_wr32(priv, 0x000260, r000260);
830
831 /* start both of them running */
832 nv_wr32(priv, 0x409840, 0xffffffff);
833 nv_wr32(priv, 0x41a10c, 0x00000000);
834 nv_wr32(priv, 0x40910c, 0x00000000);
835 nv_wr32(priv, 0x41a100, 0x00000002);
836 nv_wr32(priv, 0x409100, 0x00000002);
837 if (!nv_wait(priv, 0x409800, 0x00000001, 0x00000001))
838 nv_error(priv, "0x409800 wait failed\n");
839
840 nv_wr32(priv, 0x409840, 0xffffffff);
841 nv_wr32(priv, 0x409500, 0x7fffffff);
842 nv_wr32(priv, 0x409504, 0x00000021);
843
844 nv_wr32(priv, 0x409840, 0xffffffff);
845 nv_wr32(priv, 0x409500, 0x00000000);
846 nv_wr32(priv, 0x409504, 0x00000010);
847 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
848 nv_error(priv, "fuc09 req 0x10 timeout\n");
849 return -EBUSY;
850 }
851 priv->size = nv_rd32(priv, 0x409800);
852
853 nv_wr32(priv, 0x409840, 0xffffffff);
854 nv_wr32(priv, 0x409500, 0x00000000);
855 nv_wr32(priv, 0x409504, 0x00000016);
856 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
857 nv_error(priv, "fuc09 req 0x16 timeout\n");
858 return -EBUSY;
859 }
860
861 nv_wr32(priv, 0x409840, 0xffffffff);
862 nv_wr32(priv, 0x409500, 0x00000000);
863 nv_wr32(priv, 0x409504, 0x00000025);
864 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
865 nv_error(priv, "fuc09 req 0x25 timeout\n");
866 return -EBUSY;
867 }
868
869 nv_wr32(priv, 0x409800, 0x00000000);
870 nv_wr32(priv, 0x409500, 0x00000001);
871 nv_wr32(priv, 0x409504, 0x00000030);
872 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
873 nv_error(priv, "fuc09 req 0x30 timeout\n");
874 return -EBUSY;
875 }
876
877 nv_wr32(priv, 0x409810, 0xb00095c8);
878 nv_wr32(priv, 0x409800, 0x00000000);
879 nv_wr32(priv, 0x409500, 0x00000001);
880 nv_wr32(priv, 0x409504, 0x00000031);
881 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
882 nv_error(priv, "fuc09 req 0x31 timeout\n");
883 return -EBUSY;
884 }
885
886 nv_wr32(priv, 0x409810, 0x00080420);
887 nv_wr32(priv, 0x409800, 0x00000000);
888 nv_wr32(priv, 0x409500, 0x00000001);
889 nv_wr32(priv, 0x409504, 0x00000032);
890 if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
891 nv_error(priv, "fuc09 req 0x32 timeout\n");
892 return -EBUSY;
893 }
894
895 nv_wr32(priv, 0x409614, 0x00000070);
896 nv_wr32(priv, 0x409614, 0x00000770);
897 nv_wr32(priv, 0x40802c, 0x00000001);
898
899 if (priv->data == NULL) {
900 int ret = nve0_grctx_generate(priv);
901 if (ret) {
902 nv_error(priv, "failed to construct context\n");
903 return ret;
904 }
905 }
906
907 return 0;
908 }
909
910 /* load HUB microcode */
911 r000260 = nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
912 nv_wr32(priv, 0x4091c0, 0x01000000);
913 for (i = 0; i < sizeof(nve0_grhub_data) / 4; i++)
914 nv_wr32(priv, 0x4091c4, nve0_grhub_data[i]);
915
916 nv_wr32(priv, 0x409180, 0x01000000);
917 for (i = 0; i < sizeof(nve0_grhub_code) / 4; i++) {
918 if ((i & 0x3f) == 0)
919 nv_wr32(priv, 0x409188, i >> 6);
920 nv_wr32(priv, 0x409184, nve0_grhub_code[i]);
921 }
922
923 /* load GPC microcode */
924 nv_wr32(priv, 0x41a1c0, 0x01000000);
925 for (i = 0; i < sizeof(nve0_grgpc_data) / 4; i++)
926 nv_wr32(priv, 0x41a1c4, nve0_grgpc_data[i]);
927
928 nv_wr32(priv, 0x41a180, 0x01000000);
929 for (i = 0; i < sizeof(nve0_grgpc_code) / 4; i++) {
930 if ((i & 0x3f) == 0)
931 nv_wr32(priv, 0x41a188, i >> 6);
932 nv_wr32(priv, 0x41a184, nve0_grgpc_code[i]);
933 }
934 nv_wr32(priv, 0x000260, r000260);
935
936 /* start HUB ucode running, it'll init the GPCs */
937 nv_wr32(priv, 0x409800, nv_device(priv)->chipset);
938 nv_wr32(priv, 0x40910c, 0x00000000);
939 nv_wr32(priv, 0x409100, 0x00000002);
940 if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) {
941 nv_error(priv, "HUB_INIT timed out\n");
942 nvc0_graph_ctxctl_debug(priv);
943 return -EBUSY;
944 }
945
946 priv->size = nv_rd32(priv, 0x409804);
947 if (priv->data == NULL) {
948 int ret = nve0_grctx_generate(priv);
949 if (ret) {
950 nv_error(priv, "failed to construct context\n");
951 return ret;
952 }
953 }
954
955 return 0;
956 }
957
958 static int
959 nve0_graph_init(struct nouveau_object *object)
960 {
961 struct nvc0_graph_priv *priv = (void *)object;
962 int ret;
963
964 ret = nouveau_graph_init(&priv->base);
965 if (ret)
966 return ret;
967
968 nve0_graph_init_obj418880(priv);
969 nve0_graph_init_regs(priv);
970
971 switch (nv_device(priv)->chipset) {
972 case 0xe7:
973 case 0xe6:
974 nve0_graph_init_unk40xx(priv);
975 nve0_graph_init_unk44xx(priv);
976 nve0_graph_init_unk78xx(priv);
977 nve0_graph_init_unk60xx(priv);
978 nve0_graph_init_unk64xx(priv);
979 nve0_graph_init_unk58xx(priv);
980 nve0_graph_init_unk80xx(priv);
981 nve0_graph_init_unk70xx(priv);
982 nve0_graph_init_unk5bxx(priv);
983 nve0_graph_init_gpc(priv);
984 nve0_graph_init_tpc(priv);
985 nve0_graph_init_tpcunk(priv);
986 nve0_graph_init_unk88xx(priv);
987 break;
988 default:
989 break;
990 }
991
992 nve0_graph_init_gpc_0(priv);
993
994 nv_wr32(priv, 0x400500, 0x00010001);
995 nv_wr32(priv, 0x400100, 0xffffffff);
996 nv_wr32(priv, 0x40013c, 0xffffffff);
997
998 nve0_graph_init_units(priv);
999 nve0_graph_init_gpc_1(priv);
1000 nve0_graph_init_rop(priv);
1001
1002 nv_wr32(priv, 0x400108, 0xffffffff);
1003 nv_wr32(priv, 0x400138, 0xffffffff);
1004 nv_wr32(priv, 0x400118, 0xffffffff);
1005 nv_wr32(priv, 0x400130, 0xffffffff);
1006 nv_wr32(priv, 0x40011c, 0xffffffff);
1007 nv_wr32(priv, 0x400134, 0xffffffff);
1008 nv_wr32(priv, 0x400054, 0x34ce3464);
1009
1010 ret = nve0_graph_init_ctxctl(priv);
1011 if (ret)
1012 return ret;
1013
1014 return 0;
1015 }
1016
1017 struct nouveau_oclass
1018 nve0_graph_oclass = {
1019 .handle = NV_ENGINE(GR, 0xe0),
1020 .ofuncs = &(struct nouveau_ofuncs) {
1021 .ctor = nve0_graph_ctor,
1022 .dtor = nvc0_graph_dtor,
1023 .init = nve0_graph_init,
1024 .fini = _nouveau_graph_fini,
1025 },
1026 };
Linux kernel - Deliverables
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