drm/nvc0-/gr: make register lists from initvals functions
[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / engine / graph / nve4.c
1 /*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24
25 #include "nvc0.h"
26
27 /*******************************************************************************
28 * Graphics object classes
29 ******************************************************************************/
30
31 static struct nouveau_oclass
32 nve4_graph_sclass[] = {
33 { 0x902d, &nouveau_object_ofuncs },
34 { 0xa040, &nouveau_object_ofuncs },
35 { 0xa097, &nouveau_object_ofuncs },
36 { 0xa0c0, &nouveau_object_ofuncs },
37 {}
38 };
39
40 /*******************************************************************************
41 * PGRAPH engine/subdev functions
42 ******************************************************************************/
43
44 struct nvc0_graph_init
45 nve4_graph_init_regs[] = {
46 { 0x400080, 1, 0x04, 0x003083c2 },
47 { 0x400088, 1, 0x04, 0x0001ffe7 },
48 { 0x40008c, 1, 0x04, 0x00000000 },
49 { 0x400090, 1, 0x04, 0x00000030 },
50 { 0x40013c, 1, 0x04, 0x003901f7 },
51 { 0x400140, 1, 0x04, 0x00000100 },
52 { 0x400144, 1, 0x04, 0x00000000 },
53 { 0x400148, 1, 0x04, 0x00000110 },
54 { 0x400138, 1, 0x04, 0x00000000 },
55 { 0x400130, 2, 0x04, 0x00000000 },
56 { 0x400124, 1, 0x04, 0x00000002 },
57 {}
58 };
59
60 static struct nvc0_graph_init
61 nve4_graph_init_unk58xx[] = {
62 { 0x405844, 1, 0x04, 0x00ffffff },
63 { 0x405850, 1, 0x04, 0x00000000 },
64 { 0x405900, 1, 0x04, 0x0000ff34 },
65 { 0x405908, 1, 0x04, 0x00000000 },
66 { 0x405928, 1, 0x04, 0x00000000 },
67 { 0x40592c, 1, 0x04, 0x00000000 },
68 {}
69 };
70
71 static struct nvc0_graph_init
72 nve4_graph_init_unk70xx[] = {
73 { 0x407010, 1, 0x04, 0x00000000 },
74 {}
75 };
76
77 struct nvc0_graph_init
78 nve4_graph_init_unk5bxx[] = {
79 { 0x405b50, 1, 0x04, 0x00000000 },
80 {}
81 };
82
83 static struct nvc0_graph_init
84 nve4_graph_init_gpc[] = {
85 { 0x418408, 1, 0x04, 0x00000000 },
86 { 0x4184a0, 1, 0x04, 0x00000000 },
87 { 0x4184a4, 2, 0x04, 0x00000000 },
88 { 0x418604, 1, 0x04, 0x00000000 },
89 { 0x418680, 1, 0x04, 0x00000000 },
90 { 0x418714, 1, 0x04, 0x00000000 },
91 { 0x418384, 1, 0x04, 0x00000000 },
92 { 0x418814, 3, 0x04, 0x00000000 },
93 { 0x418b04, 1, 0x04, 0x00000000 },
94 { 0x4188c8, 2, 0x04, 0x00000000 },
95 { 0x4188d0, 1, 0x04, 0x00010000 },
96 { 0x4188d4, 1, 0x04, 0x00000001 },
97 { 0x418910, 1, 0x04, 0x00010001 },
98 { 0x418914, 1, 0x04, 0x00000301 },
99 { 0x418918, 1, 0x04, 0x00800000 },
100 { 0x418980, 1, 0x04, 0x77777770 },
101 { 0x418984, 3, 0x04, 0x77777777 },
102 { 0x418c04, 1, 0x04, 0x00000000 },
103 { 0x418c64, 1, 0x04, 0x00000000 },
104 { 0x418c68, 1, 0x04, 0x00000000 },
105 { 0x418c88, 1, 0x04, 0x00000000 },
106 { 0x418cb4, 2, 0x04, 0x00000000 },
107 { 0x418d00, 1, 0x04, 0x00000000 },
108 { 0x418d28, 1, 0x04, 0x00000000 },
109 { 0x418d2c, 1, 0x04, 0x00000000 },
110 { 0x418f00, 1, 0x04, 0x00000000 },
111 { 0x418f08, 1, 0x04, 0x00000000 },
112 { 0x418f20, 2, 0x04, 0x00000000 },
113 { 0x418e00, 1, 0x04, 0x00000060 },
114 { 0x418e08, 1, 0x04, 0x00000000 },
115 { 0x418e1c, 1, 0x04, 0x00000000 },
116 { 0x418e20, 1, 0x04, 0x00000000 },
117 { 0x41900c, 1, 0x04, 0x00000000 },
118 { 0x419018, 1, 0x04, 0x00000000 },
119 {}
120 };
121
122 static struct nvc0_graph_init
123 nve4_graph_init_tpc[] = {
124 { 0x419d0c, 1, 0x04, 0x00000000 },
125 { 0x419d10, 1, 0x04, 0x00000014 },
126 { 0x419ab0, 1, 0x04, 0x00000000 },
127 { 0x419ac8, 1, 0x04, 0x00000000 },
128 { 0x419ab8, 1, 0x04, 0x000000e7 },
129 { 0x419abc, 2, 0x04, 0x00000000 },
130 { 0x419ab4, 1, 0x04, 0x00000000 },
131 { 0x41980c, 1, 0x04, 0x00000010 },
132 { 0x419844, 1, 0x04, 0x00000000 },
133 { 0x419850, 1, 0x04, 0x00000004 },
134 { 0x419854, 2, 0x04, 0x00000000 },
135 { 0x419c98, 1, 0x04, 0x00000000 },
136 { 0x419ca8, 1, 0x04, 0x00000000 },
137 { 0x419cb0, 1, 0x04, 0x01000000 },
138 { 0x419cb4, 1, 0x04, 0x00000000 },
139 { 0x419cb8, 1, 0x04, 0x00b08bea },
140 { 0x419c84, 1, 0x04, 0x00010384 },
141 { 0x419cbc, 1, 0x04, 0x28137646 },
142 { 0x419cc0, 2, 0x04, 0x00000000 },
143 { 0x419c80, 1, 0x04, 0x00020232 },
144 { 0x419c0c, 1, 0x04, 0x00000000 },
145 { 0x419e00, 1, 0x04, 0x00000000 },
146 { 0x419ea0, 1, 0x04, 0x00000000 },
147 { 0x419ee4, 1, 0x04, 0x00000000 },
148 { 0x419ea4, 1, 0x04, 0x00000100 },
149 { 0x419ea8, 1, 0x04, 0x00000000 },
150 { 0x419eb4, 1, 0x04, 0x00000000 },
151 { 0x419eb8, 3, 0x04, 0x00000000 },
152 { 0x419edc, 1, 0x04, 0x00000000 },
153 { 0x419f00, 1, 0x04, 0x00000000 },
154 { 0x419f74, 1, 0x04, 0x00000555 },
155 {}
156 };
157
158 struct nvc0_graph_init
159 nve4_graph_init_unk[] = {
160 { 0x41be04, 1, 0x04, 0x00000000 },
161 { 0x41be08, 1, 0x04, 0x00000004 },
162 { 0x41be0c, 1, 0x04, 0x00000000 },
163 { 0x41be10, 1, 0x04, 0x003b8bc7 },
164 { 0x41be14, 2, 0x04, 0x00000000 },
165 { 0x41bfd4, 1, 0x04, 0x00800000 },
166 { 0x41bfdc, 1, 0x04, 0x00000000 },
167 { 0x41bff8, 1, 0x04, 0x00000000 },
168 { 0x41bffc, 1, 0x04, 0x00000000 },
169 { 0x41becc, 1, 0x04, 0x00000000 },
170 { 0x41bee8, 1, 0x04, 0x00000000 },
171 { 0x41beec, 1, 0x04, 0x00000000 },
172 {}
173 };
174
175 struct nvc0_graph_init
176 nve4_graph_init_unk88xx[] = {
177 { 0x40880c, 1, 0x04, 0x00000000 },
178 { 0x408850, 1, 0x04, 0x00000004 },
179 { 0x408910, 9, 0x04, 0x00000000 },
180 { 0x408950, 1, 0x04, 0x00000000 },
181 { 0x408954, 1, 0x04, 0x0000ffff },
182 { 0x408958, 1, 0x04, 0x00000034 },
183 { 0x408984, 1, 0x04, 0x00000000 },
184 { 0x408988, 1, 0x04, 0x08040201 },
185 { 0x40898c, 1, 0x04, 0x80402010 },
186 {}
187 };
188
189 int
190 nve4_graph_init(struct nouveau_object *object)
191 {
192 struct nvc0_graph_oclass *oclass = (void *)object->oclass;
193 struct nvc0_graph_priv *priv = (void *)object;
194 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
195 u32 data[TPC_MAX / 8] = {};
196 u8 tpcnr[GPC_MAX];
197 int gpc, tpc, rop;
198 int ret, i;
199
200 ret = nouveau_graph_init(&priv->base);
201 if (ret)
202 return ret;
203
204 nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000);
205 nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000);
206 nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000);
207 nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000);
208 nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000);
209 nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000);
210 nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
211 nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
212
213 for (i = 0; oclass->mmio[i]; i++)
214 nvc0_graph_mmio(priv, oclass->mmio[i]);
215
216 nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001);
217
218 memset(data, 0x00, sizeof(data));
219 memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
220 for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
221 do {
222 gpc = (gpc + 1) % priv->gpc_nr;
223 } while (!tpcnr[gpc]);
224 tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
225
226 data[i / 8] |= tpc << ((i % 8) * 4);
227 }
228
229 nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
230 nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
231 nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
232 nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
233
234 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
235 nv_wr32(priv, GPC_UNIT(gpc, 0x0914),
236 priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]);
237 nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 |
238 priv->tpc_total);
239 nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
240 }
241
242 nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
243 nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
244
245 nv_wr32(priv, 0x400500, 0x00010001);
246
247 nv_wr32(priv, 0x400100, 0xffffffff);
248 nv_wr32(priv, 0x40013c, 0xffffffff);
249
250 nv_wr32(priv, 0x409ffc, 0x00000000);
251 nv_wr32(priv, 0x409c14, 0x00003e3e);
252 nv_wr32(priv, 0x409c24, 0x000f0001);
253 nv_wr32(priv, 0x404000, 0xc0000000);
254 nv_wr32(priv, 0x404600, 0xc0000000);
255 nv_wr32(priv, 0x408030, 0xc0000000);
256 nv_wr32(priv, 0x404490, 0xc0000000);
257 nv_wr32(priv, 0x406018, 0xc0000000);
258 nv_wr32(priv, 0x407020, 0x40000000);
259 nv_wr32(priv, 0x405840, 0xc0000000);
260 nv_wr32(priv, 0x405844, 0x00ffffff);
261 nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008);
262 nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000);
263
264 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
265 nv_wr32(priv, GPC_UNIT(gpc, 0x3038), 0xc0000000);
266 nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
267 nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
268 nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
269 nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
270 for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
271 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
272 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
273 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
274 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
275 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
276 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
277 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
278 }
279 nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
280 nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
281 }
282
283 for (rop = 0; rop < priv->rop_nr; rop++) {
284 nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
285 nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
286 nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff);
287 nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff);
288 }
289
290 nv_wr32(priv, 0x400108, 0xffffffff);
291 nv_wr32(priv, 0x400138, 0xffffffff);
292 nv_wr32(priv, 0x400118, 0xffffffff);
293 nv_wr32(priv, 0x400130, 0xffffffff);
294 nv_wr32(priv, 0x40011c, 0xffffffff);
295 nv_wr32(priv, 0x400134, 0xffffffff);
296
297 nv_wr32(priv, 0x400054, 0x34ce3464);
298 return nvc0_graph_init_ctxctl(priv);
299 }
300
301 static struct nvc0_graph_init *
302 nve4_graph_init_mmio[] = {
303 nve4_graph_init_regs,
304 nvc0_graph_init_unk40xx,
305 nvc0_graph_init_unk44xx,
306 nvc0_graph_init_unk78xx,
307 nvc0_graph_init_unk60xx,
308 nvd9_graph_init_unk64xx,
309 nve4_graph_init_unk58xx,
310 nvc0_graph_init_unk80xx,
311 nve4_graph_init_unk70xx,
312 nve4_graph_init_unk5bxx,
313 nve4_graph_init_gpc,
314 nve4_graph_init_tpc,
315 nve4_graph_init_unk,
316 nve4_graph_init_unk88xx,
317 NULL
318 };
319
320 #include "fuc/hubnve0.fuc.h"
321
322 static struct nvc0_graph_ucode
323 nve4_graph_fecs_ucode = {
324 .code.data = nve0_grhub_code,
325 .code.size = sizeof(nve0_grhub_code),
326 .data.data = nve0_grhub_data,
327 .data.size = sizeof(nve0_grhub_data),
328 };
329
330 #include "fuc/gpcnve0.fuc.h"
331
332 static struct nvc0_graph_ucode
333 nve4_graph_gpccs_ucode = {
334 .code.data = nve0_grgpc_code,
335 .code.size = sizeof(nve0_grgpc_code),
336 .data.data = nve0_grgpc_data,
337 .data.size = sizeof(nve0_grgpc_data),
338 };
339
340 struct nouveau_oclass *
341 nve4_graph_oclass = &(struct nvc0_graph_oclass) {
342 .base.handle = NV_ENGINE(GR, 0xe4),
343 .base.ofuncs = &(struct nouveau_ofuncs) {
344 .ctor = nvc0_graph_ctor,
345 .dtor = nvc0_graph_dtor,
346 .init = nve4_graph_init,
347 .fini = _nouveau_graph_fini,
348 },
349 .cclass = &nve4_grctx_oclass,
350 .sclass = nve4_graph_sclass,
351 .mmio = nve4_graph_init_mmio,
352 .fecs.ucode = &nve4_graph_fecs_ucode,
353 .gpccs.ucode = &nve4_graph_gpccs_ucode,
354 }.base;
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