drivers/gpu/drm/nouveau/core/include/core/class.h

   1 #ifndef __NOUVEAU_CLASS_H__
   2 #define __NOUVEAU_CLASS_H__
   3
   4 /* 0080: NV_DEVICE
   5  */
   6
   7 #define NV_DEVICE_DISABLE_IDENTIFY                        0x0000000000000001ULL
   8 #define NV_DEVICE_DISABLE_MMIO                            0x0000000000000002ULL
   9 #define NV_DEVICE_DISABLE_VBIOS                           0x0000000000000004ULL
  10 #define NV_DEVICE_DISABLE_CORE                            0x0000000000000008ULL
  11 #define NV_DEVICE_DISABLE_DISP                            0x0000000000010000ULL
  12 #define NV_DEVICE_DISABLE_FIFO                            0x0000000000020000ULL
  13 #define NV_DEVICE_DISABLE_GRAPH                           0x0000000100000000ULL
  14 #define NV_DEVICE_DISABLE_MPEG                            0x0000000200000000ULL
  15 #define NV_DEVICE_DISABLE_ME                              0x0000000400000000ULL
  16 #define NV_DEVICE_DISABLE_VP                              0x0000000800000000ULL
  17 #define NV_DEVICE_DISABLE_CRYPT                           0x0000001000000000ULL
  18 #define NV_DEVICE_DISABLE_BSP                             0x0000002000000000ULL
  19 #define NV_DEVICE_DISABLE_PPP                             0x0000004000000000ULL
  20 #define NV_DEVICE_DISABLE_COPY0                           0x0000008000000000ULL
  21 #define NV_DEVICE_DISABLE_COPY1                           0x0000010000000000ULL
  22 #define NV_DEVICE_DISABLE_UNK1C1                          0x0000020000000000ULL
  23
  24 struct nv_device_class {
  25         u64 device;     /* device identifier, ~0 for client default */
  26         u64 disable;    /* disable particular subsystems */
  27         u64 debug0;     /* as above, but *internal* ids, and *NOT* ABI */
  28 };
  29
  30 /* 0002: NV_DMA_FROM_MEMORY
  31  * 0003: NV_DMA_TO_MEMORY
  32  * 003d: NV_DMA_IN_MEMORY
  33  */
  34
  35 #define NV_DMA_TARGET_MASK                                           0x000000ff
  36 #define NV_DMA_TARGET_VM                                             0x00000000
  37 #define NV_DMA_TARGET_VRAM                                           0x00000001
  38 #define NV_DMA_TARGET_PCI                                            0x00000002
  39 #define NV_DMA_TARGET_PCI_US                                         0x00000003
  40 #define NV_DMA_TARGET_AGP                                            0x00000004
  41 #define NV_DMA_ACCESS_MASK                                           0x00000f00
  42 #define NV_DMA_ACCESS_VM                                             0x00000000
  43 #define NV_DMA_ACCESS_RD                                             0x00000100
  44 #define NV_DMA_ACCESS_WR                                             0x00000200
  45 #define NV_DMA_ACCESS_RDWR                                           0x00000300
  46
  47 struct nv_dma_class {
  48         u32 flags;
  49         u32 pad0;
  50         u64 start;
  51         u64 limit;
  52 };
  53
  54 /* 006b: NV03_CHANNEL_DMA
  55  * 006e: NV10_CHANNEL_DMA
  56  * 176e: NV17_CHANNEL_DMA
  57  * 406e: NV40_CHANNEL_DMA
  58  * 506e: NV50_CHANNEL_DMA
  59  * 826e: NV84_CHANNEL_DMA
  60  */
  61
  62 struct nv03_channel_dma_class {
  63         u32 pushbuf;
  64         u32 pad0;
  65         u64 offset;
  66 };
  67
  68 /* 506f: NV50_CHANNEL_IND
  69  * 826f: NV84_CHANNEL_IND
  70  * 906f: NVC0_CHANNEL_IND
  71  */
  72
  73 struct nv50_channel_ind_class {
  74         u32 pushbuf;
  75         u32 ilength;
  76         u64 ioffset;
  77 };
  78
  79 /* a06f: NVE0_CHANNEL_IND
  80  */
  81
  82 #define NVE0_CHANNEL_IND_ENGINE_GR  0x00000001
  83 #define NVE0_CHANNEL_IND_ENGINE_VP  0x00000002
  84 #define NVE0_CHANNEL_IND_ENGINE_PPP 0x00000004
  85 #define NVE0_CHANNEL_IND_ENGINE_BSP 0x00000008
  86 #define NVE0_CHANNEL_IND_ENGINE_CE0 0x00000010
  87 #define NVE0_CHANNEL_IND_ENGINE_CE1 0x00000020
  88 #define NVE0_CHANNEL_IND_ENGINE_ENC 0x00000040
  89
  90 struct nve0_channel_ind_class {
  91         u32 pushbuf;
  92         u32 ilength;
  93         u64 ioffset;
  94         u32 engine;
  95 };
  96
  97 #endif