1 #include <core/engine.h>
2 #include <core/device.h>
4 #include <subdev/bios.h>
5 #include <subdev/bios/bmp.h>
6 #include <subdev/bios/bit.h>
7 #include <subdev/bios/conn.h>
8 #include <subdev/bios/dcb.h>
9 #include <subdev/bios/dp.h>
10 #include <subdev/bios/gpio.h>
11 #include <subdev/bios/init.h>
12 #include <subdev/devinit.h>
13 #include <subdev/i2c.h>
14 #include <subdev/vga.h>
15 #include <subdev/gpio.h>
17 #define bioslog(lvl, fmt, args...) do { \
18 nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \
19 init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args); \
21 #define cont(fmt, args...) do { \
22 if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE) \
23 printk(fmt, ##args); \
25 #define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
26 #define warn(fmt, args...) bioslog(WARN, fmt, ##args)
27 #define error(fmt, args...) bioslog(ERROR, fmt, ##args)
29 /******************************************************************************
30 * init parser control flow helpers
31 *****************************************************************************/
34 init_exec(struct nvbios_init
*init
)
36 return (init
->execute
== 1) || ((init
->execute
& 5) == 5);
40 init_exec_set(struct nvbios_init
*init
, bool exec
)
42 if (exec
) init
->execute
&= 0xfd;
43 else init
->execute
|= 0x02;
47 init_exec_inv(struct nvbios_init
*init
)
49 init
->execute
^= 0x02;
53 init_exec_force(struct nvbios_init
*init
, bool exec
)
55 if (exec
) init
->execute
|= 0x04;
56 else init
->execute
&= 0xfb;
59 /******************************************************************************
60 * init parser wrappers for normal register/i2c/whatever accessors
61 *****************************************************************************/
64 init_or(struct nvbios_init
*init
)
66 if (init_exec(init
)) {
68 return ffs(init
->outp
->or) - 1;
69 error("script needs OR!!\n");
75 init_link(struct nvbios_init
*init
)
77 if (init_exec(init
)) {
79 return !(init
->outp
->sorconf
.link
& 1);
80 error("script needs OR link\n");
86 init_crtc(struct nvbios_init
*init
)
88 if (init_exec(init
)) {
91 error("script needs crtc\n");
97 init_conn(struct nvbios_init
*init
)
99 struct nouveau_bios
*bios
= init
->bios
;
103 if (init_exec(init
)) {
105 conn
= init
->outp
->connector
;
106 conn
= dcb_conn(bios
, conn
, &ver
, &len
);
108 return nv_ro08(bios
, conn
);
111 error("script needs connector type\n");
118 init_nvreg(struct nvbios_init
*init
, u32 reg
)
120 /* C51 (at least) sometimes has the lower bits set which the VBIOS
121 * interprets to mean that access needs to go through certain IO
122 * ports instead. The NVIDIA binary driver has been seen to access
123 * these through the NV register address, so lets assume we can
128 /* GF8+ display scripts need register addresses mangled a bit to
129 * select a specific CRTC/OR
131 if (nv_device(init
->bios
)->card_type
>= NV_50
) {
132 if (reg
& 0x80000000) {
133 reg
+= init_crtc(init
) * 0x800;
137 if (reg
& 0x40000000) {
138 reg
+= init_or(init
) * 0x800;
140 if (reg
& 0x20000000) {
141 reg
+= init_link(init
) * 0x80;
147 if (reg
& ~0x00fffffc)
148 warn("unknown bits in register 0x%08x\n", reg
);
153 init_rd32(struct nvbios_init
*init
, u32 reg
)
155 reg
= init_nvreg(init
, reg
);
157 return nv_rd32(init
->subdev
, reg
);
162 init_wr32(struct nvbios_init
*init
, u32 reg
, u32 val
)
164 reg
= init_nvreg(init
, reg
);
166 nv_wr32(init
->subdev
, reg
, val
);
170 init_mask(struct nvbios_init
*init
, u32 reg
, u32 mask
, u32 val
)
172 reg
= init_nvreg(init
, reg
);
173 if (init_exec(init
)) {
174 u32 tmp
= nv_rd32(init
->subdev
, reg
);
175 nv_wr32(init
->subdev
, reg
, (tmp
& ~mask
) | val
);
182 init_rdport(struct nvbios_init
*init
, u16 port
)
185 return nv_rdport(init
->subdev
, init
->crtc
, port
);
190 init_wrport(struct nvbios_init
*init
, u16 port
, u8 value
)
193 nv_wrport(init
->subdev
, init
->crtc
, port
, value
);
197 init_rdvgai(struct nvbios_init
*init
, u16 port
, u8 index
)
199 struct nouveau_subdev
*subdev
= init
->subdev
;
200 if (init_exec(init
)) {
201 int head
= init
->crtc
< 0 ? 0 : init
->crtc
;
202 return nv_rdvgai(subdev
, head
, port
, index
);
208 init_wrvgai(struct nvbios_init
*init
, u16 port
, u8 index
, u8 value
)
210 /* force head 0 for updates to cr44, it only exists on first head */
211 if (nv_device(init
->subdev
)->card_type
< NV_50
) {
212 if (port
== 0x03d4 && index
== 0x44)
216 if (init_exec(init
)) {
217 int head
= init
->crtc
< 0 ? 0 : init
->crtc
;
218 nv_wrvgai(init
->subdev
, head
, port
, index
, value
);
221 /* select head 1 if cr44 write selected it */
222 if (nv_device(init
->subdev
)->card_type
< NV_50
) {
223 if (port
== 0x03d4 && index
== 0x44 && value
== 3)
228 static struct nouveau_i2c_port
*
229 init_i2c(struct nvbios_init
*init
, int index
)
231 struct nouveau_i2c
*i2c
= nouveau_i2c(init
->bios
);
234 index
= NV_I2C_DEFAULT(0);
235 if (init
->outp
&& init
->outp
->i2c_upper_default
)
236 index
= NV_I2C_DEFAULT(1);
241 error("script needs output for i2c\n");
245 if (index
== -2 && init
->outp
->location
) {
246 index
= NV_I2C_TYPE_EXTAUX(init
->outp
->extdev
);
247 return i2c
->find_type(i2c
, index
);
250 index
= init
->outp
->i2c_index
;
253 return i2c
->find(i2c
, index
);
257 init_rdi2cr(struct nvbios_init
*init
, u8 index
, u8 addr
, u8 reg
)
259 struct nouveau_i2c_port
*port
= init_i2c(init
, index
);
260 if (port
&& init_exec(init
))
261 return nv_rdi2cr(port
, addr
, reg
);
266 init_wri2cr(struct nvbios_init
*init
, u8 index
, u8 addr
, u8 reg
, u8 val
)
268 struct nouveau_i2c_port
*port
= init_i2c(init
, index
);
269 if (port
&& init_exec(init
))
270 return nv_wri2cr(port
, addr
, reg
, val
);
275 init_rdauxr(struct nvbios_init
*init
, u32 addr
)
277 struct nouveau_i2c_port
*port
= init_i2c(init
, -2);
280 if (port
&& init_exec(init
)) {
281 int ret
= nv_rdaux(port
, addr
, &data
, 1);
291 init_wrauxr(struct nvbios_init
*init
, u32 addr
, u8 data
)
293 struct nouveau_i2c_port
*port
= init_i2c(init
, -2);
294 if (port
&& init_exec(init
))
295 return nv_wraux(port
, addr
, &data
, 1);
300 init_prog_pll(struct nvbios_init
*init
, u32 id
, u32 freq
)
302 struct nouveau_devinit
*devinit
= nouveau_devinit(init
->bios
);
303 if (devinit
->pll_set
&& init_exec(init
)) {
304 int ret
= devinit
->pll_set(devinit
, id
, freq
);
306 warn("failed to prog pll 0x%08x to %dkHz\n", id
, freq
);
310 /******************************************************************************
311 * parsing of bios structures that are required to execute init tables
312 *****************************************************************************/
315 init_table(struct nouveau_bios
*bios
, u16
*len
)
317 struct bit_entry bit_I
;
319 if (!bit_entry(bios
, 'I', &bit_I
)) {
324 if (bmp_version(bios
) >= 0x0510) {
326 return bios
->bmp_offset
+ 75;
333 init_table_(struct nvbios_init
*init
, u16 offset
, const char *name
)
335 struct nouveau_bios
*bios
= init
->bios
;
336 u16 len
, data
= init_table(bios
, &len
);
338 if (len
>= offset
+ 2) {
339 data
= nv_ro16(bios
, data
+ offset
);
343 warn("%s pointer invalid\n", name
);
347 warn("init data too short for %s pointer", name
);
351 warn("init data not found\n");
355 #define init_script_table(b) init_table_((b), 0x00, "script table")
356 #define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
357 #define init_macro_table(b) init_table_((b), 0x04, "macro table")
358 #define init_condition_table(b) init_table_((b), 0x06, "condition table")
359 #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
360 #define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
361 #define init_function_table(b) init_table_((b), 0x0c, "function table")
362 #define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
365 init_script(struct nouveau_bios
*bios
, int index
)
367 struct nvbios_init init
= { .bios
= bios
};
370 if (bmp_version(bios
) && bmp_version(bios
) < 0x0510) {
374 data
= bios
->bmp_offset
+ (bios
->version
.major
< 2 ? 14 : 18);
375 return nv_ro16(bios
, data
+ (index
* 2));
378 data
= init_script_table(&init
);
380 return nv_ro16(bios
, data
+ (index
* 2));
386 init_unknown_script(struct nouveau_bios
*bios
)
388 u16 len
, data
= init_table(bios
, &len
);
389 if (data
&& len
>= 16)
390 return nv_ro16(bios
, data
+ 14);
395 init_ram_restrict_table(struct nvbios_init
*init
)
397 struct nouveau_bios
*bios
= init
->bios
;
398 struct bit_entry bit_M
;
401 if (!bit_entry(bios
, 'M', &bit_M
)) {
402 if (bit_M
.version
== 1 && bit_M
.length
>= 5)
403 data
= nv_ro16(bios
, bit_M
.offset
+ 3);
404 if (bit_M
.version
== 2 && bit_M
.length
>= 3)
405 data
= nv_ro16(bios
, bit_M
.offset
+ 1);
409 warn("ram restrict table not found\n");
414 init_ram_restrict_group_count(struct nvbios_init
*init
)
416 struct nouveau_bios
*bios
= init
->bios
;
417 struct bit_entry bit_M
;
419 if (!bit_entry(bios
, 'M', &bit_M
)) {
420 if (bit_M
.version
== 1 && bit_M
.length
>= 5)
421 return nv_ro08(bios
, bit_M
.offset
+ 2);
422 if (bit_M
.version
== 2 && bit_M
.length
>= 3)
423 return nv_ro08(bios
, bit_M
.offset
+ 0);
430 init_ram_restrict_strap(struct nvbios_init
*init
)
432 /* This appears to be the behaviour of the VBIOS parser, and *is*
433 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to
434 * avoid fucking up the memory controller (somehow) by reading it
435 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode.
437 * Preserving the non-caching behaviour on earlier chipsets just
438 * in case *not* re-reading the strap causes similar breakage.
440 if (!init
->ramcfg
|| init
->bios
->version
.major
< 0x70)
441 init
->ramcfg
= init_rd32(init
, 0x101000);
442 return (init
->ramcfg
& 0x00000003c) >> 2;
446 init_ram_restrict(struct nvbios_init
*init
)
448 u8 strap
= init_ram_restrict_strap(init
);
449 u16 table
= init_ram_restrict_table(init
);
451 return nv_ro08(init
->bios
, table
+ strap
);
456 init_xlat_(struct nvbios_init
*init
, u8 index
, u8 offset
)
458 struct nouveau_bios
*bios
= init
->bios
;
459 u16 table
= init_xlat_table(init
);
461 u16 data
= nv_ro16(bios
, table
+ (index
* 2));
463 return nv_ro08(bios
, data
+ offset
);
464 warn("xlat table pointer %d invalid\n", index
);
469 /******************************************************************************
470 * utility functions used by various init opcode handlers
471 *****************************************************************************/
474 init_condition_met(struct nvbios_init
*init
, u8 cond
)
476 struct nouveau_bios
*bios
= init
->bios
;
477 u16 table
= init_condition_table(init
);
479 u32 reg
= nv_ro32(bios
, table
+ (cond
* 12) + 0);
480 u32 msk
= nv_ro32(bios
, table
+ (cond
* 12) + 4);
481 u32 val
= nv_ro32(bios
, table
+ (cond
* 12) + 8);
482 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
483 cond
, reg
, msk
, val
);
484 return (init_rd32(init
, reg
) & msk
) == val
;
490 init_io_condition_met(struct nvbios_init
*init
, u8 cond
)
492 struct nouveau_bios
*bios
= init
->bios
;
493 u16 table
= init_io_condition_table(init
);
495 u16 port
= nv_ro16(bios
, table
+ (cond
* 5) + 0);
496 u8 index
= nv_ro08(bios
, table
+ (cond
* 5) + 2);
497 u8 mask
= nv_ro08(bios
, table
+ (cond
* 5) + 3);
498 u8 value
= nv_ro08(bios
, table
+ (cond
* 5) + 4);
499 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
500 cond
, port
, index
, mask
, value
);
501 return (init_rdvgai(init
, port
, index
) & mask
) == value
;
507 init_io_flag_condition_met(struct nvbios_init
*init
, u8 cond
)
509 struct nouveau_bios
*bios
= init
->bios
;
510 u16 table
= init_io_flag_condition_table(init
);
512 u16 port
= nv_ro16(bios
, table
+ (cond
* 9) + 0);
513 u8 index
= nv_ro08(bios
, table
+ (cond
* 9) + 2);
514 u8 mask
= nv_ro08(bios
, table
+ (cond
* 9) + 3);
515 u8 shift
= nv_ro08(bios
, table
+ (cond
* 9) + 4);
516 u16 data
= nv_ro16(bios
, table
+ (cond
* 9) + 5);
517 u8 dmask
= nv_ro08(bios
, table
+ (cond
* 9) + 7);
518 u8 value
= nv_ro08(bios
, table
+ (cond
* 9) + 8);
519 u8 ioval
= (init_rdvgai(init
, port
, index
) & mask
) >> shift
;
520 return (nv_ro08(bios
, data
+ ioval
) & dmask
) == value
;
526 init_shift(u32 data
, u8 shift
)
529 return data
>> shift
;
530 return data
<< (0x100 - shift
);
534 init_tmds_reg(struct nvbios_init
*init
, u8 tmds
)
536 /* For mlv < 0x80, it is an index into a table of TMDS base addresses.
537 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
538 * CR58 for CR57 = 0 to index a table of offsets to the basic
540 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
541 * CR58 for CR57 = 0 to index a table of offsets to the basic
542 * 0x6808b0 address, and then flip the offset by 8.
545 const int pramdac_offset
[13] = {
546 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
547 const u32 pramdac_table
[4] = {
548 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
552 u32 dacoffset
= pramdac_offset
[init
->outp
->or];
555 return 0x6808b0 + dacoffset
;
559 error("tmds opcodes need dcb\n");
561 if (tmds
< ARRAY_SIZE(pramdac_table
))
562 return pramdac_table
[tmds
];
564 error("tmds selector 0x%02x unknown\n", tmds
);
570 /******************************************************************************
571 * init opcode handlers
572 *****************************************************************************/
575 * init_reserved - stub for various unknown/unused single-byte opcodes
579 init_reserved(struct nvbios_init
*init
)
581 u8 opcode
= nv_ro08(init
->bios
, init
->offset
);
582 trace("RESERVED\t0x%02x\n", opcode
);
587 * INIT_DONE - opcode 0x71
591 init_done(struct nvbios_init
*init
)
594 init
->offset
= 0x0000;
598 * INIT_IO_RESTRICT_PROG - opcode 0x32
602 init_io_restrict_prog(struct nvbios_init
*init
)
604 struct nouveau_bios
*bios
= init
->bios
;
605 u16 port
= nv_ro16(bios
, init
->offset
+ 1);
606 u8 index
= nv_ro08(bios
, init
->offset
+ 3);
607 u8 mask
= nv_ro08(bios
, init
->offset
+ 4);
608 u8 shift
= nv_ro08(bios
, init
->offset
+ 5);
609 u8 count
= nv_ro08(bios
, init
->offset
+ 6);
610 u32 reg
= nv_ro32(bios
, init
->offset
+ 7);
613 trace("IO_RESTRICT_PROG\tR[0x%06x] = "
614 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
615 reg
, port
, index
, mask
, shift
);
618 conf
= (init_rdvgai(init
, port
, index
) & mask
) >> shift
;
619 for (i
= 0; i
< count
; i
++) {
620 u32 data
= nv_ro32(bios
, init
->offset
);
623 trace("\t0x%08x *\n", data
);
624 init_wr32(init
, reg
, data
);
626 trace("\t0x%08x\n", data
);
635 * INIT_REPEAT - opcode 0x33
639 init_repeat(struct nvbios_init
*init
)
641 struct nouveau_bios
*bios
= init
->bios
;
642 u8 count
= nv_ro08(bios
, init
->offset
+ 1);
643 u16 repeat
= init
->repeat
;
645 trace("REPEAT\t0x%02x\n", count
);
648 init
->repeat
= init
->offset
;
649 init
->repend
= init
->offset
;
651 init
->offset
= init
->repeat
;
654 trace("REPEAT\t0x%02x\n", count
);
656 init
->offset
= init
->repend
;
657 init
->repeat
= repeat
;
661 * INIT_IO_RESTRICT_PLL - opcode 0x34
665 init_io_restrict_pll(struct nvbios_init
*init
)
667 struct nouveau_bios
*bios
= init
->bios
;
668 u16 port
= nv_ro16(bios
, init
->offset
+ 1);
669 u8 index
= nv_ro08(bios
, init
->offset
+ 3);
670 u8 mask
= nv_ro08(bios
, init
->offset
+ 4);
671 u8 shift
= nv_ro08(bios
, init
->offset
+ 5);
672 s8 iofc
= nv_ro08(bios
, init
->offset
+ 6);
673 u8 count
= nv_ro08(bios
, init
->offset
+ 7);
674 u32 reg
= nv_ro32(bios
, init
->offset
+ 8);
677 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
678 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
679 reg
, port
, index
, mask
, shift
, iofc
);
682 conf
= (init_rdvgai(init
, port
, index
) & mask
) >> shift
;
683 for (i
= 0; i
< count
; i
++) {
684 u32 freq
= nv_ro16(bios
, init
->offset
) * 10;
687 trace("\t%dkHz *\n", freq
);
688 if (iofc
> 0 && init_io_flag_condition_met(init
, iofc
))
690 init_prog_pll(init
, reg
, freq
);
692 trace("\t%dkHz\n", freq
);
701 * INIT_END_REPEAT - opcode 0x36
705 init_end_repeat(struct nvbios_init
*init
)
707 trace("END_REPEAT\n");
711 init
->repend
= init
->offset
;
717 * INIT_COPY - opcode 0x37
721 init_copy(struct nvbios_init
*init
)
723 struct nouveau_bios
*bios
= init
->bios
;
724 u32 reg
= nv_ro32(bios
, init
->offset
+ 1);
725 u8 shift
= nv_ro08(bios
, init
->offset
+ 5);
726 u8 smask
= nv_ro08(bios
, init
->offset
+ 6);
727 u16 port
= nv_ro16(bios
, init
->offset
+ 7);
728 u8 index
= nv_ro08(bios
, init
->offset
+ 9);
729 u8 mask
= nv_ro08(bios
, init
->offset
+ 10);
732 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
733 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
734 port
, index
, mask
, reg
, (shift
& 0x80) ? "<<" : ">>",
735 (shift
& 0x80) ? (0x100 - shift
) : shift
, smask
);
738 data
= init_rdvgai(init
, port
, index
) & mask
;
739 data
|= init_shift(init_rd32(init
, reg
), shift
) & smask
;
740 init_wrvgai(init
, port
, index
, data
);
744 * INIT_NOT - opcode 0x38
748 init_not(struct nvbios_init
*init
)
756 * INIT_IO_FLAG_CONDITION - opcode 0x39
760 init_io_flag_condition(struct nvbios_init
*init
)
762 struct nouveau_bios
*bios
= init
->bios
;
763 u8 cond
= nv_ro08(bios
, init
->offset
+ 1);
765 trace("IO_FLAG_CONDITION\t0x%02x\n", cond
);
768 if (!init_io_flag_condition_met(init
, cond
))
769 init_exec_set(init
, false);
773 * INIT_DP_CONDITION - opcode 0x3a
777 init_dp_condition(struct nvbios_init
*init
)
779 struct nouveau_bios
*bios
= init
->bios
;
780 struct nvbios_dpout info
;
781 u8 cond
= nv_ro08(bios
, init
->offset
+ 1);
782 u8 unkn
= nv_ro08(bios
, init
->offset
+ 2);
783 u8 ver
, hdr
, cnt
, len
;
786 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond
, unkn
);
791 if (init_conn(init
) != DCB_CONNECTOR_eDP
)
792 init_exec_set(init
, false);
797 (data
= nvbios_dpout_match(bios
, DCB_OUTPUT_DP
,
798 (init
->outp
->or << 0) |
799 (init
->outp
->sorconf
.link
<< 6),
800 &ver
, &hdr
, &cnt
, &len
, &info
)))
802 if (!(info
.flags
& cond
))
803 init_exec_set(init
, false);
808 warn("script needs dp output table data\n");
811 if (!(init_rdauxr(init
, 0x0d) & 1))
812 init_exec_set(init
, false);
815 warn("unknown dp condition 0x%02x\n", cond
);
821 * INIT_IO_MASK_OR - opcode 0x3b
825 init_io_mask_or(struct nvbios_init
*init
)
827 struct nouveau_bios
*bios
= init
->bios
;
828 u8 index
= nv_ro08(bios
, init
->offset
+ 1);
829 u8
or = init_or(init
);
832 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index
, or);
835 data
= init_rdvgai(init
, 0x03d4, index
);
836 init_wrvgai(init
, 0x03d4, index
, data
&= ~(1 << or));
840 * INIT_IO_OR - opcode 0x3c
844 init_io_or(struct nvbios_init
*init
)
846 struct nouveau_bios
*bios
= init
->bios
;
847 u8 index
= nv_ro08(bios
, init
->offset
+ 1);
848 u8
or = init_or(init
);
851 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index
, or);
854 data
= init_rdvgai(init
, 0x03d4, index
);
855 init_wrvgai(init
, 0x03d4, index
, data
| (1 << or));
859 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49
863 init_idx_addr_latched(struct nvbios_init
*init
)
865 struct nouveau_bios
*bios
= init
->bios
;
866 u32 creg
= nv_ro32(bios
, init
->offset
+ 1);
867 u32 dreg
= nv_ro32(bios
, init
->offset
+ 5);
868 u32 mask
= nv_ro32(bios
, init
->offset
+ 9);
869 u32 data
= nv_ro32(bios
, init
->offset
+ 13);
870 u8 count
= nv_ro08(bios
, init
->offset
+ 17);
872 trace("INDEX_ADDRESS_LATCHED\t"
873 "R[0x%06x] : R[0x%06x]\n\tCTRL &= 0x%08x |= 0x%08x\n",
874 creg
, dreg
, mask
, data
);
878 u8 iaddr
= nv_ro08(bios
, init
->offset
+ 0);
879 u8 idata
= nv_ro08(bios
, init
->offset
+ 1);
881 trace("\t[0x%02x] = 0x%02x\n", iaddr
, idata
);
884 init_wr32(init
, dreg
, idata
);
885 init_mask(init
, creg
, ~mask
, data
| iaddr
);
890 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a
894 init_io_restrict_pll2(struct nvbios_init
*init
)
896 struct nouveau_bios
*bios
= init
->bios
;
897 u16 port
= nv_ro16(bios
, init
->offset
+ 1);
898 u8 index
= nv_ro08(bios
, init
->offset
+ 3);
899 u8 mask
= nv_ro08(bios
, init
->offset
+ 4);
900 u8 shift
= nv_ro08(bios
, init
->offset
+ 5);
901 u8 count
= nv_ro08(bios
, init
->offset
+ 6);
902 u32 reg
= nv_ro32(bios
, init
->offset
+ 7);
905 trace("IO_RESTRICT_PLL2\t"
906 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
907 reg
, port
, index
, mask
, shift
);
910 conf
= (init_rdvgai(init
, port
, index
) & mask
) >> shift
;
911 for (i
= 0; i
< count
; i
++) {
912 u32 freq
= nv_ro32(bios
, init
->offset
);
914 trace("\t%dkHz *\n", freq
);
915 init_prog_pll(init
, reg
, freq
);
917 trace("\t%dkHz\n", freq
);
925 * INIT_PLL2 - opcode 0x4b
929 init_pll2(struct nvbios_init
*init
)
931 struct nouveau_bios
*bios
= init
->bios
;
932 u32 reg
= nv_ro32(bios
, init
->offset
+ 1);
933 u32 freq
= nv_ro32(bios
, init
->offset
+ 5);
935 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg
, freq
);
938 init_prog_pll(init
, reg
, freq
);
942 * INIT_I2C_BYTE - opcode 0x4c
946 init_i2c_byte(struct nvbios_init
*init
)
948 struct nouveau_bios
*bios
= init
->bios
;
949 u8 index
= nv_ro08(bios
, init
->offset
+ 1);
950 u8 addr
= nv_ro08(bios
, init
->offset
+ 2) >> 1;
951 u8 count
= nv_ro08(bios
, init
->offset
+ 3);
953 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index
, addr
);
957 u8 reg
= nv_ro08(bios
, init
->offset
+ 0);
958 u8 mask
= nv_ro08(bios
, init
->offset
+ 1);
959 u8 data
= nv_ro08(bios
, init
->offset
+ 2);
962 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg
, mask
, data
);
965 val
= init_rdi2cr(init
, index
, addr
, reg
);
968 init_wri2cr(init
, index
, addr
, reg
, (val
& mask
) | data
);
973 * INIT_ZM_I2C_BYTE - opcode 0x4d
977 init_zm_i2c_byte(struct nvbios_init
*init
)
979 struct nouveau_bios
*bios
= init
->bios
;
980 u8 index
= nv_ro08(bios
, init
->offset
+ 1);
981 u8 addr
= nv_ro08(bios
, init
->offset
+ 2) >> 1;
982 u8 count
= nv_ro08(bios
, init
->offset
+ 3);
984 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index
, addr
);
988 u8 reg
= nv_ro08(bios
, init
->offset
+ 0);
989 u8 data
= nv_ro08(bios
, init
->offset
+ 1);
991 trace("\t[0x%02x] = 0x%02x\n", reg
, data
);
994 init_wri2cr(init
, index
, addr
, reg
, data
);
1000 * INIT_ZM_I2C - opcode 0x4e
1004 init_zm_i2c(struct nvbios_init
*init
)
1006 struct nouveau_bios
*bios
= init
->bios
;
1007 u8 index
= nv_ro08(bios
, init
->offset
+ 1);
1008 u8 addr
= nv_ro08(bios
, init
->offset
+ 2) >> 1;
1009 u8 count
= nv_ro08(bios
, init
->offset
+ 3);
1012 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index
, addr
);
1015 for (i
= 0; i
< count
; i
++) {
1016 data
[i
] = nv_ro08(bios
, init
->offset
);
1017 trace("\t0x%02x\n", data
[i
]);
1021 if (init_exec(init
)) {
1022 struct nouveau_i2c_port
*port
= init_i2c(init
, index
);
1023 struct i2c_msg msg
= {
1024 .addr
= addr
, .flags
= 0, .len
= count
, .buf
= data
,
1028 if (port
&& (ret
= i2c_transfer(&port
->adapter
, &msg
, 1)) != 1)
1029 warn("i2c wr failed, %d\n", ret
);
1034 * INIT_TMDS - opcode 0x4f
1038 init_tmds(struct nvbios_init
*init
)
1040 struct nouveau_bios
*bios
= init
->bios
;
1041 u8 tmds
= nv_ro08(bios
, init
->offset
+ 1);
1042 u8 addr
= nv_ro08(bios
, init
->offset
+ 2);
1043 u8 mask
= nv_ro08(bios
, init
->offset
+ 3);
1044 u8 data
= nv_ro08(bios
, init
->offset
+ 4);
1045 u32 reg
= init_tmds_reg(init
, tmds
);
1047 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1048 tmds
, addr
, mask
, data
);
1054 init_wr32(init
, reg
+ 0, addr
| 0x00010000);
1055 init_wr32(init
, reg
+ 4, data
| (init_rd32(init
, reg
+ 4) & mask
));
1056 init_wr32(init
, reg
+ 0, addr
);
1060 * INIT_ZM_TMDS_GROUP - opcode 0x50
1064 init_zm_tmds_group(struct nvbios_init
*init
)
1066 struct nouveau_bios
*bios
= init
->bios
;
1067 u8 tmds
= nv_ro08(bios
, init
->offset
+ 1);
1068 u8 count
= nv_ro08(bios
, init
->offset
+ 2);
1069 u32 reg
= init_tmds_reg(init
, tmds
);
1071 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds
);
1075 u8 addr
= nv_ro08(bios
, init
->offset
+ 0);
1076 u8 data
= nv_ro08(bios
, init
->offset
+ 1);
1078 trace("\t[0x%02x] = 0x%02x\n", addr
, data
);
1081 init_wr32(init
, reg
+ 4, data
);
1082 init_wr32(init
, reg
+ 0, addr
);
1087 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51
1091 init_cr_idx_adr_latch(struct nvbios_init
*init
)
1093 struct nouveau_bios
*bios
= init
->bios
;
1094 u8 addr0
= nv_ro08(bios
, init
->offset
+ 1);
1095 u8 addr1
= nv_ro08(bios
, init
->offset
+ 2);
1096 u8 base
= nv_ro08(bios
, init
->offset
+ 3);
1097 u8 count
= nv_ro08(bios
, init
->offset
+ 4);
1100 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0
, addr1
);
1103 save0
= init_rdvgai(init
, 0x03d4, addr0
);
1105 u8 data
= nv_ro08(bios
, init
->offset
);
1107 trace("\t\t[0x%02x] = 0x%02x\n", base
, data
);
1110 init_wrvgai(init
, 0x03d4, addr0
, base
++);
1111 init_wrvgai(init
, 0x03d4, addr1
, data
);
1113 init_wrvgai(init
, 0x03d4, addr0
, save0
);
1117 * INIT_CR - opcode 0x52
1121 init_cr(struct nvbios_init
*init
)
1123 struct nouveau_bios
*bios
= init
->bios
;
1124 u8 addr
= nv_ro08(bios
, init
->offset
+ 1);
1125 u8 mask
= nv_ro08(bios
, init
->offset
+ 2);
1126 u8 data
= nv_ro08(bios
, init
->offset
+ 3);
1129 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr
, mask
, data
);
1132 val
= init_rdvgai(init
, 0x03d4, addr
) & mask
;
1133 init_wrvgai(init
, 0x03d4, addr
, val
| data
);
1137 * INIT_ZM_CR - opcode 0x53
1141 init_zm_cr(struct nvbios_init
*init
)
1143 struct nouveau_bios
*bios
= init
->bios
;
1144 u8 addr
= nv_ro08(bios
, init
->offset
+ 1);
1145 u8 data
= nv_ro08(bios
, init
->offset
+ 2);
1147 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr
, data
);
1150 init_wrvgai(init
, 0x03d4, addr
, data
);
1154 * INIT_ZM_CR_GROUP - opcode 0x54
1158 init_zm_cr_group(struct nvbios_init
*init
)
1160 struct nouveau_bios
*bios
= init
->bios
;
1161 u8 count
= nv_ro08(bios
, init
->offset
+ 1);
1163 trace("ZM_CR_GROUP\n");
1167 u8 addr
= nv_ro08(bios
, init
->offset
+ 0);
1168 u8 data
= nv_ro08(bios
, init
->offset
+ 1);
1170 trace("\t\tC[0x%02x] = 0x%02x\n", addr
, data
);
1173 init_wrvgai(init
, 0x03d4, addr
, data
);
1178 * INIT_CONDITION_TIME - opcode 0x56
1182 init_condition_time(struct nvbios_init
*init
)
1184 struct nouveau_bios
*bios
= init
->bios
;
1185 u8 cond
= nv_ro08(bios
, init
->offset
+ 1);
1186 u8 retry
= nv_ro08(bios
, init
->offset
+ 2);
1187 u8 wait
= min((u16
)retry
* 50, 100);
1189 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond
, retry
);
1192 if (!init_exec(init
))
1196 if (init_condition_met(init
, cond
))
1201 init_exec_set(init
, false);
1205 * INIT_LTIME - opcode 0x57
1209 init_ltime(struct nvbios_init
*init
)
1211 struct nouveau_bios
*bios
= init
->bios
;
1212 u16 msec
= nv_ro16(bios
, init
->offset
+ 1);
1214 trace("LTIME\t0x%04x\n", msec
);
1217 if (init_exec(init
))
1222 * INIT_ZM_REG_SEQUENCE - opcode 0x58
1226 init_zm_reg_sequence(struct nvbios_init
*init
)
1228 struct nouveau_bios
*bios
= init
->bios
;
1229 u32 base
= nv_ro32(bios
, init
->offset
+ 1);
1230 u8 count
= nv_ro08(bios
, init
->offset
+ 5);
1232 trace("ZM_REG_SEQUENCE\t0x%02x\n", count
);
1236 u32 data
= nv_ro32(bios
, init
->offset
);
1238 trace("\t\tR[0x%06x] = 0x%08x\n", base
, data
);
1241 init_wr32(init
, base
, data
);
1247 * INIT_SUB_DIRECT - opcode 0x5b
1251 init_sub_direct(struct nvbios_init
*init
)
1253 struct nouveau_bios
*bios
= init
->bios
;
1254 u16 addr
= nv_ro16(bios
, init
->offset
+ 1);
1257 trace("SUB_DIRECT\t0x%04x\n", addr
);
1259 if (init_exec(init
)) {
1260 save
= init
->offset
;
1261 init
->offset
= addr
;
1262 if (nvbios_exec(init
)) {
1263 error("error parsing sub-table\n");
1266 init
->offset
= save
;
1273 * INIT_JUMP - opcode 0x5c
1277 init_jump(struct nvbios_init
*init
)
1279 struct nouveau_bios
*bios
= init
->bios
;
1280 u16 offset
= nv_ro16(bios
, init
->offset
+ 1);
1282 trace("JUMP\t0x%04x\n", offset
);
1283 init
->offset
= offset
;
1287 * INIT_I2C_IF - opcode 0x5e
1291 init_i2c_if(struct nvbios_init
*init
)
1293 struct nouveau_bios
*bios
= init
->bios
;
1294 u8 index
= nv_ro08(bios
, init
->offset
+ 1);
1295 u8 addr
= nv_ro08(bios
, init
->offset
+ 2);
1296 u8 reg
= nv_ro08(bios
, init
->offset
+ 3);
1297 u8 mask
= nv_ro08(bios
, init
->offset
+ 4);
1298 u8 data
= nv_ro08(bios
, init
->offset
+ 5);
1301 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1302 index
, addr
, reg
, mask
, data
);
1304 init_exec_force(init
, true);
1306 value
= init_rdi2cr(init
, index
, addr
, reg
);
1307 if ((value
& mask
) != data
)
1308 init_exec_set(init
, false);
1310 init_exec_force(init
, false);
1314 * INIT_COPY_NV_REG - opcode 0x5f
1318 init_copy_nv_reg(struct nvbios_init
*init
)
1320 struct nouveau_bios
*bios
= init
->bios
;
1321 u32 sreg
= nv_ro32(bios
, init
->offset
+ 1);
1322 u8 shift
= nv_ro08(bios
, init
->offset
+ 5);
1323 u32 smask
= nv_ro32(bios
, init
->offset
+ 6);
1324 u32 sxor
= nv_ro32(bios
, init
->offset
+ 10);
1325 u32 dreg
= nv_ro32(bios
, init
->offset
+ 14);
1326 u32 dmask
= nv_ro32(bios
, init
->offset
+ 18);
1329 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1330 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1331 dreg
, dmask
, sreg
, (shift
& 0x80) ? "<<" : ">>",
1332 (shift
& 0x80) ? (0x100 - shift
) : shift
, smask
, sxor
);
1335 data
= init_shift(init_rd32(init
, sreg
), shift
);
1336 init_mask(init
, dreg
, ~dmask
, (data
& smask
) ^ sxor
);
1340 * INIT_ZM_INDEX_IO - opcode 0x62
1344 init_zm_index_io(struct nvbios_init
*init
)
1346 struct nouveau_bios
*bios
= init
->bios
;
1347 u16 port
= nv_ro16(bios
, init
->offset
+ 1);
1348 u8 index
= nv_ro08(bios
, init
->offset
+ 3);
1349 u8 data
= nv_ro08(bios
, init
->offset
+ 4);
1351 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port
, index
, data
);
1354 init_wrvgai(init
, port
, index
, data
);
1358 * INIT_COMPUTE_MEM - opcode 0x63
1362 init_compute_mem(struct nvbios_init
*init
)
1364 struct nouveau_devinit
*devinit
= nouveau_devinit(init
->bios
);
1366 trace("COMPUTE_MEM\n");
1369 init_exec_force(init
, true);
1370 if (init_exec(init
) && devinit
->meminit
)
1371 devinit
->meminit(devinit
);
1372 init_exec_force(init
, false);
1376 * INIT_RESET - opcode 0x65
1380 init_reset(struct nvbios_init
*init
)
1382 struct nouveau_bios
*bios
= init
->bios
;
1383 u32 reg
= nv_ro32(bios
, init
->offset
+ 1);
1384 u32 data1
= nv_ro32(bios
, init
->offset
+ 5);
1385 u32 data2
= nv_ro32(bios
, init
->offset
+ 9);
1388 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg
, data1
, data2
);
1390 init_exec_force(init
, true);
1392 savepci19
= init_mask(init
, 0x00184c, 0x00000f00, 0x00000000);
1393 init_wr32(init
, reg
, data1
);
1395 init_wr32(init
, reg
, data2
);
1396 init_wr32(init
, 0x00184c, savepci19
);
1397 init_mask(init
, 0x001850, 0x00000001, 0x00000000);
1399 init_exec_force(init
, false);
1403 * INIT_CONFIGURE_MEM - opcode 0x66
1407 init_configure_mem_clk(struct nvbios_init
*init
)
1409 u16 mdata
= bmp_mem_init_table(init
->bios
);
1411 mdata
+= (init_rdvgai(init
, 0x03d4, 0x3c) >> 4) * 66;
1416 init_configure_mem(struct nvbios_init
*init
)
1418 struct nouveau_bios
*bios
= init
->bios
;
1422 trace("CONFIGURE_MEM\n");
1425 if (bios
->version
.major
> 2) {
1429 init_exec_force(init
, true);
1431 mdata
= init_configure_mem_clk(init
);
1432 sdata
= bmp_sdr_seq_table(bios
);
1433 if (nv_ro08(bios
, mdata
) & 0x01)
1434 sdata
= bmp_ddr_seq_table(bios
);
1435 mdata
+= 6; /* skip to data */
1437 data
= init_rdvgai(init
, 0x03c4, 0x01);
1438 init_wrvgai(init
, 0x03c4, 0x01, data
| 0x20);
1440 while ((addr
= nv_ro32(bios
, sdata
)) != 0xffffffff) {
1442 case 0x10021c: /* CKE_NORMAL */
1443 case 0x1002d0: /* CMD_REFRESH */
1444 case 0x1002d4: /* CMD_PRECHARGE */
1448 data
= nv_ro32(bios
, mdata
);
1450 if (data
== 0xffffffff)
1455 init_wr32(init
, addr
, data
);
1458 init_exec_force(init
, false);
1462 * INIT_CONFIGURE_CLK - opcode 0x67
1466 init_configure_clk(struct nvbios_init
*init
)
1468 struct nouveau_bios
*bios
= init
->bios
;
1471 trace("CONFIGURE_CLK\n");
1474 if (bios
->version
.major
> 2) {
1478 init_exec_force(init
, true);
1480 mdata
= init_configure_mem_clk(init
);
1483 clock
= nv_ro16(bios
, mdata
+ 4) * 10;
1484 init_prog_pll(init
, 0x680500, clock
);
1487 clock
= nv_ro16(bios
, mdata
+ 2) * 10;
1488 if (nv_ro08(bios
, mdata
) & 0x01)
1490 init_prog_pll(init
, 0x680504, clock
);
1492 init_exec_force(init
, false);
1496 * INIT_CONFIGURE_PREINIT - opcode 0x68
1500 init_configure_preinit(struct nvbios_init
*init
)
1502 struct nouveau_bios
*bios
= init
->bios
;
1505 trace("CONFIGURE_PREINIT\n");
1508 if (bios
->version
.major
> 2) {
1512 init_exec_force(init
, true);
1514 strap
= init_rd32(init
, 0x101000);
1515 strap
= ((strap
<< 2) & 0xf0) | ((strap
& 0x40) >> 6);
1516 init_wrvgai(init
, 0x03d4, 0x3c, strap
);
1518 init_exec_force(init
, false);
1522 * INIT_IO - opcode 0x69
1526 init_io(struct nvbios_init
*init
)
1528 struct nouveau_bios
*bios
= init
->bios
;
1529 u16 port
= nv_ro16(bios
, init
->offset
+ 1);
1530 u8 mask
= nv_ro16(bios
, init
->offset
+ 3);
1531 u8 data
= nv_ro16(bios
, init
->offset
+ 4);
1534 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port
, mask
, data
);
1537 /* ummm.. yes.. should really figure out wtf this is and why it's
1538 * needed some day.. it's almost certainly wrong, but, it also
1539 * somehow makes things work...
1541 if (nv_device(init
->bios
)->card_type
>= NV_50
&&
1542 port
== 0x03c3 && data
== 0x01) {
1543 init_mask(init
, 0x614100, 0xf0800000, 0x00800000);
1544 init_mask(init
, 0x00e18c, 0x00020000, 0x00020000);
1545 init_mask(init
, 0x614900, 0xf0800000, 0x00800000);
1546 init_mask(init
, 0x000200, 0x40000000, 0x00000000);
1548 init_mask(init
, 0x00e18c, 0x00020000, 0x00000000);
1549 init_mask(init
, 0x000200, 0x40000000, 0x40000000);
1550 init_wr32(init
, 0x614100, 0x00800018);
1551 init_wr32(init
, 0x614900, 0x00800018);
1553 init_wr32(init
, 0x614100, 0x10000018);
1554 init_wr32(init
, 0x614900, 0x10000018);
1557 value
= init_rdport(init
, port
) & mask
;
1558 init_wrport(init
, port
, data
| value
);
1562 * INIT_SUB - opcode 0x6b
1566 init_sub(struct nvbios_init
*init
)
1568 struct nouveau_bios
*bios
= init
->bios
;
1569 u8 index
= nv_ro08(bios
, init
->offset
+ 1);
1572 trace("SUB\t0x%02x\n", index
);
1574 addr
= init_script(bios
, index
);
1575 if (addr
&& init_exec(init
)) {
1576 save
= init
->offset
;
1577 init
->offset
= addr
;
1578 if (nvbios_exec(init
)) {
1579 error("error parsing sub-table\n");
1582 init
->offset
= save
;
1589 * INIT_RAM_CONDITION - opcode 0x6d
1593 init_ram_condition(struct nvbios_init
*init
)
1595 struct nouveau_bios
*bios
= init
->bios
;
1596 u8 mask
= nv_ro08(bios
, init
->offset
+ 1);
1597 u8 value
= nv_ro08(bios
, init
->offset
+ 2);
1599 trace("RAM_CONDITION\t"
1600 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask
, value
);
1603 if ((init_rd32(init
, 0x100000) & mask
) != value
)
1604 init_exec_set(init
, false);
1608 * INIT_NV_REG - opcode 0x6e
1612 init_nv_reg(struct nvbios_init
*init
)
1614 struct nouveau_bios
*bios
= init
->bios
;
1615 u32 reg
= nv_ro32(bios
, init
->offset
+ 1);
1616 u32 mask
= nv_ro32(bios
, init
->offset
+ 5);
1617 u32 data
= nv_ro32(bios
, init
->offset
+ 9);
1619 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg
, mask
, data
);
1622 init_mask(init
, reg
, ~mask
, data
);
1626 * INIT_MACRO - opcode 0x6f
1630 init_macro(struct nvbios_init
*init
)
1632 struct nouveau_bios
*bios
= init
->bios
;
1633 u8 macro
= nv_ro08(bios
, init
->offset
+ 1);
1636 trace("MACRO\t0x%02x\n", macro
);
1638 table
= init_macro_table(init
);
1640 u32 addr
= nv_ro32(bios
, table
+ (macro
* 8) + 0);
1641 u32 data
= nv_ro32(bios
, table
+ (macro
* 8) + 4);
1642 trace("\t\tR[0x%06x] = 0x%08x\n", addr
, data
);
1643 init_wr32(init
, addr
, data
);
1650 * INIT_RESUME - opcode 0x72
1654 init_resume(struct nvbios_init
*init
)
1658 init_exec_set(init
, true);
1662 * INIT_TIME - opcode 0x74
1666 init_time(struct nvbios_init
*init
)
1668 struct nouveau_bios
*bios
= init
->bios
;
1669 u16 usec
= nv_ro16(bios
, init
->offset
+ 1);
1671 trace("TIME\t0x%04x\n", usec
);
1674 if (init_exec(init
)) {
1678 mdelay((usec
+ 900) / 1000);
1683 * INIT_CONDITION - opcode 0x75
1687 init_condition(struct nvbios_init
*init
)
1689 struct nouveau_bios
*bios
= init
->bios
;
1690 u8 cond
= nv_ro08(bios
, init
->offset
+ 1);
1692 trace("CONDITION\t0x%02x\n", cond
);
1695 if (!init_condition_met(init
, cond
))
1696 init_exec_set(init
, false);
1700 * INIT_IO_CONDITION - opcode 0x76
1704 init_io_condition(struct nvbios_init
*init
)
1706 struct nouveau_bios
*bios
= init
->bios
;
1707 u8 cond
= nv_ro08(bios
, init
->offset
+ 1);
1709 trace("IO_CONDITION\t0x%02x\n", cond
);
1712 if (!init_io_condition_met(init
, cond
))
1713 init_exec_set(init
, false);
1717 * INIT_INDEX_IO - opcode 0x78
1721 init_index_io(struct nvbios_init
*init
)
1723 struct nouveau_bios
*bios
= init
->bios
;
1724 u16 port
= nv_ro16(bios
, init
->offset
+ 1);
1725 u8 index
= nv_ro16(bios
, init
->offset
+ 3);
1726 u8 mask
= nv_ro08(bios
, init
->offset
+ 4);
1727 u8 data
= nv_ro08(bios
, init
->offset
+ 5);
1730 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1731 port
, index
, mask
, data
);
1734 value
= init_rdvgai(init
, port
, index
) & mask
;
1735 init_wrvgai(init
, port
, index
, data
| value
);
1739 * INIT_PLL - opcode 0x79
1743 init_pll(struct nvbios_init
*init
)
1745 struct nouveau_bios
*bios
= init
->bios
;
1746 u32 reg
= nv_ro32(bios
, init
->offset
+ 1);
1747 u32 freq
= nv_ro16(bios
, init
->offset
+ 5) * 10;
1749 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg
, freq
);
1752 init_prog_pll(init
, reg
, freq
);
1756 * INIT_ZM_REG - opcode 0x7a
1760 init_zm_reg(struct nvbios_init
*init
)
1762 struct nouveau_bios
*bios
= init
->bios
;
1763 u32 addr
= nv_ro32(bios
, init
->offset
+ 1);
1764 u32 data
= nv_ro32(bios
, init
->offset
+ 5);
1766 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr
, data
);
1769 if (addr
== 0x000200)
1772 init_wr32(init
, addr
, data
);
1776 * INIT_RAM_RESTRICT_PLL - opcde 0x87
1780 init_ram_restrict_pll(struct nvbios_init
*init
)
1782 struct nouveau_bios
*bios
= init
->bios
;
1783 u8 type
= nv_ro08(bios
, init
->offset
+ 1);
1784 u8 count
= init_ram_restrict_group_count(init
);
1785 u8 strap
= init_ram_restrict(init
);
1788 trace("RAM_RESTRICT_PLL\t0x%02x\n", type
);
1791 for (cconf
= 0; cconf
< count
; cconf
++) {
1792 u32 freq
= nv_ro32(bios
, init
->offset
);
1794 if (cconf
== strap
) {
1795 trace("%dkHz *\n", freq
);
1796 init_prog_pll(init
, type
, freq
);
1798 trace("%dkHz\n", freq
);
1806 * INIT_GPIO - opcode 0x8e
1810 init_gpio(struct nvbios_init
*init
)
1812 struct nouveau_gpio
*gpio
= nouveau_gpio(init
->bios
);
1817 if (init_exec(init
) && gpio
&& gpio
->reset
)
1818 gpio
->reset(gpio
, DCB_GPIO_UNUSED
);
1822 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f
1826 init_ram_restrict_zm_reg_group(struct nvbios_init
*init
)
1828 struct nouveau_bios
*bios
= init
->bios
;
1829 u32 addr
= nv_ro32(bios
, init
->offset
+ 1);
1830 u8 incr
= nv_ro08(bios
, init
->offset
+ 5);
1831 u8 num
= nv_ro08(bios
, init
->offset
+ 6);
1832 u8 count
= init_ram_restrict_group_count(init
);
1833 u8 index
= init_ram_restrict(init
);
1836 trace("RAM_RESTRICT_ZM_REG_GROUP\t"
1837 "R[0x%08x] 0x%02x 0x%02x\n", addr
, incr
, num
);
1840 for (i
= 0; i
< num
; i
++) {
1841 trace("\tR[0x%06x] = {\n", addr
);
1842 for (j
= 0; j
< count
; j
++) {
1843 u32 data
= nv_ro32(bios
, init
->offset
);
1846 trace("\t\t0x%08x *\n", data
);
1847 init_wr32(init
, addr
, data
);
1849 trace("\t\t0x%08x\n", data
);
1860 * INIT_COPY_ZM_REG - opcode 0x90
1864 init_copy_zm_reg(struct nvbios_init
*init
)
1866 struct nouveau_bios
*bios
= init
->bios
;
1867 u32 sreg
= nv_ro32(bios
, init
->offset
+ 1);
1868 u32 dreg
= nv_ro32(bios
, init
->offset
+ 5);
1870 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg
, sreg
);
1873 init_wr32(init
, dreg
, init_rd32(init
, sreg
));
1877 * INIT_ZM_REG_GROUP - opcode 0x91
1881 init_zm_reg_group(struct nvbios_init
*init
)
1883 struct nouveau_bios
*bios
= init
->bios
;
1884 u32 addr
= nv_ro32(bios
, init
->offset
+ 1);
1885 u8 count
= nv_ro08(bios
, init
->offset
+ 5);
1887 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr
);
1891 u32 data
= nv_ro32(bios
, init
->offset
);
1892 trace("\t0x%08x\n", data
);
1893 init_wr32(init
, addr
, data
);
1899 * INIT_XLAT - opcode 0x96
1903 init_xlat(struct nvbios_init
*init
)
1905 struct nouveau_bios
*bios
= init
->bios
;
1906 u32 saddr
= nv_ro32(bios
, init
->offset
+ 1);
1907 u8 sshift
= nv_ro08(bios
, init
->offset
+ 5);
1908 u8 smask
= nv_ro08(bios
, init
->offset
+ 6);
1909 u8 index
= nv_ro08(bios
, init
->offset
+ 7);
1910 u32 daddr
= nv_ro32(bios
, init
->offset
+ 8);
1911 u32 dmask
= nv_ro32(bios
, init
->offset
+ 12);
1912 u8 shift
= nv_ro08(bios
, init
->offset
+ 16);
1915 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
1916 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
1917 daddr
, dmask
, index
, saddr
, (sshift
& 0x80) ? "<<" : ">>",
1918 (sshift
& 0x80) ? (0x100 - sshift
) : sshift
, smask
, shift
);
1921 data
= init_shift(init_rd32(init
, saddr
), sshift
) & smask
;
1922 data
= init_xlat_(init
, index
, data
) << shift
;
1923 init_mask(init
, daddr
, ~dmask
, data
);
1927 * INIT_ZM_MASK_ADD - opcode 0x97
1931 init_zm_mask_add(struct nvbios_init
*init
)
1933 struct nouveau_bios
*bios
= init
->bios
;
1934 u32 addr
= nv_ro32(bios
, init
->offset
+ 1);
1935 u32 mask
= nv_ro32(bios
, init
->offset
+ 5);
1936 u32 add
= nv_ro32(bios
, init
->offset
+ 9);
1939 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr
, mask
, add
);
1942 data
= init_rd32(init
, addr
);
1943 data
= (data
& mask
) | ((data
+ add
) & ~mask
);
1944 init_wr32(init
, addr
, data
);
1948 * INIT_AUXCH - opcode 0x98
1952 init_auxch(struct nvbios_init
*init
)
1954 struct nouveau_bios
*bios
= init
->bios
;
1955 u32 addr
= nv_ro32(bios
, init
->offset
+ 1);
1956 u8 count
= nv_ro08(bios
, init
->offset
+ 5);
1958 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr
, count
);
1962 u8 mask
= nv_ro08(bios
, init
->offset
+ 0);
1963 u8 data
= nv_ro08(bios
, init
->offset
+ 1);
1964 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr
, mask
, data
);
1965 mask
= init_rdauxr(init
, addr
) & mask
;
1966 init_wrauxr(init
, addr
, mask
| data
);
1972 * INIT_AUXCH - opcode 0x99
1976 init_zm_auxch(struct nvbios_init
*init
)
1978 struct nouveau_bios
*bios
= init
->bios
;
1979 u32 addr
= nv_ro32(bios
, init
->offset
+ 1);
1980 u8 count
= nv_ro08(bios
, init
->offset
+ 5);
1982 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr
, count
);
1986 u8 data
= nv_ro08(bios
, init
->offset
+ 0);
1987 trace("\tAUX[0x%08x] = 0x%02x\n", addr
, data
);
1988 init_wrauxr(init
, addr
, data
);
1994 * INIT_I2C_LONG_IF - opcode 0x9a
1998 init_i2c_long_if(struct nvbios_init
*init
)
2000 struct nouveau_bios
*bios
= init
->bios
;
2001 u8 index
= nv_ro08(bios
, init
->offset
+ 1);
2002 u8 addr
= nv_ro08(bios
, init
->offset
+ 2) >> 1;
2003 u8 reglo
= nv_ro08(bios
, init
->offset
+ 3);
2004 u8 reghi
= nv_ro08(bios
, init
->offset
+ 4);
2005 u8 mask
= nv_ro08(bios
, init
->offset
+ 5);
2006 u8 data
= nv_ro08(bios
, init
->offset
+ 6);
2007 struct nouveau_i2c_port
*port
;
2009 trace("I2C_LONG_IF\t"
2010 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
2011 index
, addr
, reglo
, reghi
, mask
, data
);
2014 port
= init_i2c(init
, index
);
2016 u8 i
[2] = { reghi
, reglo
};
2018 struct i2c_msg msg
[] = {
2019 { .addr
= addr
, .flags
= 0, .len
= 2, .buf
= i
},
2020 { .addr
= addr
, .flags
= I2C_M_RD
, .len
= 1, .buf
= o
}
2024 ret
= i2c_transfer(&port
->adapter
, msg
, 2);
2025 if (ret
== 2 && ((o
[0] & mask
) == data
))
2029 init_exec_set(init
, false);
2033 * INIT_GPIO_NE - opcode 0xa9
2037 init_gpio_ne(struct nvbios_init
*init
)
2039 struct nouveau_bios
*bios
= init
->bios
;
2040 struct nouveau_gpio
*gpio
= nouveau_gpio(bios
);
2041 struct dcb_gpio_func func
;
2042 u8 count
= nv_ro08(bios
, init
->offset
+ 1);
2043 u8 idx
= 0, ver
, len
;
2049 for (i
= init
->offset
; i
< init
->offset
+ count
; i
++)
2050 cont("0x%02x ", nv_ro08(bios
, i
));
2053 while ((data
= dcb_gpio_parse(bios
, 0, idx
++, &ver
, &len
, &func
))) {
2054 if (func
.func
!= DCB_GPIO_UNUSED
) {
2055 for (i
= init
->offset
; i
< init
->offset
+ count
; i
++) {
2056 if (func
.func
== nv_ro08(bios
, i
))
2060 trace("\tFUNC[0x%02x]", func
.func
);
2061 if (i
== (init
->offset
+ count
)) {
2063 if (init_exec(init
) && gpio
&& gpio
->reset
)
2064 gpio
->reset(gpio
, func
.func
);
2070 init
->offset
+= count
;
2073 static struct nvbios_init_opcode
{
2074 void (*exec
)(struct nvbios_init
*);
2076 [0x32] = { init_io_restrict_prog
},
2077 [0x33] = { init_repeat
},
2078 [0x34] = { init_io_restrict_pll
},
2079 [0x36] = { init_end_repeat
},
2080 [0x37] = { init_copy
},
2081 [0x38] = { init_not
},
2082 [0x39] = { init_io_flag_condition
},
2083 [0x3a] = { init_dp_condition
},
2084 [0x3b] = { init_io_mask_or
},
2085 [0x3c] = { init_io_or
},
2086 [0x49] = { init_idx_addr_latched
},
2087 [0x4a] = { init_io_restrict_pll2
},
2088 [0x4b] = { init_pll2
},
2089 [0x4c] = { init_i2c_byte
},
2090 [0x4d] = { init_zm_i2c_byte
},
2091 [0x4e] = { init_zm_i2c
},
2092 [0x4f] = { init_tmds
},
2093 [0x50] = { init_zm_tmds_group
},
2094 [0x51] = { init_cr_idx_adr_latch
},
2095 [0x52] = { init_cr
},
2096 [0x53] = { init_zm_cr
},
2097 [0x54] = { init_zm_cr_group
},
2098 [0x56] = { init_condition_time
},
2099 [0x57] = { init_ltime
},
2100 [0x58] = { init_zm_reg_sequence
},
2101 [0x5b] = { init_sub_direct
},
2102 [0x5c] = { init_jump
},
2103 [0x5e] = { init_i2c_if
},
2104 [0x5f] = { init_copy_nv_reg
},
2105 [0x62] = { init_zm_index_io
},
2106 [0x63] = { init_compute_mem
},
2107 [0x65] = { init_reset
},
2108 [0x66] = { init_configure_mem
},
2109 [0x67] = { init_configure_clk
},
2110 [0x68] = { init_configure_preinit
},
2111 [0x69] = { init_io
},
2112 [0x6b] = { init_sub
},
2113 [0x6d] = { init_ram_condition
},
2114 [0x6e] = { init_nv_reg
},
2115 [0x6f] = { init_macro
},
2116 [0x71] = { init_done
},
2117 [0x72] = { init_resume
},
2118 [0x74] = { init_time
},
2119 [0x75] = { init_condition
},
2120 [0x76] = { init_io_condition
},
2121 [0x78] = { init_index_io
},
2122 [0x79] = { init_pll
},
2123 [0x7a] = { init_zm_reg
},
2124 [0x87] = { init_ram_restrict_pll
},
2125 [0x8c] = { init_reserved
},
2126 [0x8d] = { init_reserved
},
2127 [0x8e] = { init_gpio
},
2128 [0x8f] = { init_ram_restrict_zm_reg_group
},
2129 [0x90] = { init_copy_zm_reg
},
2130 [0x91] = { init_zm_reg_group
},
2131 [0x92] = { init_reserved
},
2132 [0x96] = { init_xlat
},
2133 [0x97] = { init_zm_mask_add
},
2134 [0x98] = { init_auxch
},
2135 [0x99] = { init_zm_auxch
},
2136 [0x9a] = { init_i2c_long_if
},
2137 [0xa9] = { init_gpio_ne
},
2140 #define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
2143 nvbios_exec(struct nvbios_init
*init
)
2146 while (init
->offset
) {
2147 u8 opcode
= nv_ro08(init
->bios
, init
->offset
);
2148 if (opcode
>= init_opcode_nr
|| !init_opcode
[opcode
].exec
) {
2149 error("unknown opcode 0x%02x\n", opcode
);
2153 init_opcode
[opcode
].exec(init
);
2160 nvbios_init(struct nouveau_subdev
*subdev
, bool execute
)
2162 struct nouveau_bios
*bios
= nouveau_bios(subdev
);
2168 nv_info(bios
, "running init tables\n");
2169 while (!ret
&& (data
= (init_script(bios
, ++i
)))) {
2170 struct nvbios_init init
= {
2176 .execute
= execute
? 1 : 0,
2179 ret
= nvbios_exec(&init
);
2182 /* the vbios parser will run this right after the normal init
2183 * tables, whereas the binary driver appears to run it later.
2185 if (!ret
&& (data
= init_unknown_script(bios
))) {
2186 struct nvbios_init init
= {
2192 .execute
= execute
? 1 : 0,
2195 ret
= nvbios_exec(&init
);