drm/nouveau/pbus: add a PBUS subdev that hands IRQs to the right subdevs
[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / subdev / bus / nv04.c
1 /*
2 * Copyright 2012 Nouveau Community
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Martin Peres <martin.peres@labri.fr>
23 * Ben Skeggs
24 */
25
26 #include <subdev/bus.h>
27
28 struct nv04_bus_priv {
29 struct nouveau_bus base;
30 };
31
32 void
33 nv04_bus_intr(struct nouveau_subdev *subdev)
34 {
35 struct nouveau_bus *pbus = nouveau_bus(subdev);
36 u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
37
38 if (stat & 0x00000001) {
39 nv_error(pbus, "BUS ERROR\n");
40 stat &= ~0x00000001;
41 nv_wr32(pbus, 0x001100, 0x00000001);
42 }
43
44 if (stat & 0x00000110) {
45 subdev = nouveau_subdev(subdev, NVDEV_SUBDEV_GPIO);
46 if (subdev && subdev->intr)
47 subdev->intr(subdev);
48 stat &= ~0x00000110;
49 nv_wr32(pbus, 0x001100, 0x00000110);
50 }
51
52 if (stat) {
53 nv_error(pbus, "unknown intr 0x%08x\n", stat);
54 nv_mask(pbus, 0x001140, stat, 0x00000000);
55 }
56 }
57
58 static int
59 nv04_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
60 struct nouveau_oclass *oclass, void *data, u32 size,
61 struct nouveau_object **pobject)
62 {
63 struct nv04_bus_priv *priv;
64 int ret;
65
66 ret = nouveau_bus_create(parent, engine, oclass, &priv);
67 *pobject = nv_object(priv);
68 if (ret)
69 return ret;
70
71 nv_subdev(priv)->intr = nv04_bus_intr;
72 return 0;
73 }
74
75 static int
76 nv04_bus_init(struct nouveau_object *object)
77 {
78 struct nv04_bus_priv *priv = (void *)object;
79
80 nv_wr32(priv, 0x001100, 0xffffffff);
81 nv_wr32(priv, 0x001140, 0x00000111);
82
83 return nouveau_bus_init(&priv->base);
84 }
85
86 struct nouveau_oclass
87 nv04_bus_oclass = {
88 .handle = NV_SUBDEV(BUS, 0x04),
89 .ofuncs = &(struct nouveau_ofuncs) {
90 .ctor = nv04_bus_ctor,
91 .dtor = _nouveau_bus_dtor,
92 .init = nv04_bus_init,
93 .fini = _nouveau_bus_fini,
94 },
95 };
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