drivers/gpu/drm/nouveau/core/subdev/device/nv30.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <subdev/device.h>
  26 #include <subdev/bios.h>
  27 #include <subdev/gpio.h>
  28 #include <subdev/i2c.h>
  29 #include <subdev/clock.h>
  30 #include <subdev/devinit.h>
  31 #include <subdev/mc.h>
  32 #include <subdev/timer.h>
  33 #include <subdev/fb.h>
  34 #include <subdev/instmem.h>
  35 #include <subdev/vm.h>
  36
  37 #include <engine/dmaobj.h>
  38 #include <engine/fifo.h>
  39 #include <engine/software.h>
  40 #include <engine/graph.h>
  41 #include <engine/mpeg.h>
  42 #include <engine/disp.h>
  43
  44 int
  45 nv30_identify(struct nouveau_device *device)
  46 {
  47         switch (device->chipset) {
  48         case 0x30:
  49                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  50                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
  51                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  52                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
  53                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
  54                 device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
  55                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
  56                 device->oclass[NVDEV_SUBDEV_FB     ] = &nv30_fb_oclass;
  57                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
  58                 device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
  59                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
  60                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nv17_fifo_oclass;
  61                 device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
  62                 device->oclass[NVDEV_ENGINE_GR     ] = &nv30_graph_oclass;
  63                 device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
  64                 break;
  65         case 0x35:
  66                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  67                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
  68                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  69                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
  70                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
  71                 device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
  72                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
  73                 device->oclass[NVDEV_SUBDEV_FB     ] = &nv30_fb_oclass;
  74                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
  75                 device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
  76                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
  77                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nv17_fifo_oclass;
  78                 device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
  79                 device->oclass[NVDEV_ENGINE_GR     ] = &nv35_graph_oclass;
  80                 device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
  81                 break;
  82         case 0x31:
  83                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
  84                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
  85                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
  86                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
  87                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
  88                 device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
  89                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
  90                 device->oclass[NVDEV_SUBDEV_FB     ] = &nv30_fb_oclass;
  91                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
  92                 device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
  93                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
  94                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nv17_fifo_oclass;
  95                 device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
  96                 device->oclass[NVDEV_ENGINE_GR     ] = &nv30_graph_oclass;
  97                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
  98                 device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
  99                 break;
 100         case 0x36:
 101                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 102                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
 103                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
 104                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
 105                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
 106                 device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
 107                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 108                 device->oclass[NVDEV_SUBDEV_FB     ] = &nv30_fb_oclass;
 109                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
 110                 device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
 111                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
 112                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nv17_fifo_oclass;
 113                 device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
 114                 device->oclass[NVDEV_ENGINE_GR     ] = &nv35_graph_oclass;
 115                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
 116                 device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
 117                 break;
 118         case 0x34:
 119                 device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
 120                 device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
 121                 device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
 122                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
 123                 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
 124                 device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
 125                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
 126                 device->oclass[NVDEV_SUBDEV_FB     ] = &nv30_fb_oclass;
 127                 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
 128                 device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
 129                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
 130                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nv17_fifo_oclass;
 131                 device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
 132                 device->oclass[NVDEV_ENGINE_GR     ] = &nv34_graph_oclass;
 133                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
 134                 device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
 135                 break;
 136         default:
 137                 nv_fatal(device, "unknown Rankine chipset\n");
 138                 return -EINVAL;
 139         }
 140
 141         return 0;
 142 }