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drm/nouveau: port all engines to new engine module format
[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / subdev / device / nv40.c
1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <subdev/device.h>
26 #include <subdev/bios.h>
27 #include <subdev/gpio.h>
28 #include <subdev/i2c.h>
29 #include <subdev/clock.h>
30 #include <subdev/devinit.h>
31 #include <subdev/mc.h>
32 #include <subdev/timer.h>
33 #include <subdev/fb.h>
34 #include <subdev/instmem.h>
35 #include <subdev/vm.h>
36
37 #include <engine/dmaobj.h>
38 #include <engine/fifo.h>
39 #include <engine/software.h>
40 #include <engine/graph.h>
41 #include <engine/mpeg.h>
42 #include <engine/disp.h>
43
44 int
45 nv40_identify(struct nouveau_device *device)
46 {
47 switch (device->chipset) {
48 case 0x40:
49 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
50 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
51 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
52 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
53 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
54 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
55 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
56 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
57 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
58 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
59 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
60 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
61 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
62 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
63 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
64 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
65 break;
66 case 0x41:
67 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
68 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
69 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
70 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
71 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
72 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
73 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
74 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
75 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
76 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
77 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
78 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
79 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
80 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
81 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
82 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
83 break;
84 case 0x42:
85 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
86 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
87 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
88 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
89 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
90 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
91 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
92 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
93 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
94 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
95 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
96 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
97 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
98 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
99 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
100 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
101 break;
102 case 0x43:
103 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
104 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
105 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
106 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
107 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
108 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
109 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
110 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
111 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
112 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
113 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
114 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
115 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
116 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
117 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
118 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
119 break;
120 case 0x45:
121 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
122 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
123 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
124 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
125 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
126 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
127 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
128 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
129 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
130 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
131 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
132 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
133 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
134 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
135 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
136 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
137 break;
138 case 0x47:
139 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
140 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
141 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
142 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
143 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
144 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
145 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
146 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
147 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
148 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
149 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
150 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
151 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
152 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
153 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
154 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
155 break;
156 case 0x49:
157 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
158 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
159 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
160 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
161 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
162 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
163 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
164 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
165 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
166 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
167 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
168 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
169 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
170 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
171 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
172 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
173 break;
174 case 0x4b:
175 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
176 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
177 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
178 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
179 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
180 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
181 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
182 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
183 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
184 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
185 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
186 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
187 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
188 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
189 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
190 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
191 break;
192 case 0x44:
193 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
194 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
195 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
196 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
197 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
198 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
199 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
200 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
201 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
202 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
203 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
204 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
205 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
206 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
207 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
208 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
209 break;
210 case 0x46:
211 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
212 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
213 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
214 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
215 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
216 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
217 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
218 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
219 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
220 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
221 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
222 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
223 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
224 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
225 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
226 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
227 break;
228 case 0x4a:
229 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
230 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
231 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
232 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
233 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
234 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
235 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
236 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
237 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
238 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
239 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
240 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
241 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
242 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
243 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
244 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
245 break;
246 case 0x4c:
247 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
248 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
249 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
250 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
251 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
252 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
253 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
254 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
255 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
256 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
257 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
258 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
259 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
260 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
261 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
262 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
263 break;
264 case 0x4e:
265 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
266 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
267 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
268 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
269 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
270 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
271 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
272 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
273 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
274 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
275 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
276 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
277 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
278 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
279 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
280 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
281 break;
282 case 0x63:
283 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
284 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
285 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
286 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
287 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
288 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
289 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
290 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
291 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
292 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
293 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
294 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
295 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
296 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
297 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
298 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
299 break;
300 case 0x67:
301 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
302 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
303 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
304 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
305 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
306 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
307 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
308 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
309 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
310 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
311 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
312 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
313 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
314 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
315 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
316 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
317 break;
318 case 0x68:
319 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
320 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
321 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
322 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
323 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
324 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
325 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
326 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
327 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
328 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
329 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
330 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
331 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
332 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
333 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
334 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
335 break;
336 default:
337 nv_fatal(device, "unknown Curie chipset\n");
338 return -EINVAL;
339 }
340
341 return 0;
342 }
Linux kernel - Deliverables
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