drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c

   1 /*
   2  * Copyright 2013 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "nv50.h"
  26
  27 static int
  28 nvc0_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
  29 {
  30         struct nv50_devinit_priv *priv = (void *)devinit;
  31         struct nouveau_bios *bios = nouveau_bios(priv);
  32         struct nvbios_pll info;
  33         int N, fN, M, P;
  34         int ret;
  35
  36         ret = nvbios_pll_parse(bios, type, &info);
  37         if (ret)
  38                 return ret;
  39
  40         ret = nva3_pll_calc(nv_subdev(devinit), &info, freq, &N, &fN, &M, &P);
  41         if (ret < 0)
  42                 return ret;
  43
  44         switch (info.type) {
  45         case PLL_VPLL0:
  46         case PLL_VPLL1:
  47         case PLL_VPLL2:
  48         case PLL_VPLL3:
  49                 nv_mask(priv, info.reg + 0x0c, 0x00000000, 0x00000100);
  50                 nv_wr32(priv, info.reg + 0x04, (P << 16) | (N << 8) | M);
  51                 nv_wr32(priv, info.reg + 0x10, fN << 16);
  52                 break;
  53         default:
  54                 nv_warn(priv, "0x%08x/%dKhz unimplemented\n", type, freq);
  55                 ret = -EINVAL;
  56                 break;
  57         }
  58
  59         return ret;
  60 }
  61
  62 static int
  63 nvc0_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
  64                   struct nouveau_oclass *oclass, void *data, u32 size,
  65                   struct nouveau_object **pobject)
  66 {
  67         struct nv50_devinit_priv *priv;
  68         int ret;
  69
  70         ret = nouveau_devinit_create(parent, engine, oclass, &priv);
  71         *pobject = nv_object(priv);
  72         if (ret)
  73                 return ret;
  74
  75         if (nv_rd32(priv, 0x022500) & 0x00000001)
  76                 priv->base.post = true;
  77         return 0;
  78 }
  79
  80 struct nouveau_oclass *
  81 nvc0_devinit_oclass = &(struct nouveau_devinit_impl) {
  82         .base.handle = NV_SUBDEV(DEVINIT, 0xc0),
  83         .base.ofuncs = &(struct nouveau_ofuncs) {
  84                 .ctor = nvc0_devinit_ctor,
  85                 .dtor = _nouveau_devinit_dtor,
  86                 .init = nv50_devinit_init,
  87                 .fini = _nouveau_devinit_fini,
  88         },
  89         .pll_set = nvc0_devinit_pll_set,
  90 }.base;