2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #define AUX_DBG(fmt, args...) nv_debug(aux, "AUXCH(%d): " fmt, ch, ##args)
28 #define AUX_ERR(fmt, args...) nv_error(aux, "AUXCH(%d): " fmt, ch, ##args)
31 auxch_fini(struct nouveau_i2c
*aux
, int ch
)
33 nv_mask(aux
, 0x00e4e4 + (ch
* 0x50), 0x00310000, 0x00000000);
37 auxch_init(struct nouveau_i2c
*aux
, int ch
)
39 const u32 unksel
= 1; /* nfi which to use, or if it matters.. */
40 const u32 ureq
= unksel
? 0x00100000 : 0x00200000;
41 const u32 urep
= unksel
? 0x01000000 : 0x02000000;
44 /* wait up to 1ms for any previous transaction to be done... */
47 ctrl
= nv_rd32(aux
, 0x00e4e4 + (ch
* 0x50));
50 AUX_ERR("begin idle timeout 0x%08x\n", ctrl
);
53 } while (ctrl
& 0x03010000);
55 /* set some magic, and wait up to 1ms for it to appear */
56 nv_mask(aux
, 0x00e4e4 + (ch
* 0x50), 0x00300000, ureq
);
59 ctrl
= nv_rd32(aux
, 0x00e4e4 + (ch
* 0x50));
62 AUX_ERR("magic wait 0x%08x\n", ctrl
);
66 } while ((ctrl
& 0x03000000) != urep
);
72 nv94_aux(struct nouveau_i2c_port
*base
, bool retry
,
73 u8 type
, u32 addr
, u8
*data
, u8 size
)
75 struct nouveau_i2c
*aux
= nouveau_i2c(base
);
76 struct nv50_i2c_port
*port
= (void *)base
;
77 u32 ctrl
, stat
, timeout
, retries
;
82 AUX_DBG("%d: 0x%08x %d\n", type
, addr
, size
);
84 ret
= auxch_init(aux
, ch
);
88 stat
= nv_rd32(aux
, 0x00e4e8 + (ch
* 0x50));
89 if (!(stat
& 0x10000000)) {
90 AUX_DBG("sink not detected\n");
96 memcpy(xbuf
, data
, size
);
97 for (i
= 0; i
< 16; i
+= 4) {
98 AUX_DBG("wr 0x%08x\n", xbuf
[i
/ 4]);
99 nv_wr32(aux
, 0x00e4c0 + (ch
* 0x50) + i
, xbuf
[i
/ 4]);
103 ctrl
= nv_rd32(aux
, 0x00e4e4 + (ch
* 0x50));
107 nv_wr32(aux
, 0x00e4e0 + (ch
* 0x50), addr
);
109 /* (maybe) retry transaction a number of times on failure... */
110 for (retries
= 0; !ret
&& retries
< 32; retries
++) {
111 /* reset, and delay a while if this is a retry */
112 nv_wr32(aux
, 0x00e4e4 + (ch
* 0x50), 0x80000000 | ctrl
);
113 nv_wr32(aux
, 0x00e4e4 + (ch
* 0x50), 0x00000000 | ctrl
);
117 /* transaction request, wait up to 1ms for it to complete */
118 nv_wr32(aux
, 0x00e4e4 + (ch
* 0x50), 0x00010000 | ctrl
);
122 ctrl
= nv_rd32(aux
, 0x00e4e4 + (ch
* 0x50));
125 AUX_ERR("tx req timeout 0x%08x\n", ctrl
);
129 } while (ctrl
& 0x00010000);
132 /* read status, and check if transaction completed ok */
133 stat
= nv_mask(aux
, 0x00e4e8 + (ch
* 0x50), 0, 0);
134 if ((stat
& 0x000f0000) == 0x00080000 ||
135 (stat
& 0x000f0000) == 0x00020000)
137 if ((stat
& 0x00000100))
139 if ((stat
& 0x00000e00))
142 AUX_DBG("%02d 0x%08x 0x%08x\n", retries
, ctrl
, stat
);
146 for (i
= 0; i
< 16; i
+= 4) {
147 xbuf
[i
/ 4] = nv_rd32(aux
, 0x00e4d0 + (ch
* 0x50) + i
);
148 AUX_DBG("rd 0x%08x\n", xbuf
[i
/ 4]);
150 memcpy(data
, xbuf
, size
);
155 return ret
< 0 ? ret
: (stat
& 0x000f0000) >> 16;
159 nv94_i2c_acquire(struct nouveau_i2c_port
*base
)
161 struct nv50_i2c_priv
*priv
= (void *)nv_object(base
)->engine
;
162 struct nv50_i2c_port
*port
= (void *)base
;
164 nv_mask(priv
, port
->ctrl
+ 0x0c, 0x00000001, 0x00000000);
165 nv_mask(priv
, port
->ctrl
+ 0x00, 0x0000f003, port
->data
);
170 nv94_i2c_release(struct nouveau_i2c_port
*base
)
174 static const struct nouveau_i2c_func
176 .acquire
= nv94_i2c_acquire
,
177 .release
= nv94_i2c_release
,
178 .drive_scl
= nv50_i2c_drive_scl
,
179 .drive_sda
= nv50_i2c_drive_sda
,
180 .sense_scl
= nv50_i2c_sense_scl
,
181 .sense_sda
= nv50_i2c_sense_sda
,
185 nv94_i2c_port_ctor(struct nouveau_object
*parent
, struct nouveau_object
*engine
,
186 struct nouveau_oclass
*oclass
, void *data
, u32 index
,
187 struct nouveau_object
**pobject
)
189 struct dcb_i2c_entry
*info
= data
;
190 struct nv50_i2c_port
*port
;
193 ret
= nouveau_i2c_port_create(parent
, engine
, oclass
, index
,
194 &nouveau_i2c_bit_algo
, &nv94_i2c_func
,
196 *pobject
= nv_object(port
);
200 if (info
->drive
>= nv50_i2c_addr_nr
)
204 port
->addr
= nv50_i2c_addr
[info
->drive
];
205 if (info
->share
!= DCB_I2C_UNUSED
) {
206 port
->ctrl
= 0x00e500 + (info
->share
* 0x50);
207 port
->data
= 0x0000e001;
212 static const struct nouveau_i2c_func
214 .acquire
= nv94_i2c_acquire
,
215 .release
= nv94_i2c_release
,
220 nv94_aux_port_ctor(struct nouveau_object
*parent
, struct nouveau_object
*engine
,
221 struct nouveau_oclass
*oclass
, void *data
, u32 index
,
222 struct nouveau_object
**pobject
)
224 struct dcb_i2c_entry
*info
= data
;
225 struct nv50_i2c_port
*port
;
228 ret
= nouveau_i2c_port_create(parent
, engine
, oclass
, index
,
229 &nouveau_i2c_aux_algo
, &nv94_aux_func
,
231 *pobject
= nv_object(port
);
235 port
->addr
= info
->drive
;
236 if (info
->share
!= DCB_I2C_UNUSED
) {
237 port
->ctrl
= 0x00e500 + (info
->drive
* 0x50);
238 port
->data
= 0x00002002;
244 static struct nouveau_oclass
245 nv94_i2c_sclass
[] = {
246 { .handle
= NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT
),
247 .ofuncs
= &(struct nouveau_ofuncs
) {
248 .ctor
= nv94_i2c_port_ctor
,
249 .dtor
= _nouveau_i2c_port_dtor
,
250 .init
= nv50_i2c_port_init
,
251 .fini
= _nouveau_i2c_port_fini
,
254 { .handle
= NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX
),
255 .ofuncs
= &(struct nouveau_ofuncs
) {
256 .ctor
= nv94_aux_port_ctor
,
257 .dtor
= _nouveau_i2c_port_dtor
,
258 .init
= _nouveau_i2c_port_init
,
259 .fini
= _nouveau_i2c_port_fini
,
265 struct nouveau_oclass
*
266 nv94_i2c_oclass
= &(struct nouveau_i2c_impl
) {
267 .base
.handle
= NV_SUBDEV(I2C
, 0x94),
268 .base
.ofuncs
= &(struct nouveau_ofuncs
) {
269 .ctor
= _nouveau_i2c_ctor
,
270 .dtor
= _nouveau_i2c_dtor
,
271 .init
= _nouveau_i2c_init
,
272 .fini
= _nouveau_i2c_fini
,
274 .sclass
= nv94_i2c_sclass
,
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