drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <subdev/ibus.h>
  26
  27 struct nve0_ibus_priv {
  28         struct nouveau_ibus base;
  29 };
  30
  31 static void
  32 nve0_ibus_intr_hub(struct nve0_ibus_priv *priv, int i)
  33 {
  34         u32 addr = nv_rd32(priv, 0x122120 + (i * 0x0800));
  35         u32 data = nv_rd32(priv, 0x122124 + (i * 0x0800));
  36         u32 stat = nv_rd32(priv, 0x122128 + (i * 0x0800));
  37         nv_error(priv, "HUB%d: 0x%06x 0x%08x (0x%08x)\n", i, addr, data, stat);
  38         nv_mask(priv, 0x122128 + (i * 0x0800), 0x00000200, 0x00000000);
  39 }
  40
  41 static void
  42 nve0_ibus_intr_rop(struct nve0_ibus_priv *priv, int i)
  43 {
  44         u32 addr = nv_rd32(priv, 0x124120 + (i * 0x0800));
  45         u32 data = nv_rd32(priv, 0x124124 + (i * 0x0800));
  46         u32 stat = nv_rd32(priv, 0x124128 + (i * 0x0800));
  47         nv_error(priv, "ROP%d: 0x%06x 0x%08x (0x%08x)\n", i, addr, data, stat);
  48         nv_mask(priv, 0x124128 + (i * 0x0800), 0x00000200, 0x00000000);
  49 }
  50
  51 static void
  52 nve0_ibus_intr_gpc(struct nve0_ibus_priv *priv, int i)
  53 {
  54         u32 addr = nv_rd32(priv, 0x128120 + (i * 0x0800));
  55         u32 data = nv_rd32(priv, 0x128124 + (i * 0x0800));
  56         u32 stat = nv_rd32(priv, 0x128128 + (i * 0x0800));
  57         nv_error(priv, "GPC%d: 0x%06x 0x%08x (0x%08x)\n", i, addr, data, stat);
  58         nv_mask(priv, 0x128128 + (i * 0x0800), 0x00000200, 0x00000000);
  59 }
  60
  61 static void
  62 nve0_ibus_intr(struct nouveau_subdev *subdev)
  63 {
  64         struct nve0_ibus_priv *priv = (void *)subdev;
  65         u32 intr0 = nv_rd32(priv, 0x120058);
  66         u32 intr1 = nv_rd32(priv, 0x12005c);
  67         u32 hubnr = nv_rd32(priv, 0x120070);
  68         u32 ropnr = nv_rd32(priv, 0x120074);
  69         u32 gpcnr = nv_rd32(priv, 0x120078);
  70         u32 i;
  71
  72         for (i = 0; (intr0 & 0x0000ff00) && i < hubnr; i++) {
  73                 u32 stat = 0x00000100 << i;
  74                 if (intr0 & stat) {
  75                         nve0_ibus_intr_hub(priv, i);
  76                         intr0 &= ~stat;
  77                 }
  78         }
  79
  80         for (i = 0; (intr0 & 0xffff0000) && i < ropnr; i++) {
  81                 u32 stat = 0x00010000 << i;
  82                 if (intr0 & stat) {
  83                         nve0_ibus_intr_rop(priv, i);
  84                         intr0 &= ~stat;
  85                 }
  86         }
  87
  88         for (i = 0; intr1 && i < gpcnr; i++) {
  89                 u32 stat = 0x00000001 << i;
  90                 if (intr1 & stat) {
  91                         nve0_ibus_intr_gpc(priv, i);
  92                         intr1 &= ~stat;
  93                 }
  94         }
  95 }
  96
  97 static int
  98 nve0_ibus_init(struct nouveau_object *object)
  99 {
 100         struct nve0_ibus_priv *priv = (void *)object;
 101         int ret = nouveau_ibus_init(&priv->base);
 102         if (ret == 0) {
 103                 nv_mask(priv, 0x122318, 0x0003ffff, 0x00001000);
 104                 nv_mask(priv, 0x12231c, 0x0003ffff, 0x00000200);
 105                 nv_mask(priv, 0x122310, 0x0003ffff, 0x00000800);
 106                 nv_mask(priv, 0x122348, 0x0003ffff, 0x00000100);
 107                 nv_mask(priv, 0x1223b0, 0x0003ffff, 0x00000fff);
 108                 nv_mask(priv, 0x122348, 0x0003ffff, 0x00000200);
 109                 nv_mask(priv, 0x122358, 0x0003ffff, 0x00002880);
 110         }
 111         return ret;
 112 }
 113
 114 static int
 115 nve0_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 116                struct nouveau_oclass *oclass, void *data, u32 size,
 117                struct nouveau_object **pobject)
 118 {
 119         struct nve0_ibus_priv *priv;
 120         int ret;
 121
 122         ret = nouveau_ibus_create(parent, engine, oclass, &priv);
 123         *pobject = nv_object(priv);
 124         if (ret)
 125                 return ret;
 126
 127         nv_subdev(priv)->intr = nve0_ibus_intr;
 128         return 0;
 129 }
 130
 131 struct nouveau_oclass
 132 nve0_ibus_oclass = {
 133         .handle = NV_SUBDEV(IBUS, 0xe0),
 134         .ofuncs = &(struct nouveau_ofuncs) {
 135                 .ctor = nve0_ibus_ctor,
 136                 .dtor = _nouveau_ibus_dtor,
 137                 .init = nve0_ibus_init,
 138                 .fini = _nouveau_ibus_fini,
 139         },
 140 };