drivers/gpu/drm/nouveau/core/subdev/therm/nv40.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *          Martin Peres
  24  */
  25
  26 #include "priv.h"
  27
  28 struct nv40_therm_priv {
  29         struct nouveau_therm_priv base;
  30 };
  31
  32 static int
  33 nv40_sensor_setup(struct nouveau_therm *therm)
  34 {
  35         struct nouveau_device *device = nv_device(therm);
  36
  37         /* enable ADC readout and disable the ALARM threshold */
  38         if (device->chipset >= 0x46) {
  39                 nv_mask(therm, 0x15b8, 0x80000000, 0);
  40                 nv_wr32(therm, 0x15b0, 0x80003fff);
  41                 return nv_rd32(therm, 0x15b4) & 0x3fff;
  42         } else {
  43                 nv_wr32(therm, 0x15b0, 0xff);
  44                 return nv_rd32(therm, 0x15b4) & 0xff;
  45         }
  46 }
  47
  48 static int
  49 nv40_temp_get(struct nouveau_therm *therm)
  50 {
  51         struct nouveau_therm_priv *priv = (void *)therm;
  52         struct nouveau_device *device = nv_device(therm);
  53         struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
  54         int core_temp;
  55
  56         if (device->chipset >= 0x46) {
  57                 nv_wr32(therm, 0x15b0, 0x80003fff);
  58                 core_temp = nv_rd32(therm, 0x15b4) & 0x3fff;
  59         } else {
  60                 nv_wr32(therm, 0x15b0, 0xff);
  61                 core_temp = nv_rd32(therm, 0x15b4) & 0xff;
  62         }
  63
  64         /* Setup the sensor if the temperature is 0 */
  65         if (core_temp == 0)
  66                 core_temp = nv40_sensor_setup(therm);
  67
  68         if (sensor->slope_div == 0)
  69                 sensor->slope_div = 1;
  70         if (sensor->offset_den == 0)
  71                 sensor->offset_den = 1;
  72         if (sensor->slope_mult < 1)
  73                 sensor->slope_mult = 1;
  74
  75         core_temp = core_temp * sensor->slope_mult / sensor->slope_div;
  76         core_temp = core_temp + sensor->offset_num / sensor->offset_den;
  77         core_temp = core_temp + sensor->offset_constant - 8;
  78
  79         return core_temp;
  80 }
  81
  82 int
  83 nv40_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable)
  84 {
  85         u32 mask = enable ? 0x80000000 : 0x0000000;
  86         if      (line == 2) nv_mask(therm, 0x0010f0, 0x80000000, mask);
  87         else if (line == 9) nv_mask(therm, 0x0015f4, 0x80000000, mask);
  88         else {
  89                 nv_error(therm, "unknown pwm ctrl for gpio %d\n", line);
  90                 return -ENODEV;
  91         }
  92         return 0;
  93 }
  94
  95 int
  96 nv40_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty)
  97 {
  98         if (line == 2) {
  99                 u32 reg = nv_rd32(therm, 0x0010f0);
 100                 if (reg & 0x80000000) {
 101                         *duty = (reg & 0x7fff0000) >> 16;
 102                         *divs = (reg & 0x00007fff);
 103                         return 0;
 104                 }
 105         } else
 106         if (line == 9) {
 107                 u32 reg = nv_rd32(therm, 0x0015f4);
 108                 if (reg & 0x80000000) {
 109                         *divs = nv_rd32(therm, 0x0015f8);
 110                         *duty = (reg & 0x7fffffff);
 111                         return 0;
 112                 }
 113         } else {
 114                 nv_error(therm, "unknown pwm ctrl for gpio %d\n", line);
 115                 return -ENODEV;
 116         }
 117
 118         return -EINVAL;
 119 }
 120
 121 int
 122 nv40_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty)
 123 {
 124         if (line == 2) {
 125                 nv_mask(therm, 0x0010f0, 0x7fff7fff, (duty << 16) | divs);
 126         } else
 127         if (line == 9) {
 128                 nv_wr32(therm, 0x0015f8, divs);
 129                 nv_mask(therm, 0x0015f4, 0x7fffffff, duty);
 130         } else {
 131                 nv_error(therm, "unknown pwm ctrl for gpio %d\n", line);
 132                 return -ENODEV;
 133         }
 134
 135         return 0;
 136 }
 137
 138 static int
 139 nv40_therm_ctor(struct nouveau_object *parent,
 140                 struct nouveau_object *engine,
 141                 struct nouveau_oclass *oclass, void *data, u32 size,
 142                 struct nouveau_object **pobject)
 143 {
 144         struct nv40_therm_priv *priv;
 145         int ret;
 146
 147         ret = nouveau_therm_create(parent, engine, oclass, &priv);
 148         *pobject = nv_object(priv);
 149         if (ret)
 150                 return ret;
 151
 152         priv->base.base.pwm_ctrl = nv40_fan_pwm_ctrl;
 153         priv->base.base.pwm_get = nv40_fan_pwm_get;
 154         priv->base.base.pwm_set = nv40_fan_pwm_set;
 155         priv->base.base.temp_get = nv40_temp_get;
 156         return nouveau_therm_preinit(&priv->base.base);
 157 }
 158
 159 struct nouveau_oclass
 160 nv40_therm_oclass = {
 161         .handle = NV_SUBDEV(THERM, 0x40),
 162         .ofuncs = &(struct nouveau_ofuncs) {
 163                 .ctor = nv40_therm_ctor,
 164                 .dtor = _nouveau_therm_dtor,
 165                 .init = _nouveau_therm_init,
 166                 .fini = _nouveau_therm_fini,
 167         },
 168 };