drivers/gpu/drm/nouveau/core/subdev/therm/nv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *          Martin Peres
  24  */
  25
  26 #include "priv.h"
  27
  28 struct nv50_therm_priv {
  29         struct nouveau_therm_priv base;
  30 };
  31
  32 static int
  33 pwm_info(struct nouveau_therm *therm, int *line, int *ctrl, int *indx)
  34 {
  35         if (*line == 0x04) {
  36                 *ctrl = 0x00e100;
  37                 *line = 4;
  38                 *indx = 0;
  39         } else
  40         if (*line == 0x09) {
  41                 *ctrl = 0x00e100;
  42                 *line = 9;
  43                 *indx = 1;
  44         } else
  45         if (*line == 0x10) {
  46                 *ctrl = 0x00e28c;
  47                 *line = 0;
  48                 *indx = 0;
  49         } else {
  50                 nv_error(therm, "unknown pwm ctrl for gpio %d\n", *line);
  51                 return -ENODEV;
  52         }
  53
  54         return 0;
  55 }
  56
  57 int
  58 nv50_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable)
  59 {
  60         u32 data = enable ? 0x00000001 : 0x00000000;
  61         int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id);
  62         if (ret == 0)
  63                 nv_mask(therm, ctrl, 0x00010001 << line, data << line);
  64         return ret;
  65 }
  66
  67 int
  68 nv50_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty)
  69 {
  70         int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id);
  71         if (ret)
  72                 return ret;
  73
  74         if (nv_rd32(therm, ctrl) & (1 << line)) {
  75                 *divs = nv_rd32(therm, 0x00e114 + (id * 8));
  76                 *duty = nv_rd32(therm, 0x00e118 + (id * 8));
  77                 return 0;
  78         }
  79
  80         return -EINVAL;
  81 }
  82
  83 int
  84 nv50_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty)
  85 {
  86         int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id);
  87         if (ret)
  88                 return ret;
  89
  90         nv_wr32(therm, 0x00e114 + (id * 8), divs);
  91         nv_wr32(therm, 0x00e118 + (id * 8), duty | 0x80000000);
  92         return 0;
  93 }
  94
  95 int
  96 nv50_fan_pwm_clock(struct nouveau_therm *therm)
  97 {
  98         int chipset = nv_device(therm)->chipset;
  99         int crystal = nv_device(therm)->crystal;
 100         int pwm_clock;
 101
 102         /* determine the PWM source clock */
 103         if (chipset > 0x50 && chipset < 0x94) {
 104                 u8 pwm_div = nv_rd32(therm, 0x410c);
 105                 if (nv_rd32(therm, 0xc040) & 0x800000) {
 106                         /* Use the HOST clock (100 MHz)
 107                         * Where does this constant(2.4) comes from? */
 108                         pwm_clock = (100000000 >> pwm_div) * 10 / 24;
 109                 } else {
 110                         /* Where does this constant(20) comes from? */
 111                         pwm_clock = (crystal * 1000) >> pwm_div;
 112                         pwm_clock /= 20;
 113                 }
 114         } else {
 115                 pwm_clock = (crystal * 1000) / 20;
 116         }
 117
 118         return pwm_clock;
 119 }
 120
 121 int
 122 nv50_temp_get(struct nouveau_therm *therm)
 123 {
 124         return nv_rd32(therm, 0x20400);
 125 }
 126
 127 static void
 128 nv50_therm_program_alarms(struct nouveau_therm *therm)
 129 {
 130         struct nouveau_therm_priv *priv = (void *)therm;
 131         struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
 132         unsigned long flags;
 133
 134         spin_lock_irqsave(&priv->sensor.alarm_program_lock, flags);
 135
 136         /* enable RISING and FALLING IRQs for shutdown, THRS 0, 1, 2 and 4 */
 137         nv_wr32(therm, 0x20000, 0x000003ff);
 138
 139         /* shutdown: The computer should be shutdown when reached */
 140         nv_wr32(therm, 0x20484, sensor->thrs_shutdown.hysteresis);
 141         nv_wr32(therm, 0x20480, sensor->thrs_shutdown.temp);
 142
 143         /* THRS_1 : fan boost*/
 144         nv_wr32(therm, 0x204c4, sensor->thrs_fan_boost.temp);
 145
 146         /* THRS_2 : critical */
 147         nv_wr32(therm, 0x204c0, sensor->thrs_critical.temp);
 148
 149         /* THRS_4 : down clock */
 150         nv_wr32(therm, 0x20414, sensor->thrs_down_clock.temp);
 151         spin_unlock_irqrestore(&priv->sensor.alarm_program_lock, flags);
 152
 153         nv_info(therm,
 154                 "Programmed thresholds [ %d(%d), %d(%d), %d(%d), %d(%d) ]\n",
 155                 sensor->thrs_fan_boost.temp, sensor->thrs_fan_boost.hysteresis,
 156                 sensor->thrs_down_clock.temp,
 157                 sensor->thrs_down_clock.hysteresis,
 158                 sensor->thrs_critical.temp, sensor->thrs_critical.hysteresis,
 159                 sensor->thrs_shutdown.temp, sensor->thrs_shutdown.hysteresis);
 160
 161 }
 162
 163 /* must be called with alarm_program_lock taken ! */
 164 static void
 165 nv50_therm_threshold_hyst_emulation(struct nouveau_therm *therm,
 166                                    uint32_t thrs_reg, u8 status_bit,
 167                                    const struct nvbios_therm_threshold *thrs,
 168                                    enum nouveau_therm_thrs thrs_name)
 169 {
 170         enum nouveau_therm_thrs_direction direction;
 171         enum nouveau_therm_thrs_state prev_state, new_state;
 172         int temp, cur;
 173
 174         prev_state = nouveau_therm_sensor_get_threshold_state(therm, thrs_name);
 175         temp = nv_rd32(therm, thrs_reg);
 176
 177         /* program the next threshold */
 178         if (temp == thrs->temp) {
 179                 nv_wr32(therm, thrs_reg, thrs->temp - thrs->hysteresis);
 180                 new_state = NOUVEAU_THERM_THRS_HIGHER;
 181         } else {
 182                 nv_wr32(therm, thrs_reg, thrs->temp);
 183                 new_state = NOUVEAU_THERM_THRS_LOWER;
 184         }
 185
 186         /* fix the state (in case someone reprogrammed the alarms) */
 187         cur = therm->temp_get(therm);
 188         if (new_state == NOUVEAU_THERM_THRS_LOWER && cur > thrs->temp)
 189                 new_state = NOUVEAU_THERM_THRS_HIGHER;
 190         else if (new_state == NOUVEAU_THERM_THRS_HIGHER &&
 191                 cur < thrs->temp - thrs->hysteresis)
 192                 new_state = NOUVEAU_THERM_THRS_LOWER;
 193         nouveau_therm_sensor_set_threshold_state(therm, thrs_name, new_state);
 194
 195         /* find the direction */
 196         if (prev_state < new_state)
 197                 direction = NOUVEAU_THERM_THRS_RISING;
 198         else if (prev_state > new_state)
 199                 direction = NOUVEAU_THERM_THRS_FALLING;
 200         else
 201                 return;
 202
 203         /* advertise a change in direction */
 204         nouveau_therm_sensor_event(therm, thrs_name, direction);
 205 }
 206
 207 static void
 208 nv50_therm_intr(struct nouveau_subdev *subdev)
 209 {
 210         struct nouveau_therm *therm = nouveau_therm(subdev);
 211         struct nouveau_therm_priv *priv = (void *)therm;
 212         struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
 213         unsigned long flags;
 214         uint32_t intr;
 215
 216         spin_lock_irqsave(&priv->sensor.alarm_program_lock, flags);
 217
 218         intr = nv_rd32(therm, 0x20100);
 219
 220         /* THRS_4: downclock */
 221         if (intr & 0x002) {
 222                 nv50_therm_threshold_hyst_emulation(therm, 0x20414, 24,
 223                                                   &sensor->thrs_down_clock,
 224                                                   NOUVEAU_THERM_THRS_DOWNCLOCK);
 225                 intr &= ~0x002;
 226         }
 227
 228         /* shutdown */
 229         if (intr & 0x004) {
 230                 nv50_therm_threshold_hyst_emulation(therm, 0x20480, 20,
 231                                                    &sensor->thrs_shutdown,
 232                                                    NOUVEAU_THERM_THRS_SHUTDOWN);
 233                 intr &= ~0x004;
 234         }
 235
 236         /* THRS_1 : fan boost */
 237         if (intr & 0x008) {
 238                 nv50_therm_threshold_hyst_emulation(therm, 0x204c4, 21,
 239                                                    &sensor->thrs_fan_boost,
 240                                                    NOUVEAU_THERM_THRS_FANBOOST);
 241                 intr &= ~0x008;
 242         }
 243
 244         /* THRS_2 : critical */
 245         if (intr & 0x010) {
 246                 nv50_therm_threshold_hyst_emulation(therm, 0x204c0, 22,
 247                                                    &sensor->thrs_critical,
 248                                                    NOUVEAU_THERM_THRS_CRITICAL);
 249                 intr &= ~0x010;
 250         }
 251
 252         if (intr)
 253                 nv_error(therm, "unhandled intr 0x%08x\n", intr);
 254
 255         /* ACK everything */
 256         nv_wr32(therm, 0x20100, 0xffffffff);
 257         nv_wr32(therm, 0x1100, 0x10000); /* PBUS */
 258
 259         spin_unlock_irqrestore(&priv->sensor.alarm_program_lock, flags);
 260 }
 261
 262 static int
 263 nv50_therm_ctor(struct nouveau_object *parent,
 264                 struct nouveau_object *engine,
 265                 struct nouveau_oclass *oclass, void *data, u32 size,
 266                 struct nouveau_object **pobject)
 267 {
 268         struct nv50_therm_priv *priv;
 269         int ret;
 270
 271         ret = nouveau_therm_create(parent, engine, oclass, &priv);
 272         *pobject = nv_object(priv);
 273         if (ret)
 274                 return ret;
 275
 276         priv->base.base.pwm_ctrl = nv50_fan_pwm_ctrl;
 277         priv->base.base.pwm_get = nv50_fan_pwm_get;
 278         priv->base.base.pwm_set = nv50_fan_pwm_set;
 279         priv->base.base.pwm_clock = nv50_fan_pwm_clock;
 280         priv->base.base.temp_get = nv50_temp_get;
 281         priv->base.sensor.program_alarms = nv50_therm_program_alarms;
 282         nv_subdev(priv)->intr = nv50_therm_intr;
 283
 284         /* init the thresholds */
 285         nouveau_therm_sensor_set_threshold_state(&priv->base.base,
 286                                                  NOUVEAU_THERM_THRS_SHUTDOWN,
 287                                                  NOUVEAU_THERM_THRS_LOWER);
 288         nouveau_therm_sensor_set_threshold_state(&priv->base.base,
 289                                                  NOUVEAU_THERM_THRS_FANBOOST,
 290                                                  NOUVEAU_THERM_THRS_LOWER);
 291         nouveau_therm_sensor_set_threshold_state(&priv->base.base,
 292                                                  NOUVEAU_THERM_THRS_CRITICAL,
 293                                                  NOUVEAU_THERM_THRS_LOWER);
 294         nouveau_therm_sensor_set_threshold_state(&priv->base.base,
 295                                                  NOUVEAU_THERM_THRS_DOWNCLOCK,
 296                                                  NOUVEAU_THERM_THRS_LOWER);
 297
 298         return nouveau_therm_preinit(&priv->base.base);
 299 }
 300
 301 struct nouveau_oclass
 302 nv50_therm_oclass = {
 303         .handle = NV_SUBDEV(THERM, 0x50),
 304         .ofuncs = &(struct nouveau_ofuncs) {
 305                 .ctor = nv50_therm_ctor,
 306                 .dtor = _nouveau_therm_dtor,
 307                 .init = _nouveau_therm_init,
 308                 .fini = _nouveau_therm_fini,
 309         },
 310 };