drivers/gpu/drm/nouveau/core/subdev/therm/nvd0.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "priv.h"
  26
  27 struct nvd0_therm_priv {
  28         struct nouveau_therm_priv base;
  29 };
  30
  31 static int
  32 pwm_info(struct nouveau_therm *therm, int line)
  33 {
  34         u32 gpio = nv_rd32(therm, 0x00d610 + (line * 0x04));
  35         switch (gpio & 0x000000c0) {
  36         case 0x00000000: /* normal mode, possibly pwm forced off by us */
  37         case 0x00000040: /* nvio special */
  38                 switch (gpio & 0x0000001f) {
  39                 case 0x19: return 1;
  40                 case 0x1c: return 0;
  41                 default:
  42                         break;
  43                 }
  44         default:
  45                 break;
  46         }
  47
  48         nv_error(therm, "GPIO %d unknown PWM: 0x%08x\n", line, gpio);
  49         return -ENODEV;
  50 }
  51
  52 static int
  53 nvd0_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable)
  54 {
  55         u32 data = enable ? 0x00000040 : 0x00000000;
  56         int indx = pwm_info(therm, line);
  57         if (indx < 0)
  58                 return indx;
  59
  60         nv_mask(therm, 0x00d610 + (line * 0x04), 0x000000c0, data);
  61         return 0;
  62 }
  63
  64 static int
  65 nvd0_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty)
  66 {
  67         int indx = pwm_info(therm, line);
  68         if (indx < 0)
  69                 return indx;
  70
  71         if (nv_rd32(therm, 0x00d610 + (line * 0x04)) & 0x00000040) {
  72                 *divs = nv_rd32(therm, 0x00e114 + (indx * 8));
  73                 *duty = nv_rd32(therm, 0x00e118 + (indx * 8));
  74                 return 0;
  75         }
  76
  77         return -EINVAL;
  78 }
  79
  80 static int
  81 nvd0_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty)
  82 {
  83         int indx = pwm_info(therm, line);
  84         if (indx < 0)
  85                 return indx;
  86
  87         nv_wr32(therm, 0x00e114 + (indx * 8), divs);
  88         nv_wr32(therm, 0x00e118 + (indx * 8), duty | 0x80000000);
  89         return 0;
  90 }
  91
  92 static int
  93 nvd0_fan_pwm_clock(struct nouveau_therm *therm)
  94 {
  95         return (nv_device(therm)->crystal * 1000) / 20;
  96 }
  97
  98 static int
  99 nvd0_therm_init(struct nouveau_object *object)
 100 {
 101         struct nvd0_therm_priv *priv = (void *)object;
 102         int ret;
 103
 104         ret = nouveau_therm_init(&priv->base.base);
 105         if (ret)
 106                 return ret;
 107
 108         /* enable fan tach, count revolutions per-second */
 109         nv_mask(priv, 0x00e720, 0x00000003, 0x00000002);
 110         if (priv->base.fan->tach.func != DCB_GPIO_UNUSED) {
 111                 nv_mask(priv, 0x00d79c, 0x000000ff, priv->base.fan->tach.line);
 112                 nv_wr32(priv, 0x00e724, nv_device(priv)->crystal * 1000);
 113                 nv_mask(priv, 0x00e720, 0x00000001, 0x00000001);
 114         }
 115         nv_mask(priv, 0x00e720, 0x00000002, 0x00000000);
 116
 117         return 0;
 118 }
 119
 120 static int
 121 nvd0_therm_ctor(struct nouveau_object *parent,
 122                 struct nouveau_object *engine,
 123                 struct nouveau_oclass *oclass, void *data, u32 size,
 124                 struct nouveau_object **pobject)
 125 {
 126         struct nvd0_therm_priv *priv;
 127         int ret;
 128
 129         ret = nouveau_therm_create(parent, engine, oclass, &priv);
 130         *pobject = nv_object(priv);
 131         if (ret)
 132                 return ret;
 133
 134         priv->base.base.pwm_ctrl = nvd0_fan_pwm_ctrl;
 135         priv->base.base.pwm_get = nvd0_fan_pwm_get;
 136         priv->base.base.pwm_set = nvd0_fan_pwm_set;
 137         priv->base.base.pwm_clock = nvd0_fan_pwm_clock;
 138         priv->base.base.temp_get = nv50_temp_get;
 139         priv->base.base.fan_sense = nva3_therm_fan_sense;
 140         return nouveau_therm_preinit(&priv->base.base);
 141 }
 142
 143 struct nouveau_oclass
 144 nvd0_therm_oclass = {
 145         .handle = NV_SUBDEV(THERM, 0xd0),
 146         .ofuncs = &(struct nouveau_ofuncs) {
 147                 .ctor = nvd0_therm_ctor,
 148                 .dtor = _nouveau_therm_dtor,
 149                 .init = nvd0_therm_init,
 150                 .fini = _nouveau_therm_fini,
 151         },
 152 };