drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/gpuobj.h>
  26
  27 #include <subdev/timer.h>
  28 #include <subdev/vm.h>
  29
  30 #include "nv04.h"
  31
  32 #define NV44_GART_SIZE (512 * 1024 * 1024)
  33 #define NV44_GART_PAGE (  4 * 1024)
  34
  35 /*******************************************************************************
  36  * VM map/unmap callbacks
  37  ******************************************************************************/
  38
  39 static void
  40 nv44_vm_flush_priv(struct nv04_vmmgr_priv *priv, u32 base, u32 size)
  41 {
  42         nv_wr32(priv, 0x100814, (size - 1) << 12);
  43         nv_wr32(priv, 0x100808, base | 0x20);
  44         if (!nv_wait(priv, 0x100808, 0x00000001, 0x00000001))
  45                 nv_error(priv, "timeout: 0x%08x\n", nv_rd32(priv, 0x100808));
  46         nv_wr32(priv, 0x100808, 0x00000000);
  47 }
  48
  49 static void
  50 nv44_vm_fill(struct nouveau_gpuobj *pgt, dma_addr_t null,
  51              dma_addr_t *list, u32 pte, u32 cnt)
  52 {
  53         u32 base = (pte << 2) & ~0x0000000f;
  54         u32 tmp[4];
  55
  56         tmp[0] = nv_ro32(pgt, base + 0x0);
  57         tmp[1] = nv_ro32(pgt, base + 0x4);
  58         tmp[2] = nv_ro32(pgt, base + 0x8);
  59         tmp[3] = nv_ro32(pgt, base + 0xc);
  60         while (cnt--) {
  61                 u32 addr = list ? (*list++ >> 12) : (null >> 12);
  62                 switch (pte++ & 0x3) {
  63                 case 0:
  64                         tmp[0] &= ~0x07ffffff;
  65                         tmp[0] |= addr;
  66                         break;
  67                 case 1:
  68                         tmp[0] &= ~0xf8000000;
  69                         tmp[0] |= addr << 27;
  70                         tmp[1] &= ~0x003fffff;
  71                         tmp[1] |= addr >> 5;
  72                         break;
  73                 case 2:
  74                         tmp[1] &= ~0xffc00000;
  75                         tmp[1] |= addr << 22;
  76                         tmp[2] &= ~0x0001ffff;
  77                         tmp[2] |= addr >> 10;
  78                         break;
  79                 case 3:
  80                         tmp[2] &= ~0xfffe0000;
  81                         tmp[2] |= addr << 17;
  82                         tmp[3] &= ~0x00000fff;
  83                         tmp[3] |= addr >> 15;
  84                         break;
  85                 }
  86         }
  87
  88         nv_wo32(pgt, base + 0x0, tmp[0]);
  89         nv_wo32(pgt, base + 0x4, tmp[1]);
  90         nv_wo32(pgt, base + 0x8, tmp[2]);
  91         nv_wo32(pgt, base + 0xc, tmp[3] | 0x40000000);
  92 }
  93
  94 static void
  95 nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
  96                struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
  97 {
  98         struct nv04_vmmgr_priv *priv = (void *)vma->vm->vmm;
  99         u32 base = pte << 12;
 100         u32 size = cnt;
 101         u32 tmp[4];
 102         int i;
 103
 104         if (pte & 3) {
 105                 u32  max = 4 - (pte & 3);
 106                 u32 part = (cnt > max) ? max : cnt;
 107                 nv44_vm_fill(pgt, priv->null, list, pte, part);
 108                 pte  += part;
 109                 list += part;
 110                 cnt  -= part;
 111         }
 112
 113         while (cnt >= 4) {
 114                 for (i = 0; i < 4; i++)
 115                         tmp[i] = *list++ >> 12;
 116                 nv_wo32(pgt, pte++ * 4, tmp[0] >>  0 | tmp[1] << 27);
 117                 nv_wo32(pgt, pte++ * 4, tmp[1] >>  5 | tmp[2] << 22);
 118                 nv_wo32(pgt, pte++ * 4, tmp[2] >> 10 | tmp[3] << 17);
 119                 nv_wo32(pgt, pte++ * 4, tmp[3] >> 15 | 0x40000000);
 120                 cnt -= 4;
 121         }
 122
 123         if (cnt)
 124                 nv44_vm_fill(pgt, priv->null, list, pte, cnt);
 125         nv44_vm_flush_priv(priv, base, size);
 126 }
 127
 128 static void
 129 nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
 130 {
 131         struct nv04_vmmgr_priv *priv = (void *)nouveau_vmmgr(pgt);
 132         u32 base = pte << 12;
 133         u32 size = cnt;
 134
 135         if (pte & 3) {
 136                 u32  max = 4 - (pte & 3);
 137                 u32 part = (cnt > max) ? max : cnt;
 138                 nv44_vm_fill(pgt, priv->null, NULL, pte, part);
 139                 pte  += part;
 140                 cnt  -= part;
 141         }
 142
 143         while (cnt >= 4) {
 144                 nv_wo32(pgt, pte++ * 4, 0x00000000);
 145                 nv_wo32(pgt, pte++ * 4, 0x00000000);
 146                 nv_wo32(pgt, pte++ * 4, 0x00000000);
 147                 nv_wo32(pgt, pte++ * 4, 0x00000000);
 148                 cnt -= 4;
 149         }
 150
 151         if (cnt)
 152                 nv44_vm_fill(pgt, priv->null, NULL, pte, cnt);
 153         nv44_vm_flush_priv(priv, base, size);
 154 }
 155
 156 static void
 157 nv44_vm_flush(struct nouveau_vm *vm)
 158 {
 159 }
 160
 161 /*******************************************************************************
 162  * VMMGR subdev
 163  ******************************************************************************/
 164
 165 static int
 166 nv44_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 167                 struct nouveau_oclass *oclass, void *data, u32 size,
 168                 struct nouveau_object **pobject)
 169 {
 170         struct nouveau_device *device = nv_device(parent);
 171         struct nv04_vmmgr_priv *priv;
 172         int ret;
 173
 174         ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIEGART",
 175                                    "pciegart", &priv);
 176         *pobject = nv_object(priv);
 177         if (ret)
 178                 return ret;
 179
 180         priv->base.create = nv04_vm_create;
 181         priv->base.limit = NV44_GART_SIZE;
 182         priv->base.pgt_bits = 32 - 12;
 183         priv->base.spg_shift = 12;
 184         priv->base.lpg_shift = 12;
 185         priv->base.map_sg = nv44_vm_map_sg;
 186         priv->base.unmap = nv44_vm_unmap;
 187         priv->base.flush = nv44_vm_flush;
 188
 189         priv->page = alloc_page(GFP_DMA32 | GFP_KERNEL);
 190         if (priv->page) {
 191                 priv->null = pci_map_page(device->pdev, priv->page, 0,
 192                                           PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 193                 if (pci_dma_mapping_error(device->pdev, priv->null)) {
 194                         __free_page(priv->page);
 195                         priv->page = NULL;
 196                         priv->null = 0;
 197                 }
 198         }
 199
 200         if (!priv->page)
 201                 nv_warn(priv, "unable to allocate dummy page\n");
 202
 203         ret = nouveau_vm_create(&priv->base, 0, NV44_GART_SIZE, 0, 4096,
 204                                 &priv->vm);
 205         if (ret)
 206                 return ret;
 207
 208         ret = nouveau_gpuobj_new(parent, NULL,
 209                                 (NV44_GART_SIZE / NV44_GART_PAGE) * 4,
 210                                  512 * 1024, NVOBJ_FLAG_ZERO_ALLOC,
 211                                  &priv->vm->pgt[0].obj[0]);
 212         priv->vm->pgt[0].refcount[0] = 1;
 213         if (ret)
 214                 return ret;
 215
 216         return 0;
 217 }
 218
 219 static int
 220 nv44_vmmgr_init(struct nouveau_object *object)
 221 {
 222         struct nv04_vmmgr_priv *priv = (void *)object;
 223         struct nouveau_gpuobj *gart = priv->vm->pgt[0].obj[0];
 224         u32 addr;
 225         int ret;
 226
 227         ret = nouveau_vmmgr_init(&priv->base);
 228         if (ret)
 229                 return ret;
 230
 231         /* calculate vram address of this PRAMIN block, object must be
 232          * allocated on 512KiB alignment, and not exceed a total size
 233          * of 512KiB for this to work correctly
 234          */
 235         addr  = nv_rd32(priv, 0x10020c);
 236         addr -= ((gart->addr >> 19) + 1) << 19;
 237
 238         nv_wr32(priv, 0x100850, 0x80000000);
 239         nv_wr32(priv, 0x100818, priv->null);
 240         nv_wr32(priv, 0x100804, NV44_GART_SIZE);
 241         nv_wr32(priv, 0x100850, 0x00008000);
 242         nv_mask(priv, 0x10008c, 0x00000200, 0x00000200);
 243         nv_wr32(priv, 0x100820, 0x00000000);
 244         nv_wr32(priv, 0x10082c, 0x00000001);
 245         nv_wr32(priv, 0x100800, addr | 0x00000010);
 246         return 0;
 247 }
 248
 249 struct nouveau_oclass
 250 nv44_vmmgr_oclass = {
 251         .handle = NV_SUBDEV(VM, 0x44),
 252         .ofuncs = &(struct nouveau_ofuncs) {
 253                 .ctor = nv44_vmmgr_ctor,
 254                 .dtor = nv04_vmmgr_dtor,
 255                 .init = nv44_vmmgr_init,
 256                 .fini = _nouveau_vmmgr_fini,
 257         },
 258 };