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drm/nouveau/nvif: move internal class identifiers to class.h
[deliverable/linux.git] / drivers / gpu / drm / nouveau / include / nvif / class.h
1 #ifndef __NVIF_CLASS_H__
2 #define __NVIF_CLASS_H__
3
4 /* these class numbers are made up by us, and not nvidia-assigned */
5 #define NVIF_CLASS_CONTROL -1
6 #define NVIF_CLASS_PERFMON -2
7 #define NVIF_CLASS_PERFDOM -3
8 #define NVIF_CLASS_SW_NV04 -4
9 #define NVIF_CLASS_SW_NV10 -5
10 #define NVIF_CLASS_SW_NV50 -6
11 #define NVIF_CLASS_SW_GF100 -7
12
13 /* the below match nvidia-assigned (either in hw, or sw) class numbers */
14 #define NV_DEVICE 0x00000080
15
16 #define NV_DMA_FROM_MEMORY 0x00000002
17 #define NV_DMA_TO_MEMORY 0x00000003
18 #define NV_DMA_IN_MEMORY 0x0000003d
19
20 #define FERMI_TWOD_A 0x0000902d
21
22 #define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039
23
24 #define KEPLER_INLINE_TO_MEMORY_A 0x0000a040
25 #define KEPLER_INLINE_TO_MEMORY_B 0x0000a140
26
27 #define NV04_DISP 0x00000046
28
29 #define NV03_CHANNEL_DMA 0x0000006b
30 #define NV10_CHANNEL_DMA 0x0000006e
31 #define NV17_CHANNEL_DMA 0x0000176e
32 #define NV40_CHANNEL_DMA 0x0000406e
33 #define NV50_CHANNEL_DMA 0x0000506e
34 #define G82_CHANNEL_DMA 0x0000826e
35
36 #define NV50_CHANNEL_GPFIFO 0x0000506f
37 #define G82_CHANNEL_GPFIFO 0x0000826f
38 #define FERMI_CHANNEL_GPFIFO 0x0000906f
39 #define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f
40 #define MAXWELL_CHANNEL_GPFIFO_A 0x0000b06f
41
42 #define NV50_DISP 0x00005070
43 #define G82_DISP 0x00008270
44 #define GT200_DISP 0x00008370
45 #define GT214_DISP 0x00008570
46 #define GT206_DISP 0x00008870
47 #define GF110_DISP 0x00009070
48 #define GK104_DISP 0x00009170
49 #define GK110_DISP 0x00009270
50 #define GM107_DISP 0x00009470
51 #define GM204_DISP 0x00009570
52
53 #define NV31_MPEG 0x00003174
54 #define G82_MPEG 0x00008274
55
56 #define NV74_VP2 0x00007476
57
58 #define NV50_DISP_CURSOR 0x0000507a
59 #define G82_DISP_CURSOR 0x0000827a
60 #define GT214_DISP_CURSOR 0x0000857a
61 #define GF110_DISP_CURSOR 0x0000907a
62 #define GK104_DISP_CURSOR 0x0000917a
63
64 #define NV50_DISP_OVERLAY 0x0000507b
65 #define G82_DISP_OVERLAY 0x0000827b
66 #define GT214_DISP_OVERLAY 0x0000857b
67 #define GF110_DISP_OVERLAY 0x0000907b
68 #define GK104_DISP_OVERLAY 0x0000917b
69
70 #define NV50_DISP_BASE_CHANNEL_DMA 0x0000507c
71 #define G82_DISP_BASE_CHANNEL_DMA 0x0000827c
72 #define GT200_DISP_BASE_CHANNEL_DMA 0x0000837c
73 #define GT214_DISP_BASE_CHANNEL_DMA 0x0000857c
74 #define GF110_DISP_BASE_CHANNEL_DMA 0x0000907c
75 #define GK104_DISP_BASE_CHANNEL_DMA 0x0000917c
76 #define GK110_DISP_BASE_CHANNEL_DMA 0x0000927c
77
78 #define NV50_DISP_CORE_CHANNEL_DMA 0x0000507d
79 #define G82_DISP_CORE_CHANNEL_DMA 0x0000827d
80 #define GT200_DISP_CORE_CHANNEL_DMA 0x0000837d
81 #define GT214_DISP_CORE_CHANNEL_DMA 0x0000857d
82 #define GT206_DISP_CORE_CHANNEL_DMA 0x0000887d
83 #define GF110_DISP_CORE_CHANNEL_DMA 0x0000907d
84 #define GK104_DISP_CORE_CHANNEL_DMA 0x0000917d
85 #define GK110_DISP_CORE_CHANNEL_DMA 0x0000927d
86 #define GM107_DISP_CORE_CHANNEL_DMA 0x0000947d
87 #define GM204_DISP_CORE_CHANNEL_DMA 0x0000957d
88
89 #define NV50_DISP_OVERLAY_CHANNEL_DMA 0x0000507e
90 #define G82_DISP_OVERLAY_CHANNEL_DMA 0x0000827e
91 #define GT200_DISP_OVERLAY_CHANNEL_DMA 0x0000837e
92 #define GT214_DISP_OVERLAY_CHANNEL_DMA 0x0000857e
93 #define GF110_DISP_OVERLAY_CONTROL_DMA 0x0000907e
94 #define GK104_DISP_OVERLAY_CONTROL_DMA 0x0000917e
95
96 #define FERMI_A 0x00009097
97 #define FERMI_B 0x00009197
98 #define FERMI_C 0x00009297
99
100 #define KEPLER_A 0x0000a097
101 #define KEPLER_B 0x0000a197
102 #define KEPLER_C 0x0000a297
103
104 #define MAXWELL_A 0x0000b097
105 #define MAXWELL_B 0x0000b197
106
107 #define NV74_BSP 0x000074b0
108
109 #define GT212_MSVLD 0x000085b1
110 #define IGT21A_MSVLD 0x000086b1
111 #define G98_MSVLD 0x000088b1
112 #define GF100_MSVLD 0x000090b1
113 #define GK104_MSVLD 0x000095b1
114
115 #define GT212_MSPDEC 0x000085b2
116 #define G98_MSPDEC 0x000088b2
117 #define GF100_MSPDEC 0x000090b2
118 #define GK104_MSPDEC 0x000095b2
119
120 #define GT212_MSPPP 0x000085b3
121 #define G98_MSPPP 0x000088b3
122 #define GF100_MSPPP 0x000090b3
123
124 #define G98_SEC 0x000088b4
125
126 #define GT212_DMA 0x000085b5
127 #define FERMI_DMA 0x000090b5
128 #define KEPLER_DMA_COPY_A 0x0000a0b5
129 #define MAXWELL_DMA_COPY_A 0x0000b0b5
130
131 #define FERMI_DECOMPRESS 0x000090b8
132
133 #define FERMI_COMPUTE_A 0x000090c0
134 #define FERMI_COMPUTE_B 0x000091c0
135 #define KEPLER_COMPUTE_A 0x0000a0c0
136 #define KEPLER_COMPUTE_B 0x0000a1c0
137 #define MAXWELL_COMPUTE_A 0x0000b0c0
138 #define MAXWELL_COMPUTE_B 0x0000b1c0
139
140 #define NV74_CIPHER 0x000074c1
141
142 /*******************************************************************************
143 * client
144 ******************************************************************************/
145
146 #define NV_CLIENT_DEVLIST 0x00
147
148 struct nv_client_devlist_v0 {
149 __u8 version;
150 __u8 count;
151 __u8 pad02[6];
152 __u64 device[];
153 };
154
155
156 /*******************************************************************************
157 * device
158 ******************************************************************************/
159
160 struct nv_device_v0 {
161 __u8 version;
162 __u8 pad01[7];
163 __u64 device; /* device identifier, ~0 for client default */
164 };
165
166 #define NV_DEVICE_V0_INFO 0x00
167 #define NV_DEVICE_V0_TIME 0x01
168
169 struct nv_device_info_v0 {
170 __u8 version;
171 #define NV_DEVICE_INFO_V0_IGP 0x00
172 #define NV_DEVICE_INFO_V0_PCI 0x01
173 #define NV_DEVICE_INFO_V0_AGP 0x02
174 #define NV_DEVICE_INFO_V0_PCIE 0x03
175 #define NV_DEVICE_INFO_V0_SOC 0x04
176 __u8 platform;
177 __u16 chipset; /* from NV_PMC_BOOT_0 */
178 __u8 revision; /* from NV_PMC_BOOT_0 */
179 #define NV_DEVICE_INFO_V0_TNT 0x01
180 #define NV_DEVICE_INFO_V0_CELSIUS 0x02
181 #define NV_DEVICE_INFO_V0_KELVIN 0x03
182 #define NV_DEVICE_INFO_V0_RANKINE 0x04
183 #define NV_DEVICE_INFO_V0_CURIE 0x05
184 #define NV_DEVICE_INFO_V0_TESLA 0x06
185 #define NV_DEVICE_INFO_V0_FERMI 0x07
186 #define NV_DEVICE_INFO_V0_KEPLER 0x08
187 #define NV_DEVICE_INFO_V0_MAXWELL 0x09
188 __u8 family;
189 __u8 pad06[2];
190 __u64 ram_size;
191 __u64 ram_user;
192 char chip[16];
193 char name[64];
194 };
195
196 struct nv_device_time_v0 {
197 __u8 version;
198 __u8 pad01[7];
199 __u64 time;
200 };
201
202
203 /*******************************************************************************
204 * context dma
205 ******************************************************************************/
206
207 struct nv_dma_v0 {
208 __u8 version;
209 #define NV_DMA_V0_TARGET_VM 0x00
210 #define NV_DMA_V0_TARGET_VRAM 0x01
211 #define NV_DMA_V0_TARGET_PCI 0x02
212 #define NV_DMA_V0_TARGET_PCI_US 0x03
213 #define NV_DMA_V0_TARGET_AGP 0x04
214 __u8 target;
215 #define NV_DMA_V0_ACCESS_VM 0x00
216 #define NV_DMA_V0_ACCESS_RD 0x01
217 #define NV_DMA_V0_ACCESS_WR 0x02
218 #define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
219 __u8 access;
220 __u8 pad03[5];
221 __u64 start;
222 __u64 limit;
223 /* ... chipset-specific class data */
224 };
225
226 struct nv50_dma_v0 {
227 __u8 version;
228 #define NV50_DMA_V0_PRIV_VM 0x00
229 #define NV50_DMA_V0_PRIV_US 0x01
230 #define NV50_DMA_V0_PRIV__S 0x02
231 __u8 priv;
232 #define NV50_DMA_V0_PART_VM 0x00
233 #define NV50_DMA_V0_PART_256 0x01
234 #define NV50_DMA_V0_PART_1KB 0x02
235 __u8 part;
236 #define NV50_DMA_V0_COMP_NONE 0x00
237 #define NV50_DMA_V0_COMP_1 0x01
238 #define NV50_DMA_V0_COMP_2 0x02
239 #define NV50_DMA_V0_COMP_VM 0x03
240 __u8 comp;
241 #define NV50_DMA_V0_KIND_PITCH 0x00
242 #define NV50_DMA_V0_KIND_VM 0x7f
243 __u8 kind;
244 __u8 pad05[3];
245 };
246
247 struct gf100_dma_v0 {
248 __u8 version;
249 #define GF100_DMA_V0_PRIV_VM 0x00
250 #define GF100_DMA_V0_PRIV_US 0x01
251 #define GF100_DMA_V0_PRIV__S 0x02
252 __u8 priv;
253 #define GF100_DMA_V0_KIND_PITCH 0x00
254 #define GF100_DMA_V0_KIND_VM 0xff
255 __u8 kind;
256 __u8 pad03[5];
257 };
258
259 struct gf119_dma_v0 {
260 __u8 version;
261 #define GF119_DMA_V0_PAGE_LP 0x00
262 #define GF119_DMA_V0_PAGE_SP 0x01
263 __u8 page;
264 #define GF119_DMA_V0_KIND_PITCH 0x00
265 #define GF119_DMA_V0_KIND_VM 0xff
266 __u8 kind;
267 __u8 pad03[5];
268 };
269
270
271 /*******************************************************************************
272 * perfmon
273 ******************************************************************************/
274
275 #define NVIF_PERFMON_V0_QUERY_DOMAIN 0x00
276 #define NVIF_PERFMON_V0_QUERY_SIGNAL 0x01
277 #define NVIF_PERFMON_V0_QUERY_SOURCE 0x02
278
279 struct nvif_perfmon_query_domain_v0 {
280 __u8 version;
281 __u8 id;
282 __u8 counter_nr;
283 __u8 iter;
284 __u16 signal_nr;
285 __u8 pad05[2];
286 char name[64];
287 };
288
289 struct nvif_perfmon_query_signal_v0 {
290 __u8 version;
291 __u8 domain;
292 __u16 iter;
293 __u8 signal;
294 __u8 source_nr;
295 __u8 pad05[2];
296 char name[64];
297 };
298
299 struct nvif_perfmon_query_source_v0 {
300 __u8 version;
301 __u8 domain;
302 __u8 signal;
303 __u8 iter;
304 __u8 pad04[4];
305 __u32 source;
306 __u32 mask;
307 char name[64];
308 };
309
310
311 /*******************************************************************************
312 * perfdom
313 ******************************************************************************/
314
315 struct nvif_perfdom_v0 {
316 __u8 version;
317 __u8 domain;
318 __u8 mode;
319 __u8 pad03[1];
320 struct {
321 __u8 signal[4];
322 __u64 source[4][8];
323 __u16 logic_op;
324 } ctr[4];
325 };
326
327 #define NVIF_PERFDOM_V0_INIT 0x00
328 #define NVIF_PERFDOM_V0_SAMPLE 0x01
329 #define NVIF_PERFDOM_V0_READ 0x02
330
331 struct nvif_perfdom_init {
332 };
333
334 struct nvif_perfdom_sample {
335 };
336
337 struct nvif_perfdom_read_v0 {
338 __u8 version;
339 __u8 pad01[7];
340 __u32 ctr[4];
341 __u32 clk;
342 __u8 pad04[4];
343 };
344
345
346 /*******************************************************************************
347 * device control
348 ******************************************************************************/
349
350 #define NVIF_CONTROL_PSTATE_INFO 0x00
351 #define NVIF_CONTROL_PSTATE_ATTR 0x01
352 #define NVIF_CONTROL_PSTATE_USER 0x02
353
354 struct nvif_control_pstate_info_v0 {
355 __u8 version;
356 __u8 count; /* out: number of power states */
357 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE (-1)
358 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON (-2)
359 __s8 ustate_ac; /* out: target pstate index */
360 __s8 ustate_dc; /* out: target pstate index */
361 __s8 pwrsrc; /* out: current power source */
362 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN (-1)
363 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON (-2)
364 __s8 pstate; /* out: current pstate index */
365 __u8 pad06[2];
366 };
367
368 struct nvif_control_pstate_attr_v0 {
369 __u8 version;
370 #define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT (-1)
371 __s8 state; /* in: index of pstate to query
372 * out: pstate identifier
373 */
374 __u8 index; /* in: index of attribute to query
375 * out: index of next attribute, or 0 if no more
376 */
377 __u8 pad03[5];
378 __u32 min;
379 __u32 max;
380 char name[32];
381 char unit[16];
382 };
383
384 struct nvif_control_pstate_user_v0 {
385 __u8 version;
386 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN (-1)
387 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON (-2)
388 __s8 ustate; /* in: pstate identifier */
389 __s8 pwrsrc; /* in: target power source */
390 __u8 pad03[5];
391 };
392
393
394 /*******************************************************************************
395 * DMA FIFO channels
396 ******************************************************************************/
397
398 struct nv03_channel_dma_v0 {
399 __u8 version;
400 __u8 chid;
401 __u8 pad02[2];
402 __u32 offset;
403 __u64 pushbuf;
404 };
405
406 struct nv50_channel_dma_v0 {
407 __u8 version;
408 __u8 chid;
409 __u8 pad02[6];
410 __u64 vm;
411 __u64 pushbuf;
412 __u64 offset;
413 };
414
415 #define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
416
417 /*******************************************************************************
418 * GPFIFO channels
419 ******************************************************************************/
420
421 struct nv50_channel_gpfifo_v0 {
422 __u8 version;
423 __u8 chid;
424 __u8 pad02[2];
425 __u32 ilength;
426 __u64 ioffset;
427 __u64 pushbuf;
428 __u64 vm;
429 };
430
431 struct fermi_channel_gpfifo_v0 {
432 __u8 version;
433 __u8 chid;
434 __u8 pad02[2];
435 __u32 ilength;
436 __u64 ioffset;
437 __u64 vm;
438 };
439
440 struct kepler_channel_gpfifo_a_v0 {
441 __u8 version;
442 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01
443 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC 0x02
444 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP 0x04
445 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD 0x08
446 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10
447 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20
448 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40
449 __u8 engine;
450 __u16 chid;
451 __u32 ilength;
452 __u64 ioffset;
453 __u64 vm;
454 };
455
456 /*******************************************************************************
457 * legacy display
458 ******************************************************************************/
459
460 #define NV04_DISP_NTFY_VBLANK 0x00
461 #define NV04_DISP_NTFY_CONN 0x01
462
463 struct nv04_disp_mthd_v0 {
464 __u8 version;
465 #define NV04_DISP_SCANOUTPOS 0x00
466 __u8 method;
467 __u8 head;
468 __u8 pad03[5];
469 };
470
471 struct nv04_disp_scanoutpos_v0 {
472 __u8 version;
473 __u8 pad01[7];
474 __s64 time[2];
475 __u16 vblanks;
476 __u16 vblanke;
477 __u16 vtotal;
478 __u16 vline;
479 __u16 hblanks;
480 __u16 hblanke;
481 __u16 htotal;
482 __u16 hline;
483 };
484
485 /*******************************************************************************
486 * display
487 ******************************************************************************/
488
489 #define NV50_DISP_MTHD 0x00
490
491 struct nv50_disp_mthd_v0 {
492 __u8 version;
493 #define NV50_DISP_SCANOUTPOS 0x00
494 __u8 method;
495 __u8 head;
496 __u8 pad03[5];
497 };
498
499 struct nv50_disp_mthd_v1 {
500 __u8 version;
501 #define NV50_DISP_MTHD_V1_DAC_PWR 0x10
502 #define NV50_DISP_MTHD_V1_DAC_LOAD 0x11
503 #define NV50_DISP_MTHD_V1_SOR_PWR 0x20
504 #define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21
505 #define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22
506 #define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23
507 #define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24
508 #define NV50_DISP_MTHD_V1_PIOR_PWR 0x30
509 __u8 method;
510 __u16 hasht;
511 __u16 hashm;
512 __u8 pad06[2];
513 };
514
515 struct nv50_disp_dac_pwr_v0 {
516 __u8 version;
517 __u8 state;
518 __u8 data;
519 __u8 vsync;
520 __u8 hsync;
521 __u8 pad05[3];
522 };
523
524 struct nv50_disp_dac_load_v0 {
525 __u8 version;
526 __u8 load;
527 __u8 pad02[2];
528 __u32 data;
529 };
530
531 struct nv50_disp_sor_pwr_v0 {
532 __u8 version;
533 __u8 state;
534 __u8 pad02[6];
535 };
536
537 struct nv50_disp_sor_hda_eld_v0 {
538 __u8 version;
539 __u8 pad01[7];
540 __u8 data[];
541 };
542
543 struct nv50_disp_sor_hdmi_pwr_v0 {
544 __u8 version;
545 __u8 state;
546 __u8 max_ac_packet;
547 __u8 rekey;
548 __u8 pad04[4];
549 };
550
551 struct nv50_disp_sor_lvds_script_v0 {
552 __u8 version;
553 __u8 pad01[1];
554 __u16 script;
555 __u8 pad04[4];
556 };
557
558 struct nv50_disp_sor_dp_pwr_v0 {
559 __u8 version;
560 __u8 state;
561 __u8 pad02[6];
562 };
563
564 struct nv50_disp_pior_pwr_v0 {
565 __u8 version;
566 __u8 state;
567 __u8 type;
568 __u8 pad03[5];
569 };
570
571 /* core */
572 struct nv50_disp_core_channel_dma_v0 {
573 __u8 version;
574 __u8 pad01[7];
575 __u64 pushbuf;
576 };
577
578 #define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
579
580 /* cursor immediate */
581 struct nv50_disp_cursor_v0 {
582 __u8 version;
583 __u8 head;
584 __u8 pad02[6];
585 };
586
587 #define NV50_DISP_CURSOR_V0_NTFY_UEVENT 0x00
588
589 /* base */
590 struct nv50_disp_base_channel_dma_v0 {
591 __u8 version;
592 __u8 head;
593 __u8 pad02[6];
594 __u64 pushbuf;
595 };
596
597 #define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
598
599 /* overlay */
600 struct nv50_disp_overlay_channel_dma_v0 {
601 __u8 version;
602 __u8 head;
603 __u8 pad02[6];
604 __u64 pushbuf;
605 };
606
607 #define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
608
609 /* overlay immediate */
610 struct nv50_disp_overlay_v0 {
611 __u8 version;
612 __u8 head;
613 __u8 pad02[6];
614 };
615
616 #define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00
617
618 /*******************************************************************************
619 * software
620 ******************************************************************************/
621
622 #define NVSW_NTFY_UEVENT 0x00
623
624 #define NV04_NVSW_GET_REF 0x00
625
626 struct nv04_nvsw_get_ref_v0 {
627 __u8 version;
628 __u8 pad01[3];
629 __u32 ref;
630 };
631
632 /*******************************************************************************
633 * fermi
634 ******************************************************************************/
635
636 #define FERMI_A_ZBC_COLOR 0x00
637 #define FERMI_A_ZBC_DEPTH 0x01
638
639 struct fermi_a_zbc_color_v0 {
640 __u8 version;
641 #define FERMI_A_ZBC_COLOR_V0_FMT_ZERO 0x01
642 #define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE 0x02
643 #define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32 0x04
644 #define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16 0x08
645 #define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16 0x0c
646 #define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16 0x10
647 #define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16 0x14
648 #define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16 0x16
649 #define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8 0x18
650 #define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8 0x1c
651 #define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10 0x20
652 #define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10 0x24
653 #define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8 0x28
654 #define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8 0x2c
655 #define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8 0x30
656 #define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8 0x34
657 #define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8 0x38
658 #define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10 0x3c
659 #define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11 0x40
660 __u8 format;
661 __u8 index;
662 __u8 pad03[5];
663 __u32 ds[4];
664 __u32 l2[4];
665 };
666
667 struct fermi_a_zbc_depth_v0 {
668 __u8 version;
669 #define FERMI_A_ZBC_DEPTH_V0_FMT_FP32 0x01
670 __u8 format;
671 __u8 index;
672 __u8 pad03[5];
673 __u32 ds;
674 __u32 l2;
675 };
676
677 #endif
Linux kernel - Deliverables
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