drivers/gpu/drm/nouveau/include/nvif/class.h

   1 #ifndef __NVIF_CLASS_H__
   2 #define __NVIF_CLASS_H__
   3
   4 /* these class numbers are made up by us, and not nvidia-assigned */
   5 #define NVIF_CLASS_CONTROL                                                   -1
   6 #define NVIF_CLASS_PERFMON                                                   -2
   7 #define NVIF_CLASS_PERFDOM                                                   -3
   8 #define NVIF_CLASS_SW_NV04                                    /* if0004.h */ -4
   9 #define NVIF_CLASS_SW_NV10                                    /* if0005.h */ -5
  10 #define NVIF_CLASS_SW_NV50                                    /* if0005.h */ -6
  11 #define NVIF_CLASS_SW_GF100                                   /* if0005.h */ -7
  12
  13 /* the below match nvidia-assigned (either in hw, or sw) class numbers */
  14 #define NV_DEVICE                                                    0x00000080
  15
  16 #define NV_DMA_FROM_MEMORY                                           0x00000002
  17 #define NV_DMA_TO_MEMORY                                             0x00000003
  18 #define NV_DMA_IN_MEMORY                                             0x0000003d
  19
  20 #define FERMI_TWOD_A                                                 0x0000902d
  21
  22 #define FERMI_MEMORY_TO_MEMORY_FORMAT_A                              0x00009039
  23
  24 #define KEPLER_INLINE_TO_MEMORY_A                                    0x0000a040
  25 #define KEPLER_INLINE_TO_MEMORY_B                                    0x0000a140
  26
  27 #define NV04_DISP                                     /* cl0046.h */ 0x00000046
  28
  29 #define NV03_CHANNEL_DMA                              /* cl506b.h */ 0x0000006b
  30 #define NV10_CHANNEL_DMA                              /* cl506b.h */ 0x0000006e
  31 #define NV17_CHANNEL_DMA                              /* cl506b.h */ 0x0000176e
  32 #define NV40_CHANNEL_DMA                              /* cl506b.h */ 0x0000406e
  33 #define NV50_CHANNEL_DMA                              /* cl506e.h */ 0x0000506e
  34 #define G82_CHANNEL_DMA                               /* cl826e.h */ 0x0000826e
  35
  36 #define NV50_CHANNEL_GPFIFO                           /* cl506f.h */ 0x0000506f
  37 #define G82_CHANNEL_GPFIFO                            /* cl826f.h */ 0x0000826f
  38 #define FERMI_CHANNEL_GPFIFO                          /* cl906f.h */ 0x0000906f
  39 #define KEPLER_CHANNEL_GPFIFO_A                       /* cla06f.h */ 0x0000a06f
  40 #define MAXWELL_CHANNEL_GPFIFO_A                      /* cla06f.h */ 0x0000b06f
  41
  42 #define NV50_DISP                                     /* cl5070.h */ 0x00005070
  43 #define G82_DISP                                      /* cl5070.h */ 0x00008270
  44 #define GT200_DISP                                    /* cl5070.h */ 0x00008370
  45 #define GT214_DISP                                    /* cl5070.h */ 0x00008570
  46 #define GT206_DISP                                    /* cl5070.h */ 0x00008870
  47 #define GF110_DISP                                    /* cl5070.h */ 0x00009070
  48 #define GK104_DISP                                    /* cl5070.h */ 0x00009170
  49 #define GK110_DISP                                    /* cl5070.h */ 0x00009270
  50 #define GM107_DISP                                    /* cl5070.h */ 0x00009470
  51 #define GM204_DISP                                    /* cl5070.h */ 0x00009570
  52
  53 #define NV31_MPEG                                                    0x00003174
  54 #define G82_MPEG                                                     0x00008274
  55
  56 #define NV74_VP2                                                     0x00007476
  57
  58 #define NV50_DISP_CURSOR                              /* cl507a.h */ 0x0000507a
  59 #define G82_DISP_CURSOR                               /* cl507a.h */ 0x0000827a
  60 #define GT214_DISP_CURSOR                             /* cl507a.h */ 0x0000857a
  61 #define GF110_DISP_CURSOR                             /* cl507a.h */ 0x0000907a
  62 #define GK104_DISP_CURSOR                             /* cl507a.h */ 0x0000917a
  63
  64 #define NV50_DISP_OVERLAY                             /* cl507b.h */ 0x0000507b
  65 #define G82_DISP_OVERLAY                              /* cl507b.h */ 0x0000827b
  66 #define GT214_DISP_OVERLAY                            /* cl507b.h */ 0x0000857b
  67 #define GF110_DISP_OVERLAY                            /* cl507b.h */ 0x0000907b
  68 #define GK104_DISP_OVERLAY                            /* cl507b.h */ 0x0000917b
  69
  70 #define NV50_DISP_BASE_CHANNEL_DMA                    /* cl507c.h */ 0x0000507c
  71 #define G82_DISP_BASE_CHANNEL_DMA                     /* cl507c.h */ 0x0000827c
  72 #define GT200_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000837c
  73 #define GT214_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000857c
  74 #define GF110_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000907c
  75 #define GK104_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000917c
  76 #define GK110_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000927c
  77
  78 #define NV50_DISP_CORE_CHANNEL_DMA                    /* cl507d.h */ 0x0000507d
  79 #define G82_DISP_CORE_CHANNEL_DMA                     /* cl507d.h */ 0x0000827d
  80 #define GT200_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000837d
  81 #define GT214_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000857d
  82 #define GT206_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000887d
  83 #define GF110_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000907d
  84 #define GK104_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000917d
  85 #define GK110_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000927d
  86 #define GM107_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000947d
  87 #define GM204_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000957d
  88
  89 #define NV50_DISP_OVERLAY_CHANNEL_DMA                 /* cl507e.h */ 0x0000507e
  90 #define G82_DISP_OVERLAY_CHANNEL_DMA                  /* cl507e.h */ 0x0000827e
  91 #define GT200_DISP_OVERLAY_CHANNEL_DMA                /* cl507e.h */ 0x0000837e
  92 #define GT214_DISP_OVERLAY_CHANNEL_DMA                /* cl507e.h */ 0x0000857e
  93 #define GF110_DISP_OVERLAY_CONTROL_DMA                /* cl507e.h */ 0x0000907e
  94 #define GK104_DISP_OVERLAY_CONTROL_DMA                /* cl507e.h */ 0x0000917e
  95
  96 #define FERMI_A                                       /* cl9097.h */ 0x00009097
  97 #define FERMI_B                                       /* cl9097.h */ 0x00009197
  98 #define FERMI_C                                       /* cl9097.h */ 0x00009297
  99
 100 #define KEPLER_A                                      /* cl9097.h */ 0x0000a097
 101 #define KEPLER_B                                      /* cl9097.h */ 0x0000a197
 102 #define KEPLER_C                                      /* cl9097.h */ 0x0000a297
 103
 104 #define MAXWELL_A                                     /* cl9097.h */ 0x0000b097
 105 #define MAXWELL_B                                     /* cl9097.h */ 0x0000b197
 106
 107 #define NV74_BSP                                                     0x000074b0
 108
 109 #define GT212_MSVLD                                                  0x000085b1
 110 #define IGT21A_MSVLD                                                 0x000086b1
 111 #define G98_MSVLD                                                    0x000088b1
 112 #define GF100_MSVLD                                                  0x000090b1
 113 #define GK104_MSVLD                                                  0x000095b1
 114
 115 #define GT212_MSPDEC                                                 0x000085b2
 116 #define G98_MSPDEC                                                   0x000088b2
 117 #define GF100_MSPDEC                                                 0x000090b2
 118 #define GK104_MSPDEC                                                 0x000095b2
 119
 120 #define GT212_MSPPP                                                  0x000085b3
 121 #define G98_MSPPP                                                    0x000088b3
 122 #define GF100_MSPPP                                                  0x000090b3
 123
 124 #define G98_SEC                                                      0x000088b4
 125
 126 #define GT212_DMA                                                    0x000085b5
 127 #define FERMI_DMA                                                    0x000090b5
 128 #define KEPLER_DMA_COPY_A                                            0x0000a0b5
 129 #define MAXWELL_DMA_COPY_A                                           0x0000b0b5
 130
 131 #define FERMI_DECOMPRESS                                             0x000090b8
 132
 133 #define FERMI_COMPUTE_A                                              0x000090c0
 134 #define FERMI_COMPUTE_B                                              0x000091c0
 135 #define KEPLER_COMPUTE_A                                             0x0000a0c0
 136 #define KEPLER_COMPUTE_B                                             0x0000a1c0
 137 #define MAXWELL_COMPUTE_A                                            0x0000b0c0
 138 #define MAXWELL_COMPUTE_B                                            0x0000b1c0
 139
 140 #define NV74_CIPHER                                                  0x000074c1
 141
 142 /*******************************************************************************
 143  * client
 144  ******************************************************************************/
 145
 146 #define NV_CLIENT_DEVLIST                                                  0x00
 147
 148 struct nv_client_devlist_v0 {
 149         __u8  version;
 150         __u8  count;
 151         __u8  pad02[6];
 152         __u64 device[];
 153 };
 154
 155
 156 /*******************************************************************************
 157  * device
 158  ******************************************************************************/
 159
 160 struct nv_device_v0 {
 161         __u8  version;
 162         __u8  pad01[7];
 163         __u64 device;   /* device identifier, ~0 for client default */
 164 };
 165
 166 #define NV_DEVICE_V0_INFO                                                  0x00
 167 #define NV_DEVICE_V0_TIME                                                  0x01
 168
 169 struct nv_device_info_v0 {
 170         __u8  version;
 171 #define NV_DEVICE_INFO_V0_IGP                                              0x00
 172 #define NV_DEVICE_INFO_V0_PCI                                              0x01
 173 #define NV_DEVICE_INFO_V0_AGP                                              0x02
 174 #define NV_DEVICE_INFO_V0_PCIE                                             0x03
 175 #define NV_DEVICE_INFO_V0_SOC                                              0x04
 176         __u8  platform;
 177         __u16 chipset;  /* from NV_PMC_BOOT_0 */
 178         __u8  revision; /* from NV_PMC_BOOT_0 */
 179 #define NV_DEVICE_INFO_V0_TNT                                              0x01
 180 #define NV_DEVICE_INFO_V0_CELSIUS                                          0x02
 181 #define NV_DEVICE_INFO_V0_KELVIN                                           0x03
 182 #define NV_DEVICE_INFO_V0_RANKINE                                          0x04
 183 #define NV_DEVICE_INFO_V0_CURIE                                            0x05
 184 #define NV_DEVICE_INFO_V0_TESLA                                            0x06
 185 #define NV_DEVICE_INFO_V0_FERMI                                            0x07
 186 #define NV_DEVICE_INFO_V0_KEPLER                                           0x08
 187 #define NV_DEVICE_INFO_V0_MAXWELL                                          0x09
 188         __u8  family;
 189         __u8  pad06[2];
 190         __u64 ram_size;
 191         __u64 ram_user;
 192         char  chip[16];
 193         char  name[64];
 194 };
 195
 196 struct nv_device_time_v0 {
 197         __u8  version;
 198         __u8  pad01[7];
 199         __u64 time;
 200 };
 201
 202
 203 /*******************************************************************************
 204  * context dma
 205  ******************************************************************************/
 206
 207 struct nv_dma_v0 {
 208         __u8  version;
 209 #define NV_DMA_V0_TARGET_VM                                                0x00
 210 #define NV_DMA_V0_TARGET_VRAM                                              0x01
 211 #define NV_DMA_V0_TARGET_PCI                                               0x02
 212 #define NV_DMA_V0_TARGET_PCI_US                                            0x03
 213 #define NV_DMA_V0_TARGET_AGP                                               0x04
 214         __u8  target;
 215 #define NV_DMA_V0_ACCESS_VM                                                0x00
 216 #define NV_DMA_V0_ACCESS_RD                                                0x01
 217 #define NV_DMA_V0_ACCESS_WR                                                0x02
 218 #define NV_DMA_V0_ACCESS_RDWR                 (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
 219         __u8  access;
 220         __u8  pad03[5];
 221         __u64 start;
 222         __u64 limit;
 223         /* ... chipset-specific class data */
 224 };
 225
 226 struct nv50_dma_v0 {
 227         __u8  version;
 228 #define NV50_DMA_V0_PRIV_VM                                                0x00
 229 #define NV50_DMA_V0_PRIV_US                                                0x01
 230 #define NV50_DMA_V0_PRIV__S                                                0x02
 231         __u8  priv;
 232 #define NV50_DMA_V0_PART_VM                                                0x00
 233 #define NV50_DMA_V0_PART_256                                               0x01
 234 #define NV50_DMA_V0_PART_1KB                                               0x02
 235         __u8  part;
 236 #define NV50_DMA_V0_COMP_NONE                                              0x00
 237 #define NV50_DMA_V0_COMP_1                                                 0x01
 238 #define NV50_DMA_V0_COMP_2                                                 0x02
 239 #define NV50_DMA_V0_COMP_VM                                                0x03
 240         __u8  comp;
 241 #define NV50_DMA_V0_KIND_PITCH                                             0x00
 242 #define NV50_DMA_V0_KIND_VM                                                0x7f
 243         __u8  kind;
 244         __u8  pad05[3];
 245 };
 246
 247 struct gf100_dma_v0 {
 248         __u8  version;
 249 #define GF100_DMA_V0_PRIV_VM                                               0x00
 250 #define GF100_DMA_V0_PRIV_US                                               0x01
 251 #define GF100_DMA_V0_PRIV__S                                               0x02
 252         __u8  priv;
 253 #define GF100_DMA_V0_KIND_PITCH                                            0x00
 254 #define GF100_DMA_V0_KIND_VM                                               0xff
 255         __u8  kind;
 256         __u8  pad03[5];
 257 };
 258
 259 struct gf119_dma_v0 {
 260         __u8  version;
 261 #define GF119_DMA_V0_PAGE_LP                                               0x00
 262 #define GF119_DMA_V0_PAGE_SP                                               0x01
 263         __u8  page;
 264 #define GF119_DMA_V0_KIND_PITCH                                            0x00
 265 #define GF119_DMA_V0_KIND_VM                                               0xff
 266         __u8  kind;
 267         __u8  pad03[5];
 268 };
 269
 270
 271 /*******************************************************************************
 272  * perfmon
 273  ******************************************************************************/
 274
 275 #define NVIF_PERFMON_V0_QUERY_DOMAIN                                       0x00
 276 #define NVIF_PERFMON_V0_QUERY_SIGNAL                                       0x01
 277 #define NVIF_PERFMON_V0_QUERY_SOURCE                                       0x02
 278
 279 struct nvif_perfmon_query_domain_v0 {
 280         __u8  version;
 281         __u8  id;
 282         __u8  counter_nr;
 283         __u8  iter;
 284         __u16 signal_nr;
 285         __u8  pad05[2];
 286         char  name[64];
 287 };
 288
 289 struct nvif_perfmon_query_signal_v0 {
 290         __u8  version;
 291         __u8  domain;
 292         __u16 iter;
 293         __u8  signal;
 294         __u8  source_nr;
 295         __u8  pad05[2];
 296         char  name[64];
 297 };
 298
 299 struct nvif_perfmon_query_source_v0 {
 300         __u8  version;
 301         __u8  domain;
 302         __u8  signal;
 303         __u8  iter;
 304         __u8  pad04[4];
 305         __u32 source;
 306         __u32 mask;
 307         char  name[64];
 308 };
 309
 310
 311 /*******************************************************************************
 312  * perfdom
 313  ******************************************************************************/
 314
 315 struct nvif_perfdom_v0 {
 316         __u8  version;
 317         __u8  domain;
 318         __u8  mode;
 319         __u8  pad03[1];
 320         struct {
 321                 __u8  signal[4];
 322                 __u64 source[4][8];
 323                 __u16 logic_op;
 324         } ctr[4];
 325 };
 326
 327 #define NVIF_PERFDOM_V0_INIT                                               0x00
 328 #define NVIF_PERFDOM_V0_SAMPLE                                             0x01
 329 #define NVIF_PERFDOM_V0_READ                                               0x02
 330
 331 struct nvif_perfdom_init {
 332 };
 333
 334 struct nvif_perfdom_sample {
 335 };
 336
 337 struct nvif_perfdom_read_v0 {
 338         __u8  version;
 339         __u8  pad01[7];
 340         __u32 ctr[4];
 341         __u32 clk;
 342         __u8  pad04[4];
 343 };
 344
 345
 346 /*******************************************************************************
 347  * device control
 348  ******************************************************************************/
 349
 350 #define NVIF_CONTROL_PSTATE_INFO                                           0x00
 351 #define NVIF_CONTROL_PSTATE_ATTR                                           0x01
 352 #define NVIF_CONTROL_PSTATE_USER                                           0x02
 353
 354 struct nvif_control_pstate_info_v0 {
 355         __u8  version;
 356         __u8  count; /* out: number of power states */
 357 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE                         (-1)
 358 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON                         (-2)
 359         __s8  ustate_ac; /* out: target pstate index */
 360         __s8  ustate_dc; /* out: target pstate index */
 361         __s8  pwrsrc; /* out: current power source */
 362 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN                         (-1)
 363 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON                         (-2)
 364         __s8  pstate; /* out: current pstate index */
 365         __u8  pad06[2];
 366 };
 367
 368 struct nvif_control_pstate_attr_v0 {
 369         __u8  version;
 370 #define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT                          (-1)
 371         __s8  state; /*  in: index of pstate to query
 372                       * out: pstate identifier
 373                       */
 374         __u8  index; /*  in: index of attribute to query
 375                       * out: index of next attribute, or 0 if no more
 376                       */
 377         __u8  pad03[5];
 378         __u32 min;
 379         __u32 max;
 380         char  name[32];
 381         char  unit[16];
 382 };
 383
 384 struct nvif_control_pstate_user_v0 {
 385         __u8  version;
 386 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN                          (-1)
 387 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON                          (-2)
 388         __s8  ustate; /*  in: pstate identifier */
 389         __s8  pwrsrc; /*  in: target power source */
 390         __u8  pad03[5];
 391 };
 392 #endif