drivers/gpu/drm/nouveau/include/nvif/if0001.h

   1 #ifndef __NVIF_IF0001_H__
   2 #define __NVIF_IF0001_H__
   3
   4 #define NVIF_CONTROL_PSTATE_INFO                                           0x00
   5 #define NVIF_CONTROL_PSTATE_ATTR                                           0x01
   6 #define NVIF_CONTROL_PSTATE_USER                                           0x02
   7
   8 struct nvif_control_pstate_info_v0 {
   9         __u8  version;
  10         __u8  count; /* out: number of power states */
  11 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE                         (-1)
  12 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON                         (-2)
  13         __s8  ustate_ac; /* out: target pstate index */
  14         __s8  ustate_dc; /* out: target pstate index */
  15         __s8  pwrsrc; /* out: current power source */
  16 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN                         (-1)
  17 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON                         (-2)
  18         __s8  pstate; /* out: current pstate index */
  19         __u8  pad06[2];
  20 };
  21
  22 struct nvif_control_pstate_attr_v0 {
  23         __u8  version;
  24 #define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT                          (-1)
  25         __s8  state; /*  in: index of pstate to query
  26                       * out: pstate identifier
  27                       */
  28         __u8  index; /*  in: index of attribute to query
  29                       * out: index of next attribute, or 0 if no more
  30                       */
  31         __u8  pad03[5];
  32         __u32 min;
  33         __u32 max;
  34         char  name[32];
  35         char  unit[16];
  36 };
  37
  38 struct nvif_control_pstate_user_v0 {
  39         __u8  version;
  40 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN                          (-1)
  41 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON                          (-2)
  42         __s8  ustate; /*  in: pstate identifier */
  43         __s8  pwrsrc; /*  in: target power source */
  44         __u8  pad03[5];
  45 };
  46 #endif