2 * Copyright 2007 Dave Airlied
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
30 #include <linux/dma-mapping.h>
31 #include <linux/swiotlb.h>
33 #include "nouveau_drm.h"
34 #include "nouveau_dma.h"
35 #include "nouveau_fence.h"
37 #include "nouveau_bo.h"
38 #include "nouveau_ttm.h"
39 #include "nouveau_gem.h"
42 * NV10-NV40 tiling helpers
46 nv10_bo_update_tile_region(struct drm_device
*dev
, struct nouveau_drm_tile
*reg
,
47 u32 addr
, u32 size
, u32 pitch
, u32 flags
)
49 struct nouveau_drm
*drm
= nouveau_drm(dev
);
50 int i
= reg
- drm
->tile
.reg
;
51 struct nouveau_fb
*pfb
= nvkm_fb(&drm
->device
);
52 struct nouveau_fb_tile
*tile
= &pfb
->tile
.region
[i
];
53 struct nouveau_engine
*engine
;
55 nouveau_fence_unref(®
->fence
);
58 pfb
->tile
.fini(pfb
, i
, tile
);
61 pfb
->tile
.init(pfb
, i
, addr
, size
, pitch
, flags
, tile
);
63 pfb
->tile
.prog(pfb
, i
, tile
);
65 if ((engine
= nouveau_engine(pfb
, NVDEV_ENGINE_GR
)))
66 engine
->tile_prog(engine
, i
);
67 if ((engine
= nouveau_engine(pfb
, NVDEV_ENGINE_MPEG
)))
68 engine
->tile_prog(engine
, i
);
71 static struct nouveau_drm_tile
*
72 nv10_bo_get_tile_region(struct drm_device
*dev
, int i
)
74 struct nouveau_drm
*drm
= nouveau_drm(dev
);
75 struct nouveau_drm_tile
*tile
= &drm
->tile
.reg
[i
];
77 spin_lock(&drm
->tile
.lock
);
80 (!tile
->fence
|| nouveau_fence_done(tile
->fence
)))
85 spin_unlock(&drm
->tile
.lock
);
90 nv10_bo_put_tile_region(struct drm_device
*dev
, struct nouveau_drm_tile
*tile
,
91 struct nouveau_fence
*fence
)
93 struct nouveau_drm
*drm
= nouveau_drm(dev
);
96 spin_lock(&drm
->tile
.lock
);
97 tile
->fence
= nouveau_fence_ref(fence
);
99 spin_unlock(&drm
->tile
.lock
);
103 static struct nouveau_drm_tile
*
104 nv10_bo_set_tiling(struct drm_device
*dev
, u32 addr
,
105 u32 size
, u32 pitch
, u32 flags
)
107 struct nouveau_drm
*drm
= nouveau_drm(dev
);
108 struct nouveau_fb
*pfb
= nvkm_fb(&drm
->device
);
109 struct nouveau_drm_tile
*tile
, *found
= NULL
;
112 for (i
= 0; i
< pfb
->tile
.regions
; i
++) {
113 tile
= nv10_bo_get_tile_region(dev
, i
);
115 if (pitch
&& !found
) {
119 } else if (tile
&& pfb
->tile
.region
[i
].pitch
) {
120 /* Kill an unused tile region. */
121 nv10_bo_update_tile_region(dev
, tile
, 0, 0, 0, 0);
124 nv10_bo_put_tile_region(dev
, tile
, NULL
);
128 nv10_bo_update_tile_region(dev
, found
, addr
, size
,
134 nouveau_bo_del_ttm(struct ttm_buffer_object
*bo
)
136 struct nouveau_drm
*drm
= nouveau_bdev(bo
->bdev
);
137 struct drm_device
*dev
= drm
->dev
;
138 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
140 if (unlikely(nvbo
->gem
.filp
))
141 DRM_ERROR("bo %p still attached to GEM object\n", bo
);
142 WARN_ON(nvbo
->pin_refcnt
> 0);
143 nv10_bo_put_tile_region(dev
, nvbo
->tile
, NULL
);
148 nouveau_bo_fixup_align(struct nouveau_bo
*nvbo
, u32 flags
,
149 int *align
, int *size
)
151 struct nouveau_drm
*drm
= nouveau_bdev(nvbo
->bo
.bdev
);
152 struct nvif_device
*device
= &drm
->device
;
154 if (device
->info
.family
< NV_DEVICE_INFO_V0_TESLA
) {
155 if (nvbo
->tile_mode
) {
156 if (device
->info
.chipset
>= 0x40) {
158 *size
= roundup(*size
, 64 * nvbo
->tile_mode
);
160 } else if (device
->info
.chipset
>= 0x30) {
162 *size
= roundup(*size
, 64 * nvbo
->tile_mode
);
164 } else if (device
->info
.chipset
>= 0x20) {
166 *size
= roundup(*size
, 64 * nvbo
->tile_mode
);
168 } else if (device
->info
.chipset
>= 0x10) {
170 *size
= roundup(*size
, 32 * nvbo
->tile_mode
);
174 *size
= roundup(*size
, (1 << nvbo
->page_shift
));
175 *align
= max((1 << nvbo
->page_shift
), *align
);
178 *size
= roundup(*size
, PAGE_SIZE
);
182 nouveau_bo_new(struct drm_device
*dev
, int size
, int align
,
183 uint32_t flags
, uint32_t tile_mode
, uint32_t tile_flags
,
185 struct nouveau_bo
**pnvbo
)
187 struct nouveau_drm
*drm
= nouveau_drm(dev
);
188 struct nouveau_bo
*nvbo
;
191 int type
= ttm_bo_type_device
;
196 lpg_shift
= drm
->client
.vm
->vmm
->lpg_shift
;
197 max_size
= INT_MAX
& ~((1 << lpg_shift
) - 1);
199 if (size
<= 0 || size
> max_size
) {
200 NV_WARN(drm
, "skipped size %x\n", (u32
)size
);
205 type
= ttm_bo_type_sg
;
207 nvbo
= kzalloc(sizeof(struct nouveau_bo
), GFP_KERNEL
);
210 INIT_LIST_HEAD(&nvbo
->head
);
211 INIT_LIST_HEAD(&nvbo
->entry
);
212 INIT_LIST_HEAD(&nvbo
->vma_list
);
213 nvbo
->tile_mode
= tile_mode
;
214 nvbo
->tile_flags
= tile_flags
;
215 nvbo
->bo
.bdev
= &drm
->ttm
.bdev
;
217 nvbo
->page_shift
= 12;
218 if (drm
->client
.vm
) {
219 if (!(flags
& TTM_PL_FLAG_TT
) && size
> 256 * 1024)
220 nvbo
->page_shift
= drm
->client
.vm
->vmm
->lpg_shift
;
223 nouveau_bo_fixup_align(nvbo
, flags
, &align
, &size
);
224 nvbo
->bo
.mem
.num_pages
= size
>> PAGE_SHIFT
;
225 nouveau_bo_placement_set(nvbo
, flags
, 0);
227 acc_size
= ttm_bo_dma_acc_size(&drm
->ttm
.bdev
, size
,
228 sizeof(struct nouveau_bo
));
230 ret
= ttm_bo_init(&drm
->ttm
.bdev
, &nvbo
->bo
, size
,
231 type
, &nvbo
->placement
,
232 align
>> PAGE_SHIFT
, false, NULL
, acc_size
, sg
,
235 /* ttm will call nouveau_bo_del_ttm if it fails.. */
244 set_placement_list(uint32_t *pl
, unsigned *n
, uint32_t type
, uint32_t flags
)
248 if (type
& TTM_PL_FLAG_VRAM
)
249 pl
[(*n
)++] = TTM_PL_FLAG_VRAM
| flags
;
250 if (type
& TTM_PL_FLAG_TT
)
251 pl
[(*n
)++] = TTM_PL_FLAG_TT
| flags
;
252 if (type
& TTM_PL_FLAG_SYSTEM
)
253 pl
[(*n
)++] = TTM_PL_FLAG_SYSTEM
| flags
;
257 set_placement_range(struct nouveau_bo
*nvbo
, uint32_t type
)
259 struct nouveau_drm
*drm
= nouveau_bdev(nvbo
->bo
.bdev
);
260 struct nouveau_fb
*pfb
= nvkm_fb(&drm
->device
);
261 u32 vram_pages
= pfb
->ram
->size
>> PAGE_SHIFT
;
263 if (drm
->device
.info
.family
== NV_DEVICE_INFO_V0_CELSIUS
&&
264 nvbo
->tile_mode
&& (type
& TTM_PL_FLAG_VRAM
) &&
265 nvbo
->bo
.mem
.num_pages
< vram_pages
/ 4) {
267 * Make sure that the color and depth buffers are handled
268 * by independent memory controller units. Up to a 9x
269 * speed up when alpha-blending and depth-test are enabled
272 if (nvbo
->tile_flags
& NOUVEAU_GEM_TILE_ZETA
) {
273 nvbo
->placement
.fpfn
= vram_pages
/ 2;
274 nvbo
->placement
.lpfn
= ~0;
276 nvbo
->placement
.fpfn
= 0;
277 nvbo
->placement
.lpfn
= vram_pages
/ 2;
283 nouveau_bo_placement_set(struct nouveau_bo
*nvbo
, uint32_t type
, uint32_t busy
)
285 struct ttm_placement
*pl
= &nvbo
->placement
;
286 uint32_t flags
= TTM_PL_MASK_CACHING
|
287 (nvbo
->pin_refcnt
? TTM_PL_FLAG_NO_EVICT
: 0);
289 pl
->placement
= nvbo
->placements
;
290 set_placement_list(nvbo
->placements
, &pl
->num_placement
,
293 pl
->busy_placement
= nvbo
->busy_placements
;
294 set_placement_list(nvbo
->busy_placements
, &pl
->num_busy_placement
,
297 set_placement_range(nvbo
, type
);
301 nouveau_bo_pin(struct nouveau_bo
*nvbo
, uint32_t memtype
)
303 struct nouveau_drm
*drm
= nouveau_bdev(nvbo
->bo
.bdev
);
304 struct ttm_buffer_object
*bo
= &nvbo
->bo
;
307 ret
= ttm_bo_reserve(bo
, false, false, false, NULL
);
311 if (nvbo
->pin_refcnt
&& !(memtype
& (1 << bo
->mem
.mem_type
))) {
312 NV_ERROR(drm
, "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo
,
313 1 << bo
->mem
.mem_type
, memtype
);
318 if (nvbo
->pin_refcnt
++)
321 nouveau_bo_placement_set(nvbo
, memtype
, 0);
323 ret
= nouveau_bo_validate(nvbo
, false, false);
325 switch (bo
->mem
.mem_type
) {
327 drm
->gem
.vram_available
-= bo
->mem
.size
;
330 drm
->gem
.gart_available
-= bo
->mem
.size
;
337 ttm_bo_unreserve(bo
);
342 nouveau_bo_unpin(struct nouveau_bo
*nvbo
)
344 struct nouveau_drm
*drm
= nouveau_bdev(nvbo
->bo
.bdev
);
345 struct ttm_buffer_object
*bo
= &nvbo
->bo
;
348 ret
= ttm_bo_reserve(bo
, false, false, false, NULL
);
352 ref
= --nvbo
->pin_refcnt
;
353 WARN_ON_ONCE(ref
< 0);
357 nouveau_bo_placement_set(nvbo
, bo
->mem
.placement
, 0);
359 ret
= nouveau_bo_validate(nvbo
, false, false);
361 switch (bo
->mem
.mem_type
) {
363 drm
->gem
.vram_available
+= bo
->mem
.size
;
366 drm
->gem
.gart_available
+= bo
->mem
.size
;
374 ttm_bo_unreserve(bo
);
379 nouveau_bo_map(struct nouveau_bo
*nvbo
)
383 ret
= ttm_bo_reserve(&nvbo
->bo
, false, false, false, NULL
);
387 ret
= ttm_bo_kmap(&nvbo
->bo
, 0, nvbo
->bo
.mem
.num_pages
, &nvbo
->kmap
);
388 ttm_bo_unreserve(&nvbo
->bo
);
393 nouveau_bo_unmap(struct nouveau_bo
*nvbo
)
396 ttm_bo_kunmap(&nvbo
->kmap
);
400 nouveau_bo_validate(struct nouveau_bo
*nvbo
, bool interruptible
,
405 ret
= ttm_bo_validate(&nvbo
->bo
, &nvbo
->placement
,
406 interruptible
, no_wait_gpu
);
414 nouveau_bo_rd16(struct nouveau_bo
*nvbo
, unsigned index
)
417 u16
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
420 return ioread16_native((void __force __iomem
*)mem
);
426 nouveau_bo_wr16(struct nouveau_bo
*nvbo
, unsigned index
, u16 val
)
429 u16
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
432 iowrite16_native(val
, (void __force __iomem
*)mem
);
438 nouveau_bo_rd32(struct nouveau_bo
*nvbo
, unsigned index
)
441 u32
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
444 return ioread32_native((void __force __iomem
*)mem
);
450 nouveau_bo_wr32(struct nouveau_bo
*nvbo
, unsigned index
, u32 val
)
453 u32
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
456 iowrite32_native(val
, (void __force __iomem
*)mem
);
461 static struct ttm_tt
*
462 nouveau_ttm_tt_create(struct ttm_bo_device
*bdev
, unsigned long size
,
463 uint32_t page_flags
, struct page
*dummy_read
)
466 struct nouveau_drm
*drm
= nouveau_bdev(bdev
);
467 struct drm_device
*dev
= drm
->dev
;
469 if (drm
->agp
.stat
== ENABLED
) {
470 return ttm_agp_tt_create(bdev
, dev
->agp
->bridge
, size
,
471 page_flags
, dummy_read
);
475 return nouveau_sgdma_create_ttm(bdev
, size
, page_flags
, dummy_read
);
479 nouveau_bo_invalidate_caches(struct ttm_bo_device
*bdev
, uint32_t flags
)
481 /* We'll do this from user space. */
486 nouveau_bo_init_mem_type(struct ttm_bo_device
*bdev
, uint32_t type
,
487 struct ttm_mem_type_manager
*man
)
489 struct nouveau_drm
*drm
= nouveau_bdev(bdev
);
493 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
;
494 man
->available_caching
= TTM_PL_MASK_CACHING
;
495 man
->default_caching
= TTM_PL_FLAG_CACHED
;
498 man
->flags
= TTM_MEMTYPE_FLAG_FIXED
|
499 TTM_MEMTYPE_FLAG_MAPPABLE
;
500 man
->available_caching
= TTM_PL_FLAG_UNCACHED
|
502 man
->default_caching
= TTM_PL_FLAG_WC
;
504 if (drm
->device
.info
.family
>= NV_DEVICE_INFO_V0_TESLA
) {
505 /* Some BARs do not support being ioremapped WC */
506 if (nvkm_bar(&drm
->device
)->iomap_uncached
) {
507 man
->available_caching
= TTM_PL_FLAG_UNCACHED
;
508 man
->default_caching
= TTM_PL_FLAG_UNCACHED
;
511 man
->func
= &nouveau_vram_manager
;
512 man
->io_reserve_fastpath
= false;
513 man
->use_io_reserve_lru
= true;
515 man
->func
= &ttm_bo_manager_func
;
519 if (drm
->device
.info
.family
>= NV_DEVICE_INFO_V0_TESLA
)
520 man
->func
= &nouveau_gart_manager
;
522 if (drm
->agp
.stat
!= ENABLED
)
523 man
->func
= &nv04_gart_manager
;
525 man
->func
= &ttm_bo_manager_func
;
527 if (drm
->agp
.stat
== ENABLED
) {
528 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
;
529 man
->available_caching
= TTM_PL_FLAG_UNCACHED
|
531 man
->default_caching
= TTM_PL_FLAG_WC
;
533 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
|
534 TTM_MEMTYPE_FLAG_CMA
;
535 man
->available_caching
= TTM_PL_MASK_CACHING
;
536 man
->default_caching
= TTM_PL_FLAG_CACHED
;
547 nouveau_bo_evict_flags(struct ttm_buffer_object
*bo
, struct ttm_placement
*pl
)
549 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
551 switch (bo
->mem
.mem_type
) {
553 nouveau_bo_placement_set(nvbo
, TTM_PL_FLAG_TT
,
557 nouveau_bo_placement_set(nvbo
, TTM_PL_FLAG_SYSTEM
, 0);
561 *pl
= nvbo
->placement
;
566 nve0_bo_move_init(struct nouveau_channel
*chan
, u32 handle
)
568 int ret
= RING_SPACE(chan
, 2);
570 BEGIN_NVC0(chan
, NvSubCopy
, 0x0000, 1);
571 OUT_RING (chan
, handle
& 0x0000ffff);
578 nve0_bo_move_copy(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
579 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
581 struct nouveau_mem
*node
= old_mem
->mm_node
;
582 int ret
= RING_SPACE(chan
, 10);
584 BEGIN_NVC0(chan
, NvSubCopy
, 0x0400, 8);
585 OUT_RING (chan
, upper_32_bits(node
->vma
[0].offset
));
586 OUT_RING (chan
, lower_32_bits(node
->vma
[0].offset
));
587 OUT_RING (chan
, upper_32_bits(node
->vma
[1].offset
));
588 OUT_RING (chan
, lower_32_bits(node
->vma
[1].offset
));
589 OUT_RING (chan
, PAGE_SIZE
);
590 OUT_RING (chan
, PAGE_SIZE
);
591 OUT_RING (chan
, PAGE_SIZE
);
592 OUT_RING (chan
, new_mem
->num_pages
);
593 BEGIN_IMC0(chan
, NvSubCopy
, 0x0300, 0x0386);
599 nvc0_bo_move_init(struct nouveau_channel
*chan
, u32 handle
)
601 int ret
= RING_SPACE(chan
, 2);
603 BEGIN_NVC0(chan
, NvSubCopy
, 0x0000, 1);
604 OUT_RING (chan
, handle
);
610 nvc0_bo_move_copy(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
611 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
613 struct nouveau_mem
*node
= old_mem
->mm_node
;
614 u64 src_offset
= node
->vma
[0].offset
;
615 u64 dst_offset
= node
->vma
[1].offset
;
616 u32 page_count
= new_mem
->num_pages
;
619 page_count
= new_mem
->num_pages
;
621 int line_count
= (page_count
> 8191) ? 8191 : page_count
;
623 ret
= RING_SPACE(chan
, 11);
627 BEGIN_NVC0(chan
, NvSubCopy
, 0x030c, 8);
628 OUT_RING (chan
, upper_32_bits(src_offset
));
629 OUT_RING (chan
, lower_32_bits(src_offset
));
630 OUT_RING (chan
, upper_32_bits(dst_offset
));
631 OUT_RING (chan
, lower_32_bits(dst_offset
));
632 OUT_RING (chan
, PAGE_SIZE
);
633 OUT_RING (chan
, PAGE_SIZE
);
634 OUT_RING (chan
, PAGE_SIZE
);
635 OUT_RING (chan
, line_count
);
636 BEGIN_NVC0(chan
, NvSubCopy
, 0x0300, 1);
637 OUT_RING (chan
, 0x00000110);
639 page_count
-= line_count
;
640 src_offset
+= (PAGE_SIZE
* line_count
);
641 dst_offset
+= (PAGE_SIZE
* line_count
);
648 nvc0_bo_move_m2mf(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
649 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
651 struct nouveau_mem
*node
= old_mem
->mm_node
;
652 u64 src_offset
= node
->vma
[0].offset
;
653 u64 dst_offset
= node
->vma
[1].offset
;
654 u32 page_count
= new_mem
->num_pages
;
657 page_count
= new_mem
->num_pages
;
659 int line_count
= (page_count
> 2047) ? 2047 : page_count
;
661 ret
= RING_SPACE(chan
, 12);
665 BEGIN_NVC0(chan
, NvSubCopy
, 0x0238, 2);
666 OUT_RING (chan
, upper_32_bits(dst_offset
));
667 OUT_RING (chan
, lower_32_bits(dst_offset
));
668 BEGIN_NVC0(chan
, NvSubCopy
, 0x030c, 6);
669 OUT_RING (chan
, upper_32_bits(src_offset
));
670 OUT_RING (chan
, lower_32_bits(src_offset
));
671 OUT_RING (chan
, PAGE_SIZE
); /* src_pitch */
672 OUT_RING (chan
, PAGE_SIZE
); /* dst_pitch */
673 OUT_RING (chan
, PAGE_SIZE
); /* line_length */
674 OUT_RING (chan
, line_count
);
675 BEGIN_NVC0(chan
, NvSubCopy
, 0x0300, 1);
676 OUT_RING (chan
, 0x00100110);
678 page_count
-= line_count
;
679 src_offset
+= (PAGE_SIZE
* line_count
);
680 dst_offset
+= (PAGE_SIZE
* line_count
);
687 nva3_bo_move_copy(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
688 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
690 struct nouveau_mem
*node
= old_mem
->mm_node
;
691 u64 src_offset
= node
->vma
[0].offset
;
692 u64 dst_offset
= node
->vma
[1].offset
;
693 u32 page_count
= new_mem
->num_pages
;
696 page_count
= new_mem
->num_pages
;
698 int line_count
= (page_count
> 8191) ? 8191 : page_count
;
700 ret
= RING_SPACE(chan
, 11);
704 BEGIN_NV04(chan
, NvSubCopy
, 0x030c, 8);
705 OUT_RING (chan
, upper_32_bits(src_offset
));
706 OUT_RING (chan
, lower_32_bits(src_offset
));
707 OUT_RING (chan
, upper_32_bits(dst_offset
));
708 OUT_RING (chan
, lower_32_bits(dst_offset
));
709 OUT_RING (chan
, PAGE_SIZE
);
710 OUT_RING (chan
, PAGE_SIZE
);
711 OUT_RING (chan
, PAGE_SIZE
);
712 OUT_RING (chan
, line_count
);
713 BEGIN_NV04(chan
, NvSubCopy
, 0x0300, 1);
714 OUT_RING (chan
, 0x00000110);
716 page_count
-= line_count
;
717 src_offset
+= (PAGE_SIZE
* line_count
);
718 dst_offset
+= (PAGE_SIZE
* line_count
);
725 nv98_bo_move_exec(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
726 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
728 struct nouveau_mem
*node
= old_mem
->mm_node
;
729 int ret
= RING_SPACE(chan
, 7);
731 BEGIN_NV04(chan
, NvSubCopy
, 0x0320, 6);
732 OUT_RING (chan
, upper_32_bits(node
->vma
[0].offset
));
733 OUT_RING (chan
, lower_32_bits(node
->vma
[0].offset
));
734 OUT_RING (chan
, upper_32_bits(node
->vma
[1].offset
));
735 OUT_RING (chan
, lower_32_bits(node
->vma
[1].offset
));
736 OUT_RING (chan
, 0x00000000 /* COPY */);
737 OUT_RING (chan
, new_mem
->num_pages
<< PAGE_SHIFT
);
743 nv84_bo_move_exec(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
744 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
746 struct nouveau_mem
*node
= old_mem
->mm_node
;
747 int ret
= RING_SPACE(chan
, 7);
749 BEGIN_NV04(chan
, NvSubCopy
, 0x0304, 6);
750 OUT_RING (chan
, new_mem
->num_pages
<< PAGE_SHIFT
);
751 OUT_RING (chan
, upper_32_bits(node
->vma
[0].offset
));
752 OUT_RING (chan
, lower_32_bits(node
->vma
[0].offset
));
753 OUT_RING (chan
, upper_32_bits(node
->vma
[1].offset
));
754 OUT_RING (chan
, lower_32_bits(node
->vma
[1].offset
));
755 OUT_RING (chan
, 0x00000000 /* MODE_COPY, QUERY_NONE */);
761 nv50_bo_move_init(struct nouveau_channel
*chan
, u32 handle
)
763 int ret
= RING_SPACE(chan
, 6);
765 BEGIN_NV04(chan
, NvSubCopy
, 0x0000, 1);
766 OUT_RING (chan
, handle
);
767 BEGIN_NV04(chan
, NvSubCopy
, 0x0180, 3);
768 OUT_RING (chan
, chan
->drm
->ntfy
.handle
);
769 OUT_RING (chan
, chan
->vram
.handle
);
770 OUT_RING (chan
, chan
->vram
.handle
);
777 nv50_bo_move_m2mf(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
778 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
780 struct nouveau_mem
*node
= old_mem
->mm_node
;
781 u64 length
= (new_mem
->num_pages
<< PAGE_SHIFT
);
782 u64 src_offset
= node
->vma
[0].offset
;
783 u64 dst_offset
= node
->vma
[1].offset
;
784 int src_tiled
= !!node
->memtype
;
785 int dst_tiled
= !!((struct nouveau_mem
*)new_mem
->mm_node
)->memtype
;
789 u32 amount
, stride
, height
;
791 ret
= RING_SPACE(chan
, 18 + 6 * (src_tiled
+ dst_tiled
));
795 amount
= min(length
, (u64
)(4 * 1024 * 1024));
797 height
= amount
/ stride
;
800 BEGIN_NV04(chan
, NvSubCopy
, 0x0200, 7);
803 OUT_RING (chan
, stride
);
804 OUT_RING (chan
, height
);
809 BEGIN_NV04(chan
, NvSubCopy
, 0x0200, 1);
813 BEGIN_NV04(chan
, NvSubCopy
, 0x021c, 7);
816 OUT_RING (chan
, stride
);
817 OUT_RING (chan
, height
);
822 BEGIN_NV04(chan
, NvSubCopy
, 0x021c, 1);
826 BEGIN_NV04(chan
, NvSubCopy
, 0x0238, 2);
827 OUT_RING (chan
, upper_32_bits(src_offset
));
828 OUT_RING (chan
, upper_32_bits(dst_offset
));
829 BEGIN_NV04(chan
, NvSubCopy
, 0x030c, 8);
830 OUT_RING (chan
, lower_32_bits(src_offset
));
831 OUT_RING (chan
, lower_32_bits(dst_offset
));
832 OUT_RING (chan
, stride
);
833 OUT_RING (chan
, stride
);
834 OUT_RING (chan
, stride
);
835 OUT_RING (chan
, height
);
836 OUT_RING (chan
, 0x00000101);
837 OUT_RING (chan
, 0x00000000);
838 BEGIN_NV04(chan
, NvSubCopy
, NV_MEMORY_TO_MEMORY_FORMAT_NOP
, 1);
842 src_offset
+= amount
;
843 dst_offset
+= amount
;
850 nv04_bo_move_init(struct nouveau_channel
*chan
, u32 handle
)
852 int ret
= RING_SPACE(chan
, 4);
854 BEGIN_NV04(chan
, NvSubCopy
, 0x0000, 1);
855 OUT_RING (chan
, handle
);
856 BEGIN_NV04(chan
, NvSubCopy
, 0x0180, 1);
857 OUT_RING (chan
, chan
->drm
->ntfy
.handle
);
863 static inline uint32_t
864 nouveau_bo_mem_ctxdma(struct ttm_buffer_object
*bo
,
865 struct nouveau_channel
*chan
, struct ttm_mem_reg
*mem
)
867 if (mem
->mem_type
== TTM_PL_TT
)
869 return chan
->vram
.handle
;
873 nv04_bo_move_m2mf(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
874 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
876 u32 src_offset
= old_mem
->start
<< PAGE_SHIFT
;
877 u32 dst_offset
= new_mem
->start
<< PAGE_SHIFT
;
878 u32 page_count
= new_mem
->num_pages
;
881 ret
= RING_SPACE(chan
, 3);
885 BEGIN_NV04(chan
, NvSubCopy
, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE
, 2);
886 OUT_RING (chan
, nouveau_bo_mem_ctxdma(bo
, chan
, old_mem
));
887 OUT_RING (chan
, nouveau_bo_mem_ctxdma(bo
, chan
, new_mem
));
889 page_count
= new_mem
->num_pages
;
891 int line_count
= (page_count
> 2047) ? 2047 : page_count
;
893 ret
= RING_SPACE(chan
, 11);
897 BEGIN_NV04(chan
, NvSubCopy
,
898 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN
, 8);
899 OUT_RING (chan
, src_offset
);
900 OUT_RING (chan
, dst_offset
);
901 OUT_RING (chan
, PAGE_SIZE
); /* src_pitch */
902 OUT_RING (chan
, PAGE_SIZE
); /* dst_pitch */
903 OUT_RING (chan
, PAGE_SIZE
); /* line_length */
904 OUT_RING (chan
, line_count
);
905 OUT_RING (chan
, 0x00000101);
906 OUT_RING (chan
, 0x00000000);
907 BEGIN_NV04(chan
, NvSubCopy
, NV_MEMORY_TO_MEMORY_FORMAT_NOP
, 1);
910 page_count
-= line_count
;
911 src_offset
+= (PAGE_SIZE
* line_count
);
912 dst_offset
+= (PAGE_SIZE
* line_count
);
919 nouveau_bo_move_prep(struct nouveau_drm
*drm
, struct ttm_buffer_object
*bo
,
920 struct ttm_mem_reg
*mem
)
922 struct nouveau_mem
*old_node
= bo
->mem
.mm_node
;
923 struct nouveau_mem
*new_node
= mem
->mm_node
;
924 u64 size
= (u64
)mem
->num_pages
<< PAGE_SHIFT
;
927 ret
= nouveau_vm_get(drm
->client
.vm
, size
, old_node
->page_shift
,
928 NV_MEM_ACCESS_RW
, &old_node
->vma
[0]);
932 ret
= nouveau_vm_get(drm
->client
.vm
, size
, new_node
->page_shift
,
933 NV_MEM_ACCESS_RW
, &old_node
->vma
[1]);
935 nouveau_vm_put(&old_node
->vma
[0]);
939 nouveau_vm_map(&old_node
->vma
[0], old_node
);
940 nouveau_vm_map(&old_node
->vma
[1], new_node
);
945 nouveau_bo_move_m2mf(struct ttm_buffer_object
*bo
, int evict
, bool intr
,
946 bool no_wait_gpu
, struct ttm_mem_reg
*new_mem
)
948 struct nouveau_drm
*drm
= nouveau_bdev(bo
->bdev
);
949 struct nouveau_channel
*chan
= drm
->ttm
.chan
;
950 struct nouveau_cli
*cli
= (void *)nvif_client(&chan
->device
->base
);
951 struct nouveau_fence
*fence
;
954 /* create temporary vmas for the transfer and attach them to the
955 * old nouveau_mem node, these will get cleaned up after ttm has
956 * destroyed the ttm_mem_reg
958 if (drm
->device
.info
.family
>= NV_DEVICE_INFO_V0_TESLA
) {
959 ret
= nouveau_bo_move_prep(drm
, bo
, new_mem
);
964 mutex_lock_nested(&cli
->mutex
, SINGLE_DEPTH_NESTING
);
965 ret
= nouveau_fence_sync(bo
->sync_obj
, chan
);
967 ret
= drm
->ttm
.move(chan
, bo
, &bo
->mem
, new_mem
);
969 ret
= nouveau_fence_new(chan
, false, &fence
);
971 ret
= ttm_bo_move_accel_cleanup(bo
, fence
,
975 nouveau_fence_unref(&fence
);
979 mutex_unlock(&cli
->mutex
);
984 nouveau_bo_move_init(struct nouveau_drm
*drm
)
986 static const struct {
990 int (*exec
)(struct nouveau_channel
*,
991 struct ttm_buffer_object
*,
992 struct ttm_mem_reg
*, struct ttm_mem_reg
*);
993 int (*init
)(struct nouveau_channel
*, u32 handle
);
995 { "COPY", 4, 0xa0b5, nve0_bo_move_copy
, nve0_bo_move_init
},
996 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy
, nvc0_bo_move_init
},
997 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy
, nvc0_bo_move_init
},
998 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy
, nvc0_bo_move_init
},
999 { "COPY", 0, 0x85b5, nva3_bo_move_copy
, nv50_bo_move_init
},
1000 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec
, nv50_bo_move_init
},
1001 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf
, nvc0_bo_move_init
},
1002 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf
, nv50_bo_move_init
},
1003 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf
, nv04_bo_move_init
},
1005 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec
, nv50_bo_move_init
},
1006 }, *mthd
= _methods
;
1007 const char *name
= "CPU";
1011 struct nouveau_channel
*chan
;
1016 chan
= drm
->channel
;
1020 ret
= nvif_object_init(chan
->object
, NULL
,
1021 mthd
->oclass
| (mthd
->engine
<< 16),
1022 mthd
->oclass
, NULL
, 0,
1025 ret
= mthd
->init(chan
, drm
->ttm
.copy
.handle
);
1027 nvif_object_fini(&drm
->ttm
.copy
);
1031 drm
->ttm
.move
= mthd
->exec
;
1032 drm
->ttm
.chan
= chan
;
1036 } while ((++mthd
)->exec
);
1038 NV_INFO(drm
, "MM: using %s for buffer copies\n", name
);
1042 nouveau_bo_move_flipd(struct ttm_buffer_object
*bo
, bool evict
, bool intr
,
1043 bool no_wait_gpu
, struct ttm_mem_reg
*new_mem
)
1045 u32 placement_memtype
= TTM_PL_FLAG_TT
| TTM_PL_MASK_CACHING
;
1046 struct ttm_placement placement
;
1047 struct ttm_mem_reg tmp_mem
;
1050 placement
.fpfn
= placement
.lpfn
= 0;
1051 placement
.num_placement
= placement
.num_busy_placement
= 1;
1052 placement
.placement
= placement
.busy_placement
= &placement_memtype
;
1055 tmp_mem
.mm_node
= NULL
;
1056 ret
= ttm_bo_mem_space(bo
, &placement
, &tmp_mem
, intr
, no_wait_gpu
);
1060 ret
= ttm_tt_bind(bo
->ttm
, &tmp_mem
);
1064 ret
= nouveau_bo_move_m2mf(bo
, true, intr
, no_wait_gpu
, &tmp_mem
);
1068 ret
= ttm_bo_move_ttm(bo
, true, no_wait_gpu
, new_mem
);
1070 ttm_bo_mem_put(bo
, &tmp_mem
);
1075 nouveau_bo_move_flips(struct ttm_buffer_object
*bo
, bool evict
, bool intr
,
1076 bool no_wait_gpu
, struct ttm_mem_reg
*new_mem
)
1078 u32 placement_memtype
= TTM_PL_FLAG_TT
| TTM_PL_MASK_CACHING
;
1079 struct ttm_placement placement
;
1080 struct ttm_mem_reg tmp_mem
;
1083 placement
.fpfn
= placement
.lpfn
= 0;
1084 placement
.num_placement
= placement
.num_busy_placement
= 1;
1085 placement
.placement
= placement
.busy_placement
= &placement_memtype
;
1088 tmp_mem
.mm_node
= NULL
;
1089 ret
= ttm_bo_mem_space(bo
, &placement
, &tmp_mem
, intr
, no_wait_gpu
);
1093 ret
= ttm_bo_move_ttm(bo
, true, no_wait_gpu
, &tmp_mem
);
1097 ret
= nouveau_bo_move_m2mf(bo
, true, intr
, no_wait_gpu
, new_mem
);
1102 ttm_bo_mem_put(bo
, &tmp_mem
);
1107 nouveau_bo_move_ntfy(struct ttm_buffer_object
*bo
, struct ttm_mem_reg
*new_mem
)
1109 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
1110 struct nouveau_vma
*vma
;
1112 /* ttm can now (stupidly) pass the driver bos it didn't create... */
1113 if (bo
->destroy
!= nouveau_bo_del_ttm
)
1116 list_for_each_entry(vma
, &nvbo
->vma_list
, head
) {
1117 if (new_mem
&& new_mem
->mem_type
!= TTM_PL_SYSTEM
&&
1118 (new_mem
->mem_type
== TTM_PL_VRAM
||
1119 nvbo
->page_shift
!= vma
->vm
->vmm
->lpg_shift
)) {
1120 nouveau_vm_map(vma
, new_mem
->mm_node
);
1122 nouveau_vm_unmap(vma
);
1128 nouveau_bo_vm_bind(struct ttm_buffer_object
*bo
, struct ttm_mem_reg
*new_mem
,
1129 struct nouveau_drm_tile
**new_tile
)
1131 struct nouveau_drm
*drm
= nouveau_bdev(bo
->bdev
);
1132 struct drm_device
*dev
= drm
->dev
;
1133 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
1134 u64 offset
= new_mem
->start
<< PAGE_SHIFT
;
1137 if (new_mem
->mem_type
!= TTM_PL_VRAM
)
1140 if (drm
->device
.info
.family
>= NV_DEVICE_INFO_V0_CELSIUS
) {
1141 *new_tile
= nv10_bo_set_tiling(dev
, offset
, new_mem
->size
,
1150 nouveau_bo_vm_cleanup(struct ttm_buffer_object
*bo
,
1151 struct nouveau_drm_tile
*new_tile
,
1152 struct nouveau_drm_tile
**old_tile
)
1154 struct nouveau_drm
*drm
= nouveau_bdev(bo
->bdev
);
1155 struct drm_device
*dev
= drm
->dev
;
1157 nv10_bo_put_tile_region(dev
, *old_tile
, bo
->sync_obj
);
1158 *old_tile
= new_tile
;
1162 nouveau_bo_move(struct ttm_buffer_object
*bo
, bool evict
, bool intr
,
1163 bool no_wait_gpu
, struct ttm_mem_reg
*new_mem
)
1165 struct nouveau_drm
*drm
= nouveau_bdev(bo
->bdev
);
1166 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
1167 struct ttm_mem_reg
*old_mem
= &bo
->mem
;
1168 struct nouveau_drm_tile
*new_tile
= NULL
;
1171 if (drm
->device
.info
.family
< NV_DEVICE_INFO_V0_TESLA
) {
1172 ret
= nouveau_bo_vm_bind(bo
, new_mem
, &new_tile
);
1178 if (old_mem
->mem_type
== TTM_PL_SYSTEM
&& !bo
->ttm
) {
1179 BUG_ON(bo
->mem
.mm_node
!= NULL
);
1181 new_mem
->mm_node
= NULL
;
1185 /* Hardware assisted copy. */
1186 if (drm
->ttm
.move
) {
1187 if (new_mem
->mem_type
== TTM_PL_SYSTEM
)
1188 ret
= nouveau_bo_move_flipd(bo
, evict
, intr
,
1189 no_wait_gpu
, new_mem
);
1190 else if (old_mem
->mem_type
== TTM_PL_SYSTEM
)
1191 ret
= nouveau_bo_move_flips(bo
, evict
, intr
,
1192 no_wait_gpu
, new_mem
);
1194 ret
= nouveau_bo_move_m2mf(bo
, evict
, intr
,
1195 no_wait_gpu
, new_mem
);
1200 /* Fallback to software copy. */
1201 spin_lock(&bo
->bdev
->fence_lock
);
1202 ret
= ttm_bo_wait(bo
, true, intr
, no_wait_gpu
);
1203 spin_unlock(&bo
->bdev
->fence_lock
);
1205 ret
= ttm_bo_move_memcpy(bo
, evict
, no_wait_gpu
, new_mem
);
1208 if (drm
->device
.info
.family
< NV_DEVICE_INFO_V0_TESLA
) {
1210 nouveau_bo_vm_cleanup(bo
, NULL
, &new_tile
);
1212 nouveau_bo_vm_cleanup(bo
, new_tile
, &nvbo
->tile
);
1219 nouveau_bo_verify_access(struct ttm_buffer_object
*bo
, struct file
*filp
)
1221 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
1223 return drm_vma_node_verify_access(&nvbo
->gem
.vma_node
, filp
);
1227 nouveau_ttm_io_mem_reserve(struct ttm_bo_device
*bdev
, struct ttm_mem_reg
*mem
)
1229 struct ttm_mem_type_manager
*man
= &bdev
->man
[mem
->mem_type
];
1230 struct nouveau_drm
*drm
= nouveau_bdev(bdev
);
1231 struct nouveau_mem
*node
= mem
->mm_node
;
1232 struct drm_device
*dev
= drm
->dev
;
1235 mem
->bus
.addr
= NULL
;
1236 mem
->bus
.offset
= 0;
1237 mem
->bus
.size
= mem
->num_pages
<< PAGE_SHIFT
;
1239 mem
->bus
.is_iomem
= false;
1240 if (!(man
->flags
& TTM_MEMTYPE_FLAG_MAPPABLE
))
1242 switch (mem
->mem_type
) {
1248 if (drm
->agp
.stat
== ENABLED
) {
1249 mem
->bus
.offset
= mem
->start
<< PAGE_SHIFT
;
1250 mem
->bus
.base
= drm
->agp
.base
;
1251 mem
->bus
.is_iomem
= !dev
->agp
->cant_use_aperture
;
1254 if (drm
->device
.info
.family
< NV_DEVICE_INFO_V0_TESLA
|| !node
->memtype
)
1257 /* fallthrough, tiled memory */
1259 mem
->bus
.offset
= mem
->start
<< PAGE_SHIFT
;
1260 mem
->bus
.base
= nv_device_resource_start(nvkm_device(&drm
->device
), 1);
1261 mem
->bus
.is_iomem
= true;
1262 if (drm
->device
.info
.family
>= NV_DEVICE_INFO_V0_TESLA
) {
1263 struct nouveau_bar
*bar
= nvkm_bar(&drm
->device
);
1265 ret
= bar
->umap(bar
, node
, NV_MEM_ACCESS_RW
,
1270 mem
->bus
.offset
= node
->bar_vma
.offset
;
1280 nouveau_ttm_io_mem_free(struct ttm_bo_device
*bdev
, struct ttm_mem_reg
*mem
)
1282 struct nouveau_drm
*drm
= nouveau_bdev(bdev
);
1283 struct nouveau_bar
*bar
= nvkm_bar(&drm
->device
);
1284 struct nouveau_mem
*node
= mem
->mm_node
;
1286 if (!node
->bar_vma
.node
)
1289 bar
->unmap(bar
, &node
->bar_vma
);
1293 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object
*bo
)
1295 struct nouveau_drm
*drm
= nouveau_bdev(bo
->bdev
);
1296 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
1297 struct nvif_device
*device
= &drm
->device
;
1298 u32 mappable
= nv_device_resource_len(nvkm_device(device
), 1) >> PAGE_SHIFT
;
1301 /* as long as the bo isn't in vram, and isn't tiled, we've got
1302 * nothing to do here.
1304 if (bo
->mem
.mem_type
!= TTM_PL_VRAM
) {
1305 if (drm
->device
.info
.family
< NV_DEVICE_INFO_V0_TESLA
||
1306 !nouveau_bo_tile_layout(nvbo
))
1309 if (bo
->mem
.mem_type
== TTM_PL_SYSTEM
) {
1310 nouveau_bo_placement_set(nvbo
, TTM_PL_TT
, 0);
1312 ret
= nouveau_bo_validate(nvbo
, false, false);
1319 /* make sure bo is in mappable vram */
1320 if (drm
->device
.info
.family
>= NV_DEVICE_INFO_V0_TESLA
||
1321 bo
->mem
.start
+ bo
->mem
.num_pages
< mappable
)
1325 nvbo
->placement
.fpfn
= 0;
1326 nvbo
->placement
.lpfn
= mappable
;
1327 nouveau_bo_placement_set(nvbo
, TTM_PL_FLAG_VRAM
, 0);
1328 return nouveau_bo_validate(nvbo
, false, false);
1332 nouveau_ttm_tt_populate(struct ttm_tt
*ttm
)
1334 struct ttm_dma_tt
*ttm_dma
= (void *)ttm
;
1335 struct nouveau_drm
*drm
;
1336 struct nouveau_device
*device
;
1337 struct drm_device
*dev
;
1338 struct device
*pdev
;
1341 bool slave
= !!(ttm
->page_flags
& TTM_PAGE_FLAG_SG
);
1343 if (ttm
->state
!= tt_unpopulated
)
1346 if (slave
&& ttm
->sg
) {
1347 /* make userspace faulting work */
1348 drm_prime_sg_to_page_addr_arrays(ttm
->sg
, ttm
->pages
,
1349 ttm_dma
->dma_address
, ttm
->num_pages
);
1350 ttm
->state
= tt_unbound
;
1354 drm
= nouveau_bdev(ttm
->bdev
);
1355 device
= nvkm_device(&drm
->device
);
1357 pdev
= nv_device_base(device
);
1360 if (drm
->agp
.stat
== ENABLED
) {
1361 return ttm_agp_tt_populate(ttm
);
1365 #ifdef CONFIG_SWIOTLB
1366 if (swiotlb_nr_tbl()) {
1367 return ttm_dma_populate((void *)ttm
, dev
->dev
);
1371 r
= ttm_pool_populate(ttm
);
1376 for (i
= 0; i
< ttm
->num_pages
; i
++) {
1379 addr
= dma_map_page(pdev
, ttm
->pages
[i
], 0, PAGE_SIZE
,
1382 if (dma_mapping_error(pdev
, addr
)) {
1384 dma_unmap_page(pdev
, ttm_dma
->dma_address
[i
],
1385 PAGE_SIZE
, DMA_BIDIRECTIONAL
);
1386 ttm_dma
->dma_address
[i
] = 0;
1388 ttm_pool_unpopulate(ttm
);
1392 ttm_dma
->dma_address
[i
] = addr
;
1398 nouveau_ttm_tt_unpopulate(struct ttm_tt
*ttm
)
1400 struct ttm_dma_tt
*ttm_dma
= (void *)ttm
;
1401 struct nouveau_drm
*drm
;
1402 struct nouveau_device
*device
;
1403 struct drm_device
*dev
;
1404 struct device
*pdev
;
1406 bool slave
= !!(ttm
->page_flags
& TTM_PAGE_FLAG_SG
);
1411 drm
= nouveau_bdev(ttm
->bdev
);
1412 device
= nvkm_device(&drm
->device
);
1414 pdev
= nv_device_base(device
);
1417 if (drm
->agp
.stat
== ENABLED
) {
1418 ttm_agp_tt_unpopulate(ttm
);
1423 #ifdef CONFIG_SWIOTLB
1424 if (swiotlb_nr_tbl()) {
1425 ttm_dma_unpopulate((void *)ttm
, dev
->dev
);
1430 for (i
= 0; i
< ttm
->num_pages
; i
++) {
1431 if (ttm_dma
->dma_address
[i
]) {
1432 dma_unmap_page(pdev
, ttm_dma
->dma_address
[i
], PAGE_SIZE
,
1437 ttm_pool_unpopulate(ttm
);
1441 nouveau_bo_fence(struct nouveau_bo
*nvbo
, struct nouveau_fence
*fence
)
1443 struct nouveau_fence
*new_fence
= nouveau_fence_ref(fence
);
1444 struct nouveau_fence
*old_fence
= NULL
;
1446 spin_lock(&nvbo
->bo
.bdev
->fence_lock
);
1447 old_fence
= nvbo
->bo
.sync_obj
;
1448 nvbo
->bo
.sync_obj
= new_fence
;
1449 spin_unlock(&nvbo
->bo
.bdev
->fence_lock
);
1451 nouveau_fence_unref(&old_fence
);
1455 nouveau_bo_fence_unref(void **sync_obj
)
1457 nouveau_fence_unref((struct nouveau_fence
**)sync_obj
);
1461 nouveau_bo_fence_ref(void *sync_obj
)
1463 return nouveau_fence_ref(sync_obj
);
1467 nouveau_bo_fence_signalled(void *sync_obj
)
1469 return nouveau_fence_done(sync_obj
);
1473 nouveau_bo_fence_wait(void *sync_obj
, bool lazy
, bool intr
)
1475 return nouveau_fence_wait(sync_obj
, lazy
, intr
);
1479 nouveau_bo_fence_flush(void *sync_obj
)
1484 struct ttm_bo_driver nouveau_bo_driver
= {
1485 .ttm_tt_create
= &nouveau_ttm_tt_create
,
1486 .ttm_tt_populate
= &nouveau_ttm_tt_populate
,
1487 .ttm_tt_unpopulate
= &nouveau_ttm_tt_unpopulate
,
1488 .invalidate_caches
= nouveau_bo_invalidate_caches
,
1489 .init_mem_type
= nouveau_bo_init_mem_type
,
1490 .evict_flags
= nouveau_bo_evict_flags
,
1491 .move_notify
= nouveau_bo_move_ntfy
,
1492 .move
= nouveau_bo_move
,
1493 .verify_access
= nouveau_bo_verify_access
,
1494 .sync_obj_signaled
= nouveau_bo_fence_signalled
,
1495 .sync_obj_wait
= nouveau_bo_fence_wait
,
1496 .sync_obj_flush
= nouveau_bo_fence_flush
,
1497 .sync_obj_unref
= nouveau_bo_fence_unref
,
1498 .sync_obj_ref
= nouveau_bo_fence_ref
,
1499 .fault_reserve_notify
= &nouveau_ttm_fault_reserve_notify
,
1500 .io_mem_reserve
= &nouveau_ttm_io_mem_reserve
,
1501 .io_mem_free
= &nouveau_ttm_io_mem_free
,
1504 struct nouveau_vma
*
1505 nouveau_bo_vma_find(struct nouveau_bo
*nvbo
, struct nouveau_vm
*vm
)
1507 struct nouveau_vma
*vma
;
1508 list_for_each_entry(vma
, &nvbo
->vma_list
, head
) {
1517 nouveau_bo_vma_add(struct nouveau_bo
*nvbo
, struct nouveau_vm
*vm
,
1518 struct nouveau_vma
*vma
)
1520 const u32 size
= nvbo
->bo
.mem
.num_pages
<< PAGE_SHIFT
;
1523 ret
= nouveau_vm_get(vm
, size
, nvbo
->page_shift
,
1524 NV_MEM_ACCESS_RW
, vma
);
1528 if ( nvbo
->bo
.mem
.mem_type
!= TTM_PL_SYSTEM
&&
1529 (nvbo
->bo
.mem
.mem_type
== TTM_PL_VRAM
||
1530 nvbo
->page_shift
!= vma
->vm
->vmm
->lpg_shift
))
1531 nouveau_vm_map(vma
, nvbo
->bo
.mem
.mm_node
);
1533 list_add_tail(&vma
->head
, &nvbo
->vma_list
);
1539 nouveau_bo_vma_del(struct nouveau_bo
*nvbo
, struct nouveau_vma
*vma
)
1542 if (nvbo
->bo
.mem
.mem_type
!= TTM_PL_SYSTEM
)
1543 nouveau_vm_unmap(vma
);
1544 nouveau_vm_put(vma
);
1545 list_del(&vma
->head
);