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459a44550ce59feee69f6240ae49d696b54363a7
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_bo.c
1 /*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24 /*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30 #include <core/engine.h>
31 #include <linux/swiotlb.h>
32
33 #include <subdev/fb.h>
34 #include <subdev/vm.h>
35 #include <subdev/bar.h>
36
37 #include "nouveau_drm.h"
38 #include "nouveau_dma.h"
39 #include "nouveau_fence.h"
40
41 #include "nouveau_bo.h"
42 #include "nouveau_ttm.h"
43 #include "nouveau_gem.h"
44
45 /*
46 * NV10-NV40 tiling helpers
47 */
48
49 static void
50 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
51 u32 addr, u32 size, u32 pitch, u32 flags)
52 {
53 struct nouveau_drm *drm = nouveau_drm(dev);
54 int i = reg - drm->tile.reg;
55 struct nouveau_fb *pfb = nouveau_fb(drm->device);
56 struct nouveau_fb_tile *tile = &pfb->tile.region[i];
57 struct nouveau_engine *engine;
58
59 nouveau_fence_unref(&reg->fence);
60
61 if (tile->pitch)
62 pfb->tile.fini(pfb, i, tile);
63
64 if (pitch)
65 pfb->tile.init(pfb, i, addr, size, pitch, flags, tile);
66
67 pfb->tile.prog(pfb, i, tile);
68
69 if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_GR)))
70 engine->tile_prog(engine, i);
71 if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_MPEG)))
72 engine->tile_prog(engine, i);
73 }
74
75 static struct nouveau_drm_tile *
76 nv10_bo_get_tile_region(struct drm_device *dev, int i)
77 {
78 struct nouveau_drm *drm = nouveau_drm(dev);
79 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
80
81 spin_lock(&drm->tile.lock);
82
83 if (!tile->used &&
84 (!tile->fence || nouveau_fence_done(tile->fence)))
85 tile->used = true;
86 else
87 tile = NULL;
88
89 spin_unlock(&drm->tile.lock);
90 return tile;
91 }
92
93 static void
94 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
95 struct nouveau_fence *fence)
96 {
97 struct nouveau_drm *drm = nouveau_drm(dev);
98
99 if (tile) {
100 spin_lock(&drm->tile.lock);
101 if (fence) {
102 /* Mark it as pending. */
103 tile->fence = fence;
104 nouveau_fence_ref(fence);
105 }
106
107 tile->used = false;
108 spin_unlock(&drm->tile.lock);
109 }
110 }
111
112 static struct nouveau_drm_tile *
113 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
114 u32 size, u32 pitch, u32 flags)
115 {
116 struct nouveau_drm *drm = nouveau_drm(dev);
117 struct nouveau_fb *pfb = nouveau_fb(drm->device);
118 struct nouveau_drm_tile *tile, *found = NULL;
119 int i;
120
121 for (i = 0; i < pfb->tile.regions; i++) {
122 tile = nv10_bo_get_tile_region(dev, i);
123
124 if (pitch && !found) {
125 found = tile;
126 continue;
127
128 } else if (tile && pfb->tile.region[i].pitch) {
129 /* Kill an unused tile region. */
130 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
131 }
132
133 nv10_bo_put_tile_region(dev, tile, NULL);
134 }
135
136 if (found)
137 nv10_bo_update_tile_region(dev, found, addr, size,
138 pitch, flags);
139 return found;
140 }
141
142 static void
143 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
144 {
145 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
146 struct drm_device *dev = drm->dev;
147 struct nouveau_bo *nvbo = nouveau_bo(bo);
148
149 if (unlikely(nvbo->gem))
150 DRM_ERROR("bo %p still attached to GEM object\n", bo);
151 WARN_ON(nvbo->pin_refcnt > 0);
152 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
153 kfree(nvbo);
154 }
155
156 static void
157 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
158 int *align, int *size)
159 {
160 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
161 struct nouveau_device *device = nv_device(drm->device);
162
163 if (device->card_type < NV_50) {
164 if (nvbo->tile_mode) {
165 if (device->chipset >= 0x40) {
166 *align = 65536;
167 *size = roundup(*size, 64 * nvbo->tile_mode);
168
169 } else if (device->chipset >= 0x30) {
170 *align = 32768;
171 *size = roundup(*size, 64 * nvbo->tile_mode);
172
173 } else if (device->chipset >= 0x20) {
174 *align = 16384;
175 *size = roundup(*size, 64 * nvbo->tile_mode);
176
177 } else if (device->chipset >= 0x10) {
178 *align = 16384;
179 *size = roundup(*size, 32 * nvbo->tile_mode);
180 }
181 }
182 } else {
183 *size = roundup(*size, (1 << nvbo->page_shift));
184 *align = max((1 << nvbo->page_shift), *align);
185 }
186
187 *size = roundup(*size, PAGE_SIZE);
188 }
189
190 int
191 nouveau_bo_new(struct drm_device *dev, int size, int align,
192 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
193 struct sg_table *sg,
194 struct nouveau_bo **pnvbo)
195 {
196 struct nouveau_drm *drm = nouveau_drm(dev);
197 struct nouveau_bo *nvbo;
198 size_t acc_size;
199 int ret;
200 int type = ttm_bo_type_device;
201
202 if (sg)
203 type = ttm_bo_type_sg;
204
205 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
206 if (!nvbo)
207 return -ENOMEM;
208 INIT_LIST_HEAD(&nvbo->head);
209 INIT_LIST_HEAD(&nvbo->entry);
210 INIT_LIST_HEAD(&nvbo->vma_list);
211 nvbo->tile_mode = tile_mode;
212 nvbo->tile_flags = tile_flags;
213 nvbo->bo.bdev = &drm->ttm.bdev;
214
215 nvbo->page_shift = 12;
216 if (drm->client.base.vm) {
217 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
218 nvbo->page_shift = drm->client.base.vm->vmm->lpg_shift;
219 }
220
221 nouveau_bo_fixup_align(nvbo, flags, &align, &size);
222 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
223 nouveau_bo_placement_set(nvbo, flags, 0);
224
225 acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size,
226 sizeof(struct nouveau_bo));
227
228 ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size,
229 type, &nvbo->placement,
230 align >> PAGE_SHIFT, false, NULL, acc_size, sg,
231 nouveau_bo_del_ttm);
232 if (ret) {
233 /* ttm will call nouveau_bo_del_ttm if it fails.. */
234 return ret;
235 }
236
237 *pnvbo = nvbo;
238 return 0;
239 }
240
241 static void
242 set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
243 {
244 *n = 0;
245
246 if (type & TTM_PL_FLAG_VRAM)
247 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
248 if (type & TTM_PL_FLAG_TT)
249 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
250 if (type & TTM_PL_FLAG_SYSTEM)
251 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
252 }
253
254 static void
255 set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
256 {
257 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
258 struct nouveau_fb *pfb = nouveau_fb(drm->device);
259 u32 vram_pages = pfb->ram->size >> PAGE_SHIFT;
260
261 if (nv_device(drm->device)->card_type == NV_10 &&
262 nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
263 nvbo->bo.mem.num_pages < vram_pages / 4) {
264 /*
265 * Make sure that the color and depth buffers are handled
266 * by independent memory controller units. Up to a 9x
267 * speed up when alpha-blending and depth-test are enabled
268 * at the same time.
269 */
270 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
271 nvbo->placement.fpfn = vram_pages / 2;
272 nvbo->placement.lpfn = ~0;
273 } else {
274 nvbo->placement.fpfn = 0;
275 nvbo->placement.lpfn = vram_pages / 2;
276 }
277 }
278 }
279
280 void
281 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
282 {
283 struct ttm_placement *pl = &nvbo->placement;
284 uint32_t flags = TTM_PL_MASK_CACHING |
285 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
286
287 pl->placement = nvbo->placements;
288 set_placement_list(nvbo->placements, &pl->num_placement,
289 type, flags);
290
291 pl->busy_placement = nvbo->busy_placements;
292 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
293 type | busy, flags);
294
295 set_placement_range(nvbo, type);
296 }
297
298 int
299 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
300 {
301 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
302 struct ttm_buffer_object *bo = &nvbo->bo;
303 int ret;
304
305 ret = ttm_bo_reserve(bo, false, false, false, 0);
306 if (ret)
307 goto out;
308
309 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
310 NV_ERROR(drm, "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
311 1 << bo->mem.mem_type, memtype);
312 ret = -EINVAL;
313 goto out;
314 }
315
316 if (nvbo->pin_refcnt++)
317 goto out;
318
319 nouveau_bo_placement_set(nvbo, memtype, 0);
320
321 ret = nouveau_bo_validate(nvbo, false, false);
322 if (ret == 0) {
323 switch (bo->mem.mem_type) {
324 case TTM_PL_VRAM:
325 drm->gem.vram_available -= bo->mem.size;
326 break;
327 case TTM_PL_TT:
328 drm->gem.gart_available -= bo->mem.size;
329 break;
330 default:
331 break;
332 }
333 }
334 out:
335 ttm_bo_unreserve(bo);
336 return ret;
337 }
338
339 int
340 nouveau_bo_unpin(struct nouveau_bo *nvbo)
341 {
342 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
343 struct ttm_buffer_object *bo = &nvbo->bo;
344 int ret, ref;
345
346 ret = ttm_bo_reserve(bo, false, false, false, 0);
347 if (ret)
348 return ret;
349
350 ref = --nvbo->pin_refcnt;
351 WARN_ON_ONCE(ref < 0);
352 if (ref)
353 goto out;
354
355 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
356
357 ret = nouveau_bo_validate(nvbo, false, false);
358 if (ret == 0) {
359 switch (bo->mem.mem_type) {
360 case TTM_PL_VRAM:
361 drm->gem.vram_available += bo->mem.size;
362 break;
363 case TTM_PL_TT:
364 drm->gem.gart_available += bo->mem.size;
365 break;
366 default:
367 break;
368 }
369 }
370
371 out:
372 ttm_bo_unreserve(bo);
373 return ret;
374 }
375
376 int
377 nouveau_bo_map(struct nouveau_bo *nvbo)
378 {
379 int ret;
380
381 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
382 if (ret)
383 return ret;
384
385 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
386 ttm_bo_unreserve(&nvbo->bo);
387 return ret;
388 }
389
390 void
391 nouveau_bo_unmap(struct nouveau_bo *nvbo)
392 {
393 if (nvbo)
394 ttm_bo_kunmap(&nvbo->kmap);
395 }
396
397 int
398 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
399 bool no_wait_gpu)
400 {
401 int ret;
402
403 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement,
404 interruptible, no_wait_gpu);
405 if (ret)
406 return ret;
407
408 return 0;
409 }
410
411 u16
412 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
413 {
414 bool is_iomem;
415 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
416 mem = &mem[index];
417 if (is_iomem)
418 return ioread16_native((void __force __iomem *)mem);
419 else
420 return *mem;
421 }
422
423 void
424 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
425 {
426 bool is_iomem;
427 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
428 mem = &mem[index];
429 if (is_iomem)
430 iowrite16_native(val, (void __force __iomem *)mem);
431 else
432 *mem = val;
433 }
434
435 u32
436 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
437 {
438 bool is_iomem;
439 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
440 mem = &mem[index];
441 if (is_iomem)
442 return ioread32_native((void __force __iomem *)mem);
443 else
444 return *mem;
445 }
446
447 void
448 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
449 {
450 bool is_iomem;
451 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
452 mem = &mem[index];
453 if (is_iomem)
454 iowrite32_native(val, (void __force __iomem *)mem);
455 else
456 *mem = val;
457 }
458
459 static struct ttm_tt *
460 nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size,
461 uint32_t page_flags, struct page *dummy_read)
462 {
463 #if __OS_HAS_AGP
464 struct nouveau_drm *drm = nouveau_bdev(bdev);
465 struct drm_device *dev = drm->dev;
466
467 if (drm->agp.stat == ENABLED) {
468 return ttm_agp_tt_create(bdev, dev->agp->bridge, size,
469 page_flags, dummy_read);
470 }
471 #endif
472
473 return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read);
474 }
475
476 static int
477 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
478 {
479 /* We'll do this from user space. */
480 return 0;
481 }
482
483 static int
484 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
485 struct ttm_mem_type_manager *man)
486 {
487 struct nouveau_drm *drm = nouveau_bdev(bdev);
488
489 switch (type) {
490 case TTM_PL_SYSTEM:
491 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
492 man->available_caching = TTM_PL_MASK_CACHING;
493 man->default_caching = TTM_PL_FLAG_CACHED;
494 break;
495 case TTM_PL_VRAM:
496 if (nv_device(drm->device)->card_type >= NV_50) {
497 man->func = &nouveau_vram_manager;
498 man->io_reserve_fastpath = false;
499 man->use_io_reserve_lru = true;
500 } else {
501 man->func = &ttm_bo_manager_func;
502 }
503 man->flags = TTM_MEMTYPE_FLAG_FIXED |
504 TTM_MEMTYPE_FLAG_MAPPABLE;
505 man->available_caching = TTM_PL_FLAG_UNCACHED |
506 TTM_PL_FLAG_WC;
507 man->default_caching = TTM_PL_FLAG_WC;
508 break;
509 case TTM_PL_TT:
510 if (nv_device(drm->device)->card_type >= NV_50)
511 man->func = &nouveau_gart_manager;
512 else
513 if (drm->agp.stat != ENABLED)
514 man->func = &nv04_gart_manager;
515 else
516 man->func = &ttm_bo_manager_func;
517
518 if (drm->agp.stat == ENABLED) {
519 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
520 man->available_caching = TTM_PL_FLAG_UNCACHED |
521 TTM_PL_FLAG_WC;
522 man->default_caching = TTM_PL_FLAG_WC;
523 } else {
524 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
525 TTM_MEMTYPE_FLAG_CMA;
526 man->available_caching = TTM_PL_MASK_CACHING;
527 man->default_caching = TTM_PL_FLAG_CACHED;
528 }
529
530 break;
531 default:
532 return -EINVAL;
533 }
534 return 0;
535 }
536
537 static void
538 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
539 {
540 struct nouveau_bo *nvbo = nouveau_bo(bo);
541
542 switch (bo->mem.mem_type) {
543 case TTM_PL_VRAM:
544 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
545 TTM_PL_FLAG_SYSTEM);
546 break;
547 default:
548 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
549 break;
550 }
551
552 *pl = nvbo->placement;
553 }
554
555
556 /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
557 * TTM_PL_{VRAM,TT} directly.
558 */
559
560 static int
561 nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
562 struct nouveau_bo *nvbo, bool evict,
563 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
564 {
565 struct nouveau_fence *fence = NULL;
566 int ret;
567
568 ret = nouveau_fence_new(chan, false, &fence);
569 if (ret)
570 return ret;
571
572 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, evict,
573 no_wait_gpu, new_mem);
574 nouveau_fence_unref(&fence);
575 return ret;
576 }
577
578 static int
579 nve0_bo_move_init(struct nouveau_channel *chan, u32 handle)
580 {
581 int ret = RING_SPACE(chan, 2);
582 if (ret == 0) {
583 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
584 OUT_RING (chan, handle & 0x0000ffff);
585 FIRE_RING (chan);
586 }
587 return ret;
588 }
589
590 static int
591 nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
592 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
593 {
594 struct nouveau_mem *node = old_mem->mm_node;
595 int ret = RING_SPACE(chan, 10);
596 if (ret == 0) {
597 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
598 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
599 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
600 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
601 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
602 OUT_RING (chan, PAGE_SIZE);
603 OUT_RING (chan, PAGE_SIZE);
604 OUT_RING (chan, PAGE_SIZE);
605 OUT_RING (chan, new_mem->num_pages);
606 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
607 }
608 return ret;
609 }
610
611 static int
612 nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
613 {
614 int ret = RING_SPACE(chan, 2);
615 if (ret == 0) {
616 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
617 OUT_RING (chan, handle);
618 }
619 return ret;
620 }
621
622 static int
623 nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
624 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
625 {
626 struct nouveau_mem *node = old_mem->mm_node;
627 u64 src_offset = node->vma[0].offset;
628 u64 dst_offset = node->vma[1].offset;
629 u32 page_count = new_mem->num_pages;
630 int ret;
631
632 page_count = new_mem->num_pages;
633 while (page_count) {
634 int line_count = (page_count > 8191) ? 8191 : page_count;
635
636 ret = RING_SPACE(chan, 11);
637 if (ret)
638 return ret;
639
640 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8);
641 OUT_RING (chan, upper_32_bits(src_offset));
642 OUT_RING (chan, lower_32_bits(src_offset));
643 OUT_RING (chan, upper_32_bits(dst_offset));
644 OUT_RING (chan, lower_32_bits(dst_offset));
645 OUT_RING (chan, PAGE_SIZE);
646 OUT_RING (chan, PAGE_SIZE);
647 OUT_RING (chan, PAGE_SIZE);
648 OUT_RING (chan, line_count);
649 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
650 OUT_RING (chan, 0x00000110);
651
652 page_count -= line_count;
653 src_offset += (PAGE_SIZE * line_count);
654 dst_offset += (PAGE_SIZE * line_count);
655 }
656
657 return 0;
658 }
659
660 static int
661 nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
662 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
663 {
664 struct nouveau_mem *node = old_mem->mm_node;
665 u64 src_offset = node->vma[0].offset;
666 u64 dst_offset = node->vma[1].offset;
667 u32 page_count = new_mem->num_pages;
668 int ret;
669
670 page_count = new_mem->num_pages;
671 while (page_count) {
672 int line_count = (page_count > 2047) ? 2047 : page_count;
673
674 ret = RING_SPACE(chan, 12);
675 if (ret)
676 return ret;
677
678 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
679 OUT_RING (chan, upper_32_bits(dst_offset));
680 OUT_RING (chan, lower_32_bits(dst_offset));
681 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
682 OUT_RING (chan, upper_32_bits(src_offset));
683 OUT_RING (chan, lower_32_bits(src_offset));
684 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
685 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
686 OUT_RING (chan, PAGE_SIZE); /* line_length */
687 OUT_RING (chan, line_count);
688 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
689 OUT_RING (chan, 0x00100110);
690
691 page_count -= line_count;
692 src_offset += (PAGE_SIZE * line_count);
693 dst_offset += (PAGE_SIZE * line_count);
694 }
695
696 return 0;
697 }
698
699 static int
700 nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
701 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
702 {
703 struct nouveau_mem *node = old_mem->mm_node;
704 u64 src_offset = node->vma[0].offset;
705 u64 dst_offset = node->vma[1].offset;
706 u32 page_count = new_mem->num_pages;
707 int ret;
708
709 page_count = new_mem->num_pages;
710 while (page_count) {
711 int line_count = (page_count > 8191) ? 8191 : page_count;
712
713 ret = RING_SPACE(chan, 11);
714 if (ret)
715 return ret;
716
717 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
718 OUT_RING (chan, upper_32_bits(src_offset));
719 OUT_RING (chan, lower_32_bits(src_offset));
720 OUT_RING (chan, upper_32_bits(dst_offset));
721 OUT_RING (chan, lower_32_bits(dst_offset));
722 OUT_RING (chan, PAGE_SIZE);
723 OUT_RING (chan, PAGE_SIZE);
724 OUT_RING (chan, PAGE_SIZE);
725 OUT_RING (chan, line_count);
726 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1);
727 OUT_RING (chan, 0x00000110);
728
729 page_count -= line_count;
730 src_offset += (PAGE_SIZE * line_count);
731 dst_offset += (PAGE_SIZE * line_count);
732 }
733
734 return 0;
735 }
736
737 static int
738 nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
739 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
740 {
741 struct nouveau_mem *node = old_mem->mm_node;
742 int ret = RING_SPACE(chan, 7);
743 if (ret == 0) {
744 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
745 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
746 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
747 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
748 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
749 OUT_RING (chan, 0x00000000 /* COPY */);
750 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
751 }
752 return ret;
753 }
754
755 static int
756 nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
757 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
758 {
759 struct nouveau_mem *node = old_mem->mm_node;
760 int ret = RING_SPACE(chan, 7);
761 if (ret == 0) {
762 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
763 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
764 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
765 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
766 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
767 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
768 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */);
769 }
770 return ret;
771 }
772
773 static int
774 nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
775 {
776 int ret = RING_SPACE(chan, 6);
777 if (ret == 0) {
778 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
779 OUT_RING (chan, handle);
780 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
781 OUT_RING (chan, NvNotify0);
782 OUT_RING (chan, NvDmaFB);
783 OUT_RING (chan, NvDmaFB);
784 }
785
786 return ret;
787 }
788
789 static int
790 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
791 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
792 {
793 struct nouveau_mem *node = old_mem->mm_node;
794 struct nouveau_bo *nvbo = nouveau_bo(bo);
795 u64 length = (new_mem->num_pages << PAGE_SHIFT);
796 u64 src_offset = node->vma[0].offset;
797 u64 dst_offset = node->vma[1].offset;
798 int ret;
799
800 while (length) {
801 u32 amount, stride, height;
802
803 amount = min(length, (u64)(4 * 1024 * 1024));
804 stride = 16 * 4;
805 height = amount / stride;
806
807 if (old_mem->mem_type == TTM_PL_VRAM &&
808 nouveau_bo_tile_layout(nvbo)) {
809 ret = RING_SPACE(chan, 8);
810 if (ret)
811 return ret;
812
813 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
814 OUT_RING (chan, 0);
815 OUT_RING (chan, 0);
816 OUT_RING (chan, stride);
817 OUT_RING (chan, height);
818 OUT_RING (chan, 1);
819 OUT_RING (chan, 0);
820 OUT_RING (chan, 0);
821 } else {
822 ret = RING_SPACE(chan, 2);
823 if (ret)
824 return ret;
825
826 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
827 OUT_RING (chan, 1);
828 }
829 if (new_mem->mem_type == TTM_PL_VRAM &&
830 nouveau_bo_tile_layout(nvbo)) {
831 ret = RING_SPACE(chan, 8);
832 if (ret)
833 return ret;
834
835 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
836 OUT_RING (chan, 0);
837 OUT_RING (chan, 0);
838 OUT_RING (chan, stride);
839 OUT_RING (chan, height);
840 OUT_RING (chan, 1);
841 OUT_RING (chan, 0);
842 OUT_RING (chan, 0);
843 } else {
844 ret = RING_SPACE(chan, 2);
845 if (ret)
846 return ret;
847
848 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
849 OUT_RING (chan, 1);
850 }
851
852 ret = RING_SPACE(chan, 14);
853 if (ret)
854 return ret;
855
856 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
857 OUT_RING (chan, upper_32_bits(src_offset));
858 OUT_RING (chan, upper_32_bits(dst_offset));
859 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
860 OUT_RING (chan, lower_32_bits(src_offset));
861 OUT_RING (chan, lower_32_bits(dst_offset));
862 OUT_RING (chan, stride);
863 OUT_RING (chan, stride);
864 OUT_RING (chan, stride);
865 OUT_RING (chan, height);
866 OUT_RING (chan, 0x00000101);
867 OUT_RING (chan, 0x00000000);
868 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
869 OUT_RING (chan, 0);
870
871 length -= amount;
872 src_offset += amount;
873 dst_offset += amount;
874 }
875
876 return 0;
877 }
878
879 static int
880 nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
881 {
882 int ret = RING_SPACE(chan, 4);
883 if (ret == 0) {
884 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
885 OUT_RING (chan, handle);
886 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
887 OUT_RING (chan, NvNotify0);
888 }
889
890 return ret;
891 }
892
893 static inline uint32_t
894 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
895 struct nouveau_channel *chan, struct ttm_mem_reg *mem)
896 {
897 if (mem->mem_type == TTM_PL_TT)
898 return NvDmaTT;
899 return NvDmaFB;
900 }
901
902 static int
903 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
904 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
905 {
906 u32 src_offset = old_mem->start << PAGE_SHIFT;
907 u32 dst_offset = new_mem->start << PAGE_SHIFT;
908 u32 page_count = new_mem->num_pages;
909 int ret;
910
911 ret = RING_SPACE(chan, 3);
912 if (ret)
913 return ret;
914
915 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
916 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
917 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
918
919 page_count = new_mem->num_pages;
920 while (page_count) {
921 int line_count = (page_count > 2047) ? 2047 : page_count;
922
923 ret = RING_SPACE(chan, 11);
924 if (ret)
925 return ret;
926
927 BEGIN_NV04(chan, NvSubCopy,
928 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
929 OUT_RING (chan, src_offset);
930 OUT_RING (chan, dst_offset);
931 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
932 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
933 OUT_RING (chan, PAGE_SIZE); /* line_length */
934 OUT_RING (chan, line_count);
935 OUT_RING (chan, 0x00000101);
936 OUT_RING (chan, 0x00000000);
937 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
938 OUT_RING (chan, 0);
939
940 page_count -= line_count;
941 src_offset += (PAGE_SIZE * line_count);
942 dst_offset += (PAGE_SIZE * line_count);
943 }
944
945 return 0;
946 }
947
948 static int
949 nouveau_vma_getmap(struct nouveau_channel *chan, struct nouveau_bo *nvbo,
950 struct ttm_mem_reg *mem, struct nouveau_vma *vma)
951 {
952 struct nouveau_mem *node = mem->mm_node;
953 int ret;
954
955 ret = nouveau_vm_get(nv_client(chan->cli)->vm, mem->num_pages <<
956 PAGE_SHIFT, node->page_shift,
957 NV_MEM_ACCESS_RW, vma);
958 if (ret)
959 return ret;
960
961 if (mem->mem_type == TTM_PL_VRAM)
962 nouveau_vm_map(vma, node);
963 else
964 nouveau_vm_map_sg(vma, 0, mem->num_pages << PAGE_SHIFT, node);
965
966 return 0;
967 }
968
969 static int
970 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
971 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
972 {
973 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
974 struct nouveau_channel *chan = chan = drm->ttm.chan;
975 struct nouveau_bo *nvbo = nouveau_bo(bo);
976 struct ttm_mem_reg *old_mem = &bo->mem;
977 int ret;
978
979 mutex_lock_nested(&chan->cli->mutex, SINGLE_DEPTH_NESTING);
980
981 /* create temporary vmas for the transfer and attach them to the
982 * old nouveau_mem node, these will get cleaned up after ttm has
983 * destroyed the ttm_mem_reg
984 */
985 if (nv_device(drm->device)->card_type >= NV_50) {
986 struct nouveau_mem *node = old_mem->mm_node;
987
988 ret = nouveau_vma_getmap(chan, nvbo, old_mem, &node->vma[0]);
989 if (ret)
990 goto out;
991
992 ret = nouveau_vma_getmap(chan, nvbo, new_mem, &node->vma[1]);
993 if (ret)
994 goto out;
995 }
996
997 ret = drm->ttm.move(chan, bo, &bo->mem, new_mem);
998 if (ret == 0) {
999 ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict,
1000 no_wait_gpu, new_mem);
1001 }
1002
1003 out:
1004 mutex_unlock(&chan->cli->mutex);
1005 return ret;
1006 }
1007
1008 void
1009 nouveau_bo_move_init(struct nouveau_drm *drm)
1010 {
1011 static const struct {
1012 const char *name;
1013 int engine;
1014 u32 oclass;
1015 int (*exec)(struct nouveau_channel *,
1016 struct ttm_buffer_object *,
1017 struct ttm_mem_reg *, struct ttm_mem_reg *);
1018 int (*init)(struct nouveau_channel *, u32 handle);
1019 } _methods[] = {
1020 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
1021 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1022 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
1023 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
1024 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
1025 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
1026 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
1027 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
1028 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
1029 {},
1030 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init },
1031 }, *mthd = _methods;
1032 const char *name = "CPU";
1033 int ret;
1034
1035 do {
1036 struct nouveau_object *object;
1037 struct nouveau_channel *chan;
1038 u32 handle = (mthd->engine << 16) | mthd->oclass;
1039
1040 if (mthd->engine)
1041 chan = drm->cechan;
1042 else
1043 chan = drm->channel;
1044 if (chan == NULL)
1045 continue;
1046
1047 ret = nouveau_object_new(nv_object(drm), chan->handle, handle,
1048 mthd->oclass, NULL, 0, &object);
1049 if (ret == 0) {
1050 ret = mthd->init(chan, handle);
1051 if (ret) {
1052 nouveau_object_del(nv_object(drm),
1053 chan->handle, handle);
1054 continue;
1055 }
1056
1057 drm->ttm.move = mthd->exec;
1058 drm->ttm.chan = chan;
1059 name = mthd->name;
1060 break;
1061 }
1062 } while ((++mthd)->exec);
1063
1064 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
1065 }
1066
1067 static int
1068 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
1069 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1070 {
1071 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
1072 struct ttm_placement placement;
1073 struct ttm_mem_reg tmp_mem;
1074 int ret;
1075
1076 placement.fpfn = placement.lpfn = 0;
1077 placement.num_placement = placement.num_busy_placement = 1;
1078 placement.placement = placement.busy_placement = &placement_memtype;
1079
1080 tmp_mem = *new_mem;
1081 tmp_mem.mm_node = NULL;
1082 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1083 if (ret)
1084 return ret;
1085
1086 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
1087 if (ret)
1088 goto out;
1089
1090 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_mem);
1091 if (ret)
1092 goto out;
1093
1094 ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
1095 out:
1096 ttm_bo_mem_put(bo, &tmp_mem);
1097 return ret;
1098 }
1099
1100 static int
1101 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
1102 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1103 {
1104 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
1105 struct ttm_placement placement;
1106 struct ttm_mem_reg tmp_mem;
1107 int ret;
1108
1109 placement.fpfn = placement.lpfn = 0;
1110 placement.num_placement = placement.num_busy_placement = 1;
1111 placement.placement = placement.busy_placement = &placement_memtype;
1112
1113 tmp_mem = *new_mem;
1114 tmp_mem.mm_node = NULL;
1115 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1116 if (ret)
1117 return ret;
1118
1119 ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
1120 if (ret)
1121 goto out;
1122
1123 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_mem);
1124 if (ret)
1125 goto out;
1126
1127 out:
1128 ttm_bo_mem_put(bo, &tmp_mem);
1129 return ret;
1130 }
1131
1132 static void
1133 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
1134 {
1135 struct nouveau_bo *nvbo = nouveau_bo(bo);
1136 struct nouveau_vma *vma;
1137
1138 /* ttm can now (stupidly) pass the driver bos it didn't create... */
1139 if (bo->destroy != nouveau_bo_del_ttm)
1140 return;
1141
1142 list_for_each_entry(vma, &nvbo->vma_list, head) {
1143 if (new_mem && new_mem->mem_type == TTM_PL_VRAM) {
1144 nouveau_vm_map(vma, new_mem->mm_node);
1145 } else
1146 if (new_mem && new_mem->mem_type == TTM_PL_TT &&
1147 nvbo->page_shift == vma->vm->vmm->spg_shift) {
1148 if (((struct nouveau_mem *)new_mem->mm_node)->sg)
1149 nouveau_vm_map_sg_table(vma, 0, new_mem->
1150 num_pages << PAGE_SHIFT,
1151 new_mem->mm_node);
1152 else
1153 nouveau_vm_map_sg(vma, 0, new_mem->
1154 num_pages << PAGE_SHIFT,
1155 new_mem->mm_node);
1156 } else {
1157 nouveau_vm_unmap(vma);
1158 }
1159 }
1160 }
1161
1162 static int
1163 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
1164 struct nouveau_drm_tile **new_tile)
1165 {
1166 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1167 struct drm_device *dev = drm->dev;
1168 struct nouveau_bo *nvbo = nouveau_bo(bo);
1169 u64 offset = new_mem->start << PAGE_SHIFT;
1170
1171 *new_tile = NULL;
1172 if (new_mem->mem_type != TTM_PL_VRAM)
1173 return 0;
1174
1175 if (nv_device(drm->device)->card_type >= NV_10) {
1176 *new_tile = nv10_bo_set_tiling(dev, offset, new_mem->size,
1177 nvbo->tile_mode,
1178 nvbo->tile_flags);
1179 }
1180
1181 return 0;
1182 }
1183
1184 static void
1185 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1186 struct nouveau_drm_tile *new_tile,
1187 struct nouveau_drm_tile **old_tile)
1188 {
1189 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1190 struct drm_device *dev = drm->dev;
1191
1192 nv10_bo_put_tile_region(dev, *old_tile, bo->sync_obj);
1193 *old_tile = new_tile;
1194 }
1195
1196 static int
1197 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
1198 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1199 {
1200 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1201 struct nouveau_bo *nvbo = nouveau_bo(bo);
1202 struct ttm_mem_reg *old_mem = &bo->mem;
1203 struct nouveau_drm_tile *new_tile = NULL;
1204 int ret = 0;
1205
1206 if (nv_device(drm->device)->card_type < NV_50) {
1207 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
1208 if (ret)
1209 return ret;
1210 }
1211
1212 /* Fake bo copy. */
1213 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1214 BUG_ON(bo->mem.mm_node != NULL);
1215 bo->mem = *new_mem;
1216 new_mem->mm_node = NULL;
1217 goto out;
1218 }
1219
1220 /* CPU copy if we have no accelerated method available */
1221 if (!drm->ttm.move) {
1222 ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
1223 goto out;
1224 }
1225
1226 /* Hardware assisted copy. */
1227 if (new_mem->mem_type == TTM_PL_SYSTEM)
1228 ret = nouveau_bo_move_flipd(bo, evict, intr,
1229 no_wait_gpu, new_mem);
1230 else if (old_mem->mem_type == TTM_PL_SYSTEM)
1231 ret = nouveau_bo_move_flips(bo, evict, intr,
1232 no_wait_gpu, new_mem);
1233 else
1234 ret = nouveau_bo_move_m2mf(bo, evict, intr,
1235 no_wait_gpu, new_mem);
1236
1237 if (!ret)
1238 goto out;
1239
1240 /* Fallback to software copy. */
1241 ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
1242
1243 out:
1244 if (nv_device(drm->device)->card_type < NV_50) {
1245 if (ret)
1246 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1247 else
1248 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1249 }
1250
1251 return ret;
1252 }
1253
1254 static int
1255 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1256 {
1257 return 0;
1258 }
1259
1260 static int
1261 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1262 {
1263 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
1264 struct nouveau_drm *drm = nouveau_bdev(bdev);
1265 struct drm_device *dev = drm->dev;
1266 int ret;
1267
1268 mem->bus.addr = NULL;
1269 mem->bus.offset = 0;
1270 mem->bus.size = mem->num_pages << PAGE_SHIFT;
1271 mem->bus.base = 0;
1272 mem->bus.is_iomem = false;
1273 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
1274 return -EINVAL;
1275 switch (mem->mem_type) {
1276 case TTM_PL_SYSTEM:
1277 /* System memory */
1278 return 0;
1279 case TTM_PL_TT:
1280 #if __OS_HAS_AGP
1281 if (drm->agp.stat == ENABLED) {
1282 mem->bus.offset = mem->start << PAGE_SHIFT;
1283 mem->bus.base = drm->agp.base;
1284 mem->bus.is_iomem = !dev->agp->cant_use_aperture;
1285 }
1286 #endif
1287 break;
1288 case TTM_PL_VRAM:
1289 mem->bus.offset = mem->start << PAGE_SHIFT;
1290 mem->bus.base = pci_resource_start(dev->pdev, 1);
1291 mem->bus.is_iomem = true;
1292 if (nv_device(drm->device)->card_type >= NV_50) {
1293 struct nouveau_bar *bar = nouveau_bar(drm->device);
1294 struct nouveau_mem *node = mem->mm_node;
1295
1296 ret = bar->umap(bar, node, NV_MEM_ACCESS_RW,
1297 &node->bar_vma);
1298 if (ret)
1299 return ret;
1300
1301 mem->bus.offset = node->bar_vma.offset;
1302 }
1303 break;
1304 default:
1305 return -EINVAL;
1306 }
1307 return 0;
1308 }
1309
1310 static void
1311 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1312 {
1313 struct nouveau_drm *drm = nouveau_bdev(bdev);
1314 struct nouveau_bar *bar = nouveau_bar(drm->device);
1315 struct nouveau_mem *node = mem->mm_node;
1316
1317 if (!node->bar_vma.node)
1318 return;
1319
1320 bar->unmap(bar, &node->bar_vma);
1321 }
1322
1323 static int
1324 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1325 {
1326 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1327 struct nouveau_bo *nvbo = nouveau_bo(bo);
1328 struct nouveau_device *device = nv_device(drm->device);
1329 u32 mappable = pci_resource_len(device->pdev, 1) >> PAGE_SHIFT;
1330
1331 /* as long as the bo isn't in vram, and isn't tiled, we've got
1332 * nothing to do here.
1333 */
1334 if (bo->mem.mem_type != TTM_PL_VRAM) {
1335 if (nv_device(drm->device)->card_type < NV_50 ||
1336 !nouveau_bo_tile_layout(nvbo))
1337 return 0;
1338 }
1339
1340 /* make sure bo is in mappable vram */
1341 if (bo->mem.start + bo->mem.num_pages < mappable)
1342 return 0;
1343
1344
1345 nvbo->placement.fpfn = 0;
1346 nvbo->placement.lpfn = mappable;
1347 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
1348 return nouveau_bo_validate(nvbo, false, false);
1349 }
1350
1351 static int
1352 nouveau_ttm_tt_populate(struct ttm_tt *ttm)
1353 {
1354 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1355 struct nouveau_drm *drm;
1356 struct drm_device *dev;
1357 unsigned i;
1358 int r;
1359 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1360
1361 if (ttm->state != tt_unpopulated)
1362 return 0;
1363
1364 if (slave && ttm->sg) {
1365 /* make userspace faulting work */
1366 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1367 ttm_dma->dma_address, ttm->num_pages);
1368 ttm->state = tt_unbound;
1369 return 0;
1370 }
1371
1372 drm = nouveau_bdev(ttm->bdev);
1373 dev = drm->dev;
1374
1375 #if __OS_HAS_AGP
1376 if (drm->agp.stat == ENABLED) {
1377 return ttm_agp_tt_populate(ttm);
1378 }
1379 #endif
1380
1381 #ifdef CONFIG_SWIOTLB
1382 if (swiotlb_nr_tbl()) {
1383 return ttm_dma_populate((void *)ttm, dev->dev);
1384 }
1385 #endif
1386
1387 r = ttm_pool_populate(ttm);
1388 if (r) {
1389 return r;
1390 }
1391
1392 for (i = 0; i < ttm->num_pages; i++) {
1393 ttm_dma->dma_address[i] = pci_map_page(dev->pdev, ttm->pages[i],
1394 0, PAGE_SIZE,
1395 PCI_DMA_BIDIRECTIONAL);
1396 if (pci_dma_mapping_error(dev->pdev, ttm_dma->dma_address[i])) {
1397 while (--i) {
1398 pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
1399 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1400 ttm_dma->dma_address[i] = 0;
1401 }
1402 ttm_pool_unpopulate(ttm);
1403 return -EFAULT;
1404 }
1405 }
1406 return 0;
1407 }
1408
1409 static void
1410 nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1411 {
1412 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1413 struct nouveau_drm *drm;
1414 struct drm_device *dev;
1415 unsigned i;
1416 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1417
1418 if (slave)
1419 return;
1420
1421 drm = nouveau_bdev(ttm->bdev);
1422 dev = drm->dev;
1423
1424 #if __OS_HAS_AGP
1425 if (drm->agp.stat == ENABLED) {
1426 ttm_agp_tt_unpopulate(ttm);
1427 return;
1428 }
1429 #endif
1430
1431 #ifdef CONFIG_SWIOTLB
1432 if (swiotlb_nr_tbl()) {
1433 ttm_dma_unpopulate((void *)ttm, dev->dev);
1434 return;
1435 }
1436 #endif
1437
1438 for (i = 0; i < ttm->num_pages; i++) {
1439 if (ttm_dma->dma_address[i]) {
1440 pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
1441 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1442 }
1443 }
1444
1445 ttm_pool_unpopulate(ttm);
1446 }
1447
1448 void
1449 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
1450 {
1451 struct nouveau_fence *old_fence = NULL;
1452
1453 if (likely(fence))
1454 nouveau_fence_ref(fence);
1455
1456 spin_lock(&nvbo->bo.bdev->fence_lock);
1457 old_fence = nvbo->bo.sync_obj;
1458 nvbo->bo.sync_obj = fence;
1459 spin_unlock(&nvbo->bo.bdev->fence_lock);
1460
1461 nouveau_fence_unref(&old_fence);
1462 }
1463
1464 static void
1465 nouveau_bo_fence_unref(void **sync_obj)
1466 {
1467 nouveau_fence_unref((struct nouveau_fence **)sync_obj);
1468 }
1469
1470 static void *
1471 nouveau_bo_fence_ref(void *sync_obj)
1472 {
1473 return nouveau_fence_ref(sync_obj);
1474 }
1475
1476 static bool
1477 nouveau_bo_fence_signalled(void *sync_obj)
1478 {
1479 return nouveau_fence_done(sync_obj);
1480 }
1481
1482 static int
1483 nouveau_bo_fence_wait(void *sync_obj, bool lazy, bool intr)
1484 {
1485 return nouveau_fence_wait(sync_obj, lazy, intr);
1486 }
1487
1488 static int
1489 nouveau_bo_fence_flush(void *sync_obj)
1490 {
1491 return 0;
1492 }
1493
1494 struct ttm_bo_driver nouveau_bo_driver = {
1495 .ttm_tt_create = &nouveau_ttm_tt_create,
1496 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1497 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1498 .invalidate_caches = nouveau_bo_invalidate_caches,
1499 .init_mem_type = nouveau_bo_init_mem_type,
1500 .evict_flags = nouveau_bo_evict_flags,
1501 .move_notify = nouveau_bo_move_ntfy,
1502 .move = nouveau_bo_move,
1503 .verify_access = nouveau_bo_verify_access,
1504 .sync_obj_signaled = nouveau_bo_fence_signalled,
1505 .sync_obj_wait = nouveau_bo_fence_wait,
1506 .sync_obj_flush = nouveau_bo_fence_flush,
1507 .sync_obj_unref = nouveau_bo_fence_unref,
1508 .sync_obj_ref = nouveau_bo_fence_ref,
1509 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1510 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1511 .io_mem_free = &nouveau_ttm_io_mem_free,
1512 };
1513
1514 struct nouveau_vma *
1515 nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm)
1516 {
1517 struct nouveau_vma *vma;
1518 list_for_each_entry(vma, &nvbo->vma_list, head) {
1519 if (vma->vm == vm)
1520 return vma;
1521 }
1522
1523 return NULL;
1524 }
1525
1526 int
1527 nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
1528 struct nouveau_vma *vma)
1529 {
1530 const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
1531 struct nouveau_mem *node = nvbo->bo.mem.mm_node;
1532 int ret;
1533
1534 ret = nouveau_vm_get(vm, size, nvbo->page_shift,
1535 NV_MEM_ACCESS_RW, vma);
1536 if (ret)
1537 return ret;
1538
1539 if (nvbo->bo.mem.mem_type == TTM_PL_VRAM)
1540 nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
1541 else if (nvbo->bo.mem.mem_type == TTM_PL_TT) {
1542 if (node->sg)
1543 nouveau_vm_map_sg_table(vma, 0, size, node);
1544 else
1545 nouveau_vm_map_sg(vma, 0, size, node);
1546 }
1547
1548 list_add_tail(&vma->head, &nvbo->vma_list);
1549 vma->refcount = 1;
1550 return 0;
1551 }
1552
1553 void
1554 nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
1555 {
1556 if (vma->node) {
1557 if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM)
1558 nouveau_vm_unmap(vma);
1559 nouveau_vm_put(vma);
1560 list_del(&vma->head);
1561 }
1562 }
Linux kernel - Deliverables
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