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drm/nouveau: do not allow negative sizes for now
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_bo.c
1 /*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24 /*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30 #include <core/engine.h>
31 #include <linux/swiotlb.h>
32
33 #include <subdev/fb.h>
34 #include <subdev/vm.h>
35 #include <subdev/bar.h>
36
37 #include "nouveau_drm.h"
38 #include "nouveau_dma.h"
39 #include "nouveau_fence.h"
40
41 #include "nouveau_bo.h"
42 #include "nouveau_ttm.h"
43 #include "nouveau_gem.h"
44
45 /*
46 * NV10-NV40 tiling helpers
47 */
48
49 static void
50 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
51 u32 addr, u32 size, u32 pitch, u32 flags)
52 {
53 struct nouveau_drm *drm = nouveau_drm(dev);
54 int i = reg - drm->tile.reg;
55 struct nouveau_fb *pfb = nouveau_fb(drm->device);
56 struct nouveau_fb_tile *tile = &pfb->tile.region[i];
57 struct nouveau_engine *engine;
58
59 nouveau_fence_unref(&reg->fence);
60
61 if (tile->pitch)
62 pfb->tile.fini(pfb, i, tile);
63
64 if (pitch)
65 pfb->tile.init(pfb, i, addr, size, pitch, flags, tile);
66
67 pfb->tile.prog(pfb, i, tile);
68
69 if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_GR)))
70 engine->tile_prog(engine, i);
71 if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_MPEG)))
72 engine->tile_prog(engine, i);
73 }
74
75 static struct nouveau_drm_tile *
76 nv10_bo_get_tile_region(struct drm_device *dev, int i)
77 {
78 struct nouveau_drm *drm = nouveau_drm(dev);
79 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
80
81 spin_lock(&drm->tile.lock);
82
83 if (!tile->used &&
84 (!tile->fence || nouveau_fence_done(tile->fence)))
85 tile->used = true;
86 else
87 tile = NULL;
88
89 spin_unlock(&drm->tile.lock);
90 return tile;
91 }
92
93 static void
94 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
95 struct nouveau_fence *fence)
96 {
97 struct nouveau_drm *drm = nouveau_drm(dev);
98
99 if (tile) {
100 spin_lock(&drm->tile.lock);
101 if (fence) {
102 /* Mark it as pending. */
103 tile->fence = fence;
104 nouveau_fence_ref(fence);
105 }
106
107 tile->used = false;
108 spin_unlock(&drm->tile.lock);
109 }
110 }
111
112 static struct nouveau_drm_tile *
113 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
114 u32 size, u32 pitch, u32 flags)
115 {
116 struct nouveau_drm *drm = nouveau_drm(dev);
117 struct nouveau_fb *pfb = nouveau_fb(drm->device);
118 struct nouveau_drm_tile *tile, *found = NULL;
119 int i;
120
121 for (i = 0; i < pfb->tile.regions; i++) {
122 tile = nv10_bo_get_tile_region(dev, i);
123
124 if (pitch && !found) {
125 found = tile;
126 continue;
127
128 } else if (tile && pfb->tile.region[i].pitch) {
129 /* Kill an unused tile region. */
130 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
131 }
132
133 nv10_bo_put_tile_region(dev, tile, NULL);
134 }
135
136 if (found)
137 nv10_bo_update_tile_region(dev, found, addr, size,
138 pitch, flags);
139 return found;
140 }
141
142 static void
143 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
144 {
145 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
146 struct drm_device *dev = drm->dev;
147 struct nouveau_bo *nvbo = nouveau_bo(bo);
148
149 if (unlikely(nvbo->gem))
150 DRM_ERROR("bo %p still attached to GEM object\n", bo);
151 WARN_ON(nvbo->pin_refcnt > 0);
152 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
153 kfree(nvbo);
154 }
155
156 static void
157 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
158 int *align, int *size)
159 {
160 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
161 struct nouveau_device *device = nv_device(drm->device);
162
163 if (device->card_type < NV_50) {
164 if (nvbo->tile_mode) {
165 if (device->chipset >= 0x40) {
166 *align = 65536;
167 *size = roundup(*size, 64 * nvbo->tile_mode);
168
169 } else if (device->chipset >= 0x30) {
170 *align = 32768;
171 *size = roundup(*size, 64 * nvbo->tile_mode);
172
173 } else if (device->chipset >= 0x20) {
174 *align = 16384;
175 *size = roundup(*size, 64 * nvbo->tile_mode);
176
177 } else if (device->chipset >= 0x10) {
178 *align = 16384;
179 *size = roundup(*size, 32 * nvbo->tile_mode);
180 }
181 }
182 } else {
183 *size = roundup(*size, (1 << nvbo->page_shift));
184 *align = max((1 << nvbo->page_shift), *align);
185 }
186
187 *size = roundup(*size, PAGE_SIZE);
188 }
189
190 int
191 nouveau_bo_new(struct drm_device *dev, int size, int align,
192 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
193 struct sg_table *sg,
194 struct nouveau_bo **pnvbo)
195 {
196 struct nouveau_drm *drm = nouveau_drm(dev);
197 struct nouveau_bo *nvbo;
198 size_t acc_size;
199 int ret;
200 int type = ttm_bo_type_device;
201 int max_size = INT_MAX & ~((1 << drm->client.base.vm->vmm->lpg_shift) - 1);
202
203 if (size <= 0 || size > max_size) {
204 nv_warn(drm, "skipped size %x\n", (u32)size);
205 return -EINVAL;
206 }
207
208 if (sg)
209 type = ttm_bo_type_sg;
210
211 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
212 if (!nvbo)
213 return -ENOMEM;
214 INIT_LIST_HEAD(&nvbo->head);
215 INIT_LIST_HEAD(&nvbo->entry);
216 INIT_LIST_HEAD(&nvbo->vma_list);
217 nvbo->tile_mode = tile_mode;
218 nvbo->tile_flags = tile_flags;
219 nvbo->bo.bdev = &drm->ttm.bdev;
220
221 nvbo->page_shift = 12;
222 if (drm->client.base.vm) {
223 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
224 nvbo->page_shift = drm->client.base.vm->vmm->lpg_shift;
225 }
226
227 nouveau_bo_fixup_align(nvbo, flags, &align, &size);
228 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
229 nouveau_bo_placement_set(nvbo, flags, 0);
230
231 acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size,
232 sizeof(struct nouveau_bo));
233
234 ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size,
235 type, &nvbo->placement,
236 align >> PAGE_SHIFT, false, NULL, acc_size, sg,
237 nouveau_bo_del_ttm);
238 if (ret) {
239 /* ttm will call nouveau_bo_del_ttm if it fails.. */
240 return ret;
241 }
242
243 *pnvbo = nvbo;
244 return 0;
245 }
246
247 static void
248 set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
249 {
250 *n = 0;
251
252 if (type & TTM_PL_FLAG_VRAM)
253 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
254 if (type & TTM_PL_FLAG_TT)
255 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
256 if (type & TTM_PL_FLAG_SYSTEM)
257 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
258 }
259
260 static void
261 set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
262 {
263 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
264 struct nouveau_fb *pfb = nouveau_fb(drm->device);
265 u32 vram_pages = pfb->ram->size >> PAGE_SHIFT;
266
267 if (nv_device(drm->device)->card_type == NV_10 &&
268 nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
269 nvbo->bo.mem.num_pages < vram_pages / 4) {
270 /*
271 * Make sure that the color and depth buffers are handled
272 * by independent memory controller units. Up to a 9x
273 * speed up when alpha-blending and depth-test are enabled
274 * at the same time.
275 */
276 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
277 nvbo->placement.fpfn = vram_pages / 2;
278 nvbo->placement.lpfn = ~0;
279 } else {
280 nvbo->placement.fpfn = 0;
281 nvbo->placement.lpfn = vram_pages / 2;
282 }
283 }
284 }
285
286 void
287 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
288 {
289 struct ttm_placement *pl = &nvbo->placement;
290 uint32_t flags = TTM_PL_MASK_CACHING |
291 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
292
293 pl->placement = nvbo->placements;
294 set_placement_list(nvbo->placements, &pl->num_placement,
295 type, flags);
296
297 pl->busy_placement = nvbo->busy_placements;
298 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
299 type | busy, flags);
300
301 set_placement_range(nvbo, type);
302 }
303
304 int
305 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
306 {
307 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
308 struct ttm_buffer_object *bo = &nvbo->bo;
309 int ret;
310
311 ret = ttm_bo_reserve(bo, false, false, false, 0);
312 if (ret)
313 goto out;
314
315 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
316 NV_ERROR(drm, "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
317 1 << bo->mem.mem_type, memtype);
318 ret = -EINVAL;
319 goto out;
320 }
321
322 if (nvbo->pin_refcnt++)
323 goto out;
324
325 nouveau_bo_placement_set(nvbo, memtype, 0);
326
327 ret = nouveau_bo_validate(nvbo, false, false);
328 if (ret == 0) {
329 switch (bo->mem.mem_type) {
330 case TTM_PL_VRAM:
331 drm->gem.vram_available -= bo->mem.size;
332 break;
333 case TTM_PL_TT:
334 drm->gem.gart_available -= bo->mem.size;
335 break;
336 default:
337 break;
338 }
339 }
340 out:
341 ttm_bo_unreserve(bo);
342 return ret;
343 }
344
345 int
346 nouveau_bo_unpin(struct nouveau_bo *nvbo)
347 {
348 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
349 struct ttm_buffer_object *bo = &nvbo->bo;
350 int ret, ref;
351
352 ret = ttm_bo_reserve(bo, false, false, false, 0);
353 if (ret)
354 return ret;
355
356 ref = --nvbo->pin_refcnt;
357 WARN_ON_ONCE(ref < 0);
358 if (ref)
359 goto out;
360
361 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
362
363 ret = nouveau_bo_validate(nvbo, false, false);
364 if (ret == 0) {
365 switch (bo->mem.mem_type) {
366 case TTM_PL_VRAM:
367 drm->gem.vram_available += bo->mem.size;
368 break;
369 case TTM_PL_TT:
370 drm->gem.gart_available += bo->mem.size;
371 break;
372 default:
373 break;
374 }
375 }
376
377 out:
378 ttm_bo_unreserve(bo);
379 return ret;
380 }
381
382 int
383 nouveau_bo_map(struct nouveau_bo *nvbo)
384 {
385 int ret;
386
387 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
388 if (ret)
389 return ret;
390
391 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
392 ttm_bo_unreserve(&nvbo->bo);
393 return ret;
394 }
395
396 void
397 nouveau_bo_unmap(struct nouveau_bo *nvbo)
398 {
399 if (nvbo)
400 ttm_bo_kunmap(&nvbo->kmap);
401 }
402
403 int
404 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
405 bool no_wait_gpu)
406 {
407 int ret;
408
409 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement,
410 interruptible, no_wait_gpu);
411 if (ret)
412 return ret;
413
414 return 0;
415 }
416
417 u16
418 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
419 {
420 bool is_iomem;
421 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
422 mem = &mem[index];
423 if (is_iomem)
424 return ioread16_native((void __force __iomem *)mem);
425 else
426 return *mem;
427 }
428
429 void
430 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
431 {
432 bool is_iomem;
433 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
434 mem = &mem[index];
435 if (is_iomem)
436 iowrite16_native(val, (void __force __iomem *)mem);
437 else
438 *mem = val;
439 }
440
441 u32
442 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
443 {
444 bool is_iomem;
445 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
446 mem = &mem[index];
447 if (is_iomem)
448 return ioread32_native((void __force __iomem *)mem);
449 else
450 return *mem;
451 }
452
453 void
454 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
455 {
456 bool is_iomem;
457 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
458 mem = &mem[index];
459 if (is_iomem)
460 iowrite32_native(val, (void __force __iomem *)mem);
461 else
462 *mem = val;
463 }
464
465 static struct ttm_tt *
466 nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size,
467 uint32_t page_flags, struct page *dummy_read)
468 {
469 #if __OS_HAS_AGP
470 struct nouveau_drm *drm = nouveau_bdev(bdev);
471 struct drm_device *dev = drm->dev;
472
473 if (drm->agp.stat == ENABLED) {
474 return ttm_agp_tt_create(bdev, dev->agp->bridge, size,
475 page_flags, dummy_read);
476 }
477 #endif
478
479 return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read);
480 }
481
482 static int
483 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
484 {
485 /* We'll do this from user space. */
486 return 0;
487 }
488
489 static int
490 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
491 struct ttm_mem_type_manager *man)
492 {
493 struct nouveau_drm *drm = nouveau_bdev(bdev);
494
495 switch (type) {
496 case TTM_PL_SYSTEM:
497 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
498 man->available_caching = TTM_PL_MASK_CACHING;
499 man->default_caching = TTM_PL_FLAG_CACHED;
500 break;
501 case TTM_PL_VRAM:
502 if (nv_device(drm->device)->card_type >= NV_50) {
503 man->func = &nouveau_vram_manager;
504 man->io_reserve_fastpath = false;
505 man->use_io_reserve_lru = true;
506 } else {
507 man->func = &ttm_bo_manager_func;
508 }
509 man->flags = TTM_MEMTYPE_FLAG_FIXED |
510 TTM_MEMTYPE_FLAG_MAPPABLE;
511 man->available_caching = TTM_PL_FLAG_UNCACHED |
512 TTM_PL_FLAG_WC;
513 man->default_caching = TTM_PL_FLAG_WC;
514 break;
515 case TTM_PL_TT:
516 if (nv_device(drm->device)->card_type >= NV_50)
517 man->func = &nouveau_gart_manager;
518 else
519 if (drm->agp.stat != ENABLED)
520 man->func = &nv04_gart_manager;
521 else
522 man->func = &ttm_bo_manager_func;
523
524 if (drm->agp.stat == ENABLED) {
525 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
526 man->available_caching = TTM_PL_FLAG_UNCACHED |
527 TTM_PL_FLAG_WC;
528 man->default_caching = TTM_PL_FLAG_WC;
529 } else {
530 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
531 TTM_MEMTYPE_FLAG_CMA;
532 man->available_caching = TTM_PL_MASK_CACHING;
533 man->default_caching = TTM_PL_FLAG_CACHED;
534 }
535
536 break;
537 default:
538 return -EINVAL;
539 }
540 return 0;
541 }
542
543 static void
544 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
545 {
546 struct nouveau_bo *nvbo = nouveau_bo(bo);
547
548 switch (bo->mem.mem_type) {
549 case TTM_PL_VRAM:
550 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
551 TTM_PL_FLAG_SYSTEM);
552 break;
553 default:
554 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
555 break;
556 }
557
558 *pl = nvbo->placement;
559 }
560
561
562 /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
563 * TTM_PL_{VRAM,TT} directly.
564 */
565
566 static int
567 nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
568 struct nouveau_bo *nvbo, bool evict,
569 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
570 {
571 struct nouveau_fence *fence = NULL;
572 int ret;
573
574 ret = nouveau_fence_new(chan, false, &fence);
575 if (ret)
576 return ret;
577
578 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, evict,
579 no_wait_gpu, new_mem);
580 nouveau_fence_unref(&fence);
581 return ret;
582 }
583
584 static int
585 nve0_bo_move_init(struct nouveau_channel *chan, u32 handle)
586 {
587 int ret = RING_SPACE(chan, 2);
588 if (ret == 0) {
589 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
590 OUT_RING (chan, handle & 0x0000ffff);
591 FIRE_RING (chan);
592 }
593 return ret;
594 }
595
596 static int
597 nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
598 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
599 {
600 struct nouveau_mem *node = old_mem->mm_node;
601 int ret = RING_SPACE(chan, 10);
602 if (ret == 0) {
603 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
604 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
605 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
606 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
607 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
608 OUT_RING (chan, PAGE_SIZE);
609 OUT_RING (chan, PAGE_SIZE);
610 OUT_RING (chan, PAGE_SIZE);
611 OUT_RING (chan, new_mem->num_pages);
612 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
613 }
614 return ret;
615 }
616
617 static int
618 nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
619 {
620 int ret = RING_SPACE(chan, 2);
621 if (ret == 0) {
622 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
623 OUT_RING (chan, handle);
624 }
625 return ret;
626 }
627
628 static int
629 nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
630 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
631 {
632 struct nouveau_mem *node = old_mem->mm_node;
633 u64 src_offset = node->vma[0].offset;
634 u64 dst_offset = node->vma[1].offset;
635 u32 page_count = new_mem->num_pages;
636 int ret;
637
638 page_count = new_mem->num_pages;
639 while (page_count) {
640 int line_count = (page_count > 8191) ? 8191 : page_count;
641
642 ret = RING_SPACE(chan, 11);
643 if (ret)
644 return ret;
645
646 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8);
647 OUT_RING (chan, upper_32_bits(src_offset));
648 OUT_RING (chan, lower_32_bits(src_offset));
649 OUT_RING (chan, upper_32_bits(dst_offset));
650 OUT_RING (chan, lower_32_bits(dst_offset));
651 OUT_RING (chan, PAGE_SIZE);
652 OUT_RING (chan, PAGE_SIZE);
653 OUT_RING (chan, PAGE_SIZE);
654 OUT_RING (chan, line_count);
655 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
656 OUT_RING (chan, 0x00000110);
657
658 page_count -= line_count;
659 src_offset += (PAGE_SIZE * line_count);
660 dst_offset += (PAGE_SIZE * line_count);
661 }
662
663 return 0;
664 }
665
666 static int
667 nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
668 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
669 {
670 struct nouveau_mem *node = old_mem->mm_node;
671 u64 src_offset = node->vma[0].offset;
672 u64 dst_offset = node->vma[1].offset;
673 u32 page_count = new_mem->num_pages;
674 int ret;
675
676 page_count = new_mem->num_pages;
677 while (page_count) {
678 int line_count = (page_count > 2047) ? 2047 : page_count;
679
680 ret = RING_SPACE(chan, 12);
681 if (ret)
682 return ret;
683
684 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
685 OUT_RING (chan, upper_32_bits(dst_offset));
686 OUT_RING (chan, lower_32_bits(dst_offset));
687 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
688 OUT_RING (chan, upper_32_bits(src_offset));
689 OUT_RING (chan, lower_32_bits(src_offset));
690 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
691 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
692 OUT_RING (chan, PAGE_SIZE); /* line_length */
693 OUT_RING (chan, line_count);
694 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
695 OUT_RING (chan, 0x00100110);
696
697 page_count -= line_count;
698 src_offset += (PAGE_SIZE * line_count);
699 dst_offset += (PAGE_SIZE * line_count);
700 }
701
702 return 0;
703 }
704
705 static int
706 nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
707 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
708 {
709 struct nouveau_mem *node = old_mem->mm_node;
710 u64 src_offset = node->vma[0].offset;
711 u64 dst_offset = node->vma[1].offset;
712 u32 page_count = new_mem->num_pages;
713 int ret;
714
715 page_count = new_mem->num_pages;
716 while (page_count) {
717 int line_count = (page_count > 8191) ? 8191 : page_count;
718
719 ret = RING_SPACE(chan, 11);
720 if (ret)
721 return ret;
722
723 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
724 OUT_RING (chan, upper_32_bits(src_offset));
725 OUT_RING (chan, lower_32_bits(src_offset));
726 OUT_RING (chan, upper_32_bits(dst_offset));
727 OUT_RING (chan, lower_32_bits(dst_offset));
728 OUT_RING (chan, PAGE_SIZE);
729 OUT_RING (chan, PAGE_SIZE);
730 OUT_RING (chan, PAGE_SIZE);
731 OUT_RING (chan, line_count);
732 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1);
733 OUT_RING (chan, 0x00000110);
734
735 page_count -= line_count;
736 src_offset += (PAGE_SIZE * line_count);
737 dst_offset += (PAGE_SIZE * line_count);
738 }
739
740 return 0;
741 }
742
743 static int
744 nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
745 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
746 {
747 struct nouveau_mem *node = old_mem->mm_node;
748 int ret = RING_SPACE(chan, 7);
749 if (ret == 0) {
750 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
751 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
752 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
753 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
754 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
755 OUT_RING (chan, 0x00000000 /* COPY */);
756 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
757 }
758 return ret;
759 }
760
761 static int
762 nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
763 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
764 {
765 struct nouveau_mem *node = old_mem->mm_node;
766 int ret = RING_SPACE(chan, 7);
767 if (ret == 0) {
768 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
769 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
770 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
771 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
772 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
773 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
774 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */);
775 }
776 return ret;
777 }
778
779 static int
780 nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
781 {
782 int ret = RING_SPACE(chan, 6);
783 if (ret == 0) {
784 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
785 OUT_RING (chan, handle);
786 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
787 OUT_RING (chan, NvNotify0);
788 OUT_RING (chan, NvDmaFB);
789 OUT_RING (chan, NvDmaFB);
790 }
791
792 return ret;
793 }
794
795 static int
796 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
797 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
798 {
799 struct nouveau_mem *node = old_mem->mm_node;
800 struct nouveau_bo *nvbo = nouveau_bo(bo);
801 u64 length = (new_mem->num_pages << PAGE_SHIFT);
802 u64 src_offset = node->vma[0].offset;
803 u64 dst_offset = node->vma[1].offset;
804 int ret;
805
806 while (length) {
807 u32 amount, stride, height;
808
809 amount = min(length, (u64)(4 * 1024 * 1024));
810 stride = 16 * 4;
811 height = amount / stride;
812
813 if (old_mem->mem_type == TTM_PL_VRAM &&
814 nouveau_bo_tile_layout(nvbo)) {
815 ret = RING_SPACE(chan, 8);
816 if (ret)
817 return ret;
818
819 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
820 OUT_RING (chan, 0);
821 OUT_RING (chan, 0);
822 OUT_RING (chan, stride);
823 OUT_RING (chan, height);
824 OUT_RING (chan, 1);
825 OUT_RING (chan, 0);
826 OUT_RING (chan, 0);
827 } else {
828 ret = RING_SPACE(chan, 2);
829 if (ret)
830 return ret;
831
832 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
833 OUT_RING (chan, 1);
834 }
835 if (new_mem->mem_type == TTM_PL_VRAM &&
836 nouveau_bo_tile_layout(nvbo)) {
837 ret = RING_SPACE(chan, 8);
838 if (ret)
839 return ret;
840
841 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
842 OUT_RING (chan, 0);
843 OUT_RING (chan, 0);
844 OUT_RING (chan, stride);
845 OUT_RING (chan, height);
846 OUT_RING (chan, 1);
847 OUT_RING (chan, 0);
848 OUT_RING (chan, 0);
849 } else {
850 ret = RING_SPACE(chan, 2);
851 if (ret)
852 return ret;
853
854 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
855 OUT_RING (chan, 1);
856 }
857
858 ret = RING_SPACE(chan, 14);
859 if (ret)
860 return ret;
861
862 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
863 OUT_RING (chan, upper_32_bits(src_offset));
864 OUT_RING (chan, upper_32_bits(dst_offset));
865 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
866 OUT_RING (chan, lower_32_bits(src_offset));
867 OUT_RING (chan, lower_32_bits(dst_offset));
868 OUT_RING (chan, stride);
869 OUT_RING (chan, stride);
870 OUT_RING (chan, stride);
871 OUT_RING (chan, height);
872 OUT_RING (chan, 0x00000101);
873 OUT_RING (chan, 0x00000000);
874 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
875 OUT_RING (chan, 0);
876
877 length -= amount;
878 src_offset += amount;
879 dst_offset += amount;
880 }
881
882 return 0;
883 }
884
885 static int
886 nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
887 {
888 int ret = RING_SPACE(chan, 4);
889 if (ret == 0) {
890 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
891 OUT_RING (chan, handle);
892 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
893 OUT_RING (chan, NvNotify0);
894 }
895
896 return ret;
897 }
898
899 static inline uint32_t
900 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
901 struct nouveau_channel *chan, struct ttm_mem_reg *mem)
902 {
903 if (mem->mem_type == TTM_PL_TT)
904 return NvDmaTT;
905 return NvDmaFB;
906 }
907
908 static int
909 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
910 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
911 {
912 u32 src_offset = old_mem->start << PAGE_SHIFT;
913 u32 dst_offset = new_mem->start << PAGE_SHIFT;
914 u32 page_count = new_mem->num_pages;
915 int ret;
916
917 ret = RING_SPACE(chan, 3);
918 if (ret)
919 return ret;
920
921 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
922 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
923 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
924
925 page_count = new_mem->num_pages;
926 while (page_count) {
927 int line_count = (page_count > 2047) ? 2047 : page_count;
928
929 ret = RING_SPACE(chan, 11);
930 if (ret)
931 return ret;
932
933 BEGIN_NV04(chan, NvSubCopy,
934 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
935 OUT_RING (chan, src_offset);
936 OUT_RING (chan, dst_offset);
937 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
938 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
939 OUT_RING (chan, PAGE_SIZE); /* line_length */
940 OUT_RING (chan, line_count);
941 OUT_RING (chan, 0x00000101);
942 OUT_RING (chan, 0x00000000);
943 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
944 OUT_RING (chan, 0);
945
946 page_count -= line_count;
947 src_offset += (PAGE_SIZE * line_count);
948 dst_offset += (PAGE_SIZE * line_count);
949 }
950
951 return 0;
952 }
953
954 static int
955 nouveau_vma_getmap(struct nouveau_channel *chan, struct nouveau_bo *nvbo,
956 struct ttm_mem_reg *mem, struct nouveau_vma *vma)
957 {
958 struct nouveau_mem *node = mem->mm_node;
959 int ret;
960
961 ret = nouveau_vm_get(nv_client(chan->cli)->vm, mem->num_pages <<
962 PAGE_SHIFT, node->page_shift,
963 NV_MEM_ACCESS_RW, vma);
964 if (ret)
965 return ret;
966
967 if (mem->mem_type == TTM_PL_VRAM)
968 nouveau_vm_map(vma, node);
969 else
970 nouveau_vm_map_sg(vma, 0, mem->num_pages << PAGE_SHIFT, node);
971
972 return 0;
973 }
974
975 static int
976 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
977 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
978 {
979 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
980 struct nouveau_channel *chan = chan = drm->ttm.chan;
981 struct nouveau_bo *nvbo = nouveau_bo(bo);
982 struct ttm_mem_reg *old_mem = &bo->mem;
983 int ret;
984
985 mutex_lock_nested(&chan->cli->mutex, SINGLE_DEPTH_NESTING);
986
987 /* create temporary vmas for the transfer and attach them to the
988 * old nouveau_mem node, these will get cleaned up after ttm has
989 * destroyed the ttm_mem_reg
990 */
991 if (nv_device(drm->device)->card_type >= NV_50) {
992 struct nouveau_mem *node = old_mem->mm_node;
993
994 ret = nouveau_vma_getmap(chan, nvbo, old_mem, &node->vma[0]);
995 if (ret)
996 goto out;
997
998 ret = nouveau_vma_getmap(chan, nvbo, new_mem, &node->vma[1]);
999 if (ret)
1000 goto out;
1001 }
1002
1003 ret = drm->ttm.move(chan, bo, &bo->mem, new_mem);
1004 if (ret == 0) {
1005 ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict,
1006 no_wait_gpu, new_mem);
1007 }
1008
1009 out:
1010 mutex_unlock(&chan->cli->mutex);
1011 return ret;
1012 }
1013
1014 void
1015 nouveau_bo_move_init(struct nouveau_drm *drm)
1016 {
1017 static const struct {
1018 const char *name;
1019 int engine;
1020 u32 oclass;
1021 int (*exec)(struct nouveau_channel *,
1022 struct ttm_buffer_object *,
1023 struct ttm_mem_reg *, struct ttm_mem_reg *);
1024 int (*init)(struct nouveau_channel *, u32 handle);
1025 } _methods[] = {
1026 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
1027 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1028 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
1029 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
1030 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
1031 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
1032 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
1033 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
1034 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
1035 {},
1036 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init },
1037 }, *mthd = _methods;
1038 const char *name = "CPU";
1039 int ret;
1040
1041 do {
1042 struct nouveau_object *object;
1043 struct nouveau_channel *chan;
1044 u32 handle = (mthd->engine << 16) | mthd->oclass;
1045
1046 if (mthd->engine)
1047 chan = drm->cechan;
1048 else
1049 chan = drm->channel;
1050 if (chan == NULL)
1051 continue;
1052
1053 ret = nouveau_object_new(nv_object(drm), chan->handle, handle,
1054 mthd->oclass, NULL, 0, &object);
1055 if (ret == 0) {
1056 ret = mthd->init(chan, handle);
1057 if (ret) {
1058 nouveau_object_del(nv_object(drm),
1059 chan->handle, handle);
1060 continue;
1061 }
1062
1063 drm->ttm.move = mthd->exec;
1064 drm->ttm.chan = chan;
1065 name = mthd->name;
1066 break;
1067 }
1068 } while ((++mthd)->exec);
1069
1070 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
1071 }
1072
1073 static int
1074 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
1075 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1076 {
1077 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
1078 struct ttm_placement placement;
1079 struct ttm_mem_reg tmp_mem;
1080 int ret;
1081
1082 placement.fpfn = placement.lpfn = 0;
1083 placement.num_placement = placement.num_busy_placement = 1;
1084 placement.placement = placement.busy_placement = &placement_memtype;
1085
1086 tmp_mem = *new_mem;
1087 tmp_mem.mm_node = NULL;
1088 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1089 if (ret)
1090 return ret;
1091
1092 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
1093 if (ret)
1094 goto out;
1095
1096 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_mem);
1097 if (ret)
1098 goto out;
1099
1100 ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
1101 out:
1102 ttm_bo_mem_put(bo, &tmp_mem);
1103 return ret;
1104 }
1105
1106 static int
1107 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
1108 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1109 {
1110 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
1111 struct ttm_placement placement;
1112 struct ttm_mem_reg tmp_mem;
1113 int ret;
1114
1115 placement.fpfn = placement.lpfn = 0;
1116 placement.num_placement = placement.num_busy_placement = 1;
1117 placement.placement = placement.busy_placement = &placement_memtype;
1118
1119 tmp_mem = *new_mem;
1120 tmp_mem.mm_node = NULL;
1121 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1122 if (ret)
1123 return ret;
1124
1125 ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
1126 if (ret)
1127 goto out;
1128
1129 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_mem);
1130 if (ret)
1131 goto out;
1132
1133 out:
1134 ttm_bo_mem_put(bo, &tmp_mem);
1135 return ret;
1136 }
1137
1138 static void
1139 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
1140 {
1141 struct nouveau_bo *nvbo = nouveau_bo(bo);
1142 struct nouveau_vma *vma;
1143
1144 /* ttm can now (stupidly) pass the driver bos it didn't create... */
1145 if (bo->destroy != nouveau_bo_del_ttm)
1146 return;
1147
1148 list_for_each_entry(vma, &nvbo->vma_list, head) {
1149 if (new_mem && new_mem->mem_type == TTM_PL_VRAM) {
1150 nouveau_vm_map(vma, new_mem->mm_node);
1151 } else
1152 if (new_mem && new_mem->mem_type == TTM_PL_TT &&
1153 nvbo->page_shift == vma->vm->vmm->spg_shift) {
1154 if (((struct nouveau_mem *)new_mem->mm_node)->sg)
1155 nouveau_vm_map_sg_table(vma, 0, new_mem->
1156 num_pages << PAGE_SHIFT,
1157 new_mem->mm_node);
1158 else
1159 nouveau_vm_map_sg(vma, 0, new_mem->
1160 num_pages << PAGE_SHIFT,
1161 new_mem->mm_node);
1162 } else {
1163 nouveau_vm_unmap(vma);
1164 }
1165 }
1166 }
1167
1168 static int
1169 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
1170 struct nouveau_drm_tile **new_tile)
1171 {
1172 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1173 struct drm_device *dev = drm->dev;
1174 struct nouveau_bo *nvbo = nouveau_bo(bo);
1175 u64 offset = new_mem->start << PAGE_SHIFT;
1176
1177 *new_tile = NULL;
1178 if (new_mem->mem_type != TTM_PL_VRAM)
1179 return 0;
1180
1181 if (nv_device(drm->device)->card_type >= NV_10) {
1182 *new_tile = nv10_bo_set_tiling(dev, offset, new_mem->size,
1183 nvbo->tile_mode,
1184 nvbo->tile_flags);
1185 }
1186
1187 return 0;
1188 }
1189
1190 static void
1191 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1192 struct nouveau_drm_tile *new_tile,
1193 struct nouveau_drm_tile **old_tile)
1194 {
1195 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1196 struct drm_device *dev = drm->dev;
1197
1198 nv10_bo_put_tile_region(dev, *old_tile, bo->sync_obj);
1199 *old_tile = new_tile;
1200 }
1201
1202 static int
1203 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
1204 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1205 {
1206 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1207 struct nouveau_bo *nvbo = nouveau_bo(bo);
1208 struct ttm_mem_reg *old_mem = &bo->mem;
1209 struct nouveau_drm_tile *new_tile = NULL;
1210 int ret = 0;
1211
1212 if (nv_device(drm->device)->card_type < NV_50) {
1213 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
1214 if (ret)
1215 return ret;
1216 }
1217
1218 /* Fake bo copy. */
1219 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1220 BUG_ON(bo->mem.mm_node != NULL);
1221 bo->mem = *new_mem;
1222 new_mem->mm_node = NULL;
1223 goto out;
1224 }
1225
1226 /* CPU copy if we have no accelerated method available */
1227 if (!drm->ttm.move) {
1228 ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
1229 goto out;
1230 }
1231
1232 /* Hardware assisted copy. */
1233 if (new_mem->mem_type == TTM_PL_SYSTEM)
1234 ret = nouveau_bo_move_flipd(bo, evict, intr,
1235 no_wait_gpu, new_mem);
1236 else if (old_mem->mem_type == TTM_PL_SYSTEM)
1237 ret = nouveau_bo_move_flips(bo, evict, intr,
1238 no_wait_gpu, new_mem);
1239 else
1240 ret = nouveau_bo_move_m2mf(bo, evict, intr,
1241 no_wait_gpu, new_mem);
1242
1243 if (!ret)
1244 goto out;
1245
1246 /* Fallback to software copy. */
1247 ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
1248
1249 out:
1250 if (nv_device(drm->device)->card_type < NV_50) {
1251 if (ret)
1252 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1253 else
1254 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1255 }
1256
1257 return ret;
1258 }
1259
1260 static int
1261 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1262 {
1263 return 0;
1264 }
1265
1266 static int
1267 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1268 {
1269 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
1270 struct nouveau_drm *drm = nouveau_bdev(bdev);
1271 struct drm_device *dev = drm->dev;
1272 int ret;
1273
1274 mem->bus.addr = NULL;
1275 mem->bus.offset = 0;
1276 mem->bus.size = mem->num_pages << PAGE_SHIFT;
1277 mem->bus.base = 0;
1278 mem->bus.is_iomem = false;
1279 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
1280 return -EINVAL;
1281 switch (mem->mem_type) {
1282 case TTM_PL_SYSTEM:
1283 /* System memory */
1284 return 0;
1285 case TTM_PL_TT:
1286 #if __OS_HAS_AGP
1287 if (drm->agp.stat == ENABLED) {
1288 mem->bus.offset = mem->start << PAGE_SHIFT;
1289 mem->bus.base = drm->agp.base;
1290 mem->bus.is_iomem = !dev->agp->cant_use_aperture;
1291 }
1292 #endif
1293 break;
1294 case TTM_PL_VRAM:
1295 mem->bus.offset = mem->start << PAGE_SHIFT;
1296 mem->bus.base = pci_resource_start(dev->pdev, 1);
1297 mem->bus.is_iomem = true;
1298 if (nv_device(drm->device)->card_type >= NV_50) {
1299 struct nouveau_bar *bar = nouveau_bar(drm->device);
1300 struct nouveau_mem *node = mem->mm_node;
1301
1302 ret = bar->umap(bar, node, NV_MEM_ACCESS_RW,
1303 &node->bar_vma);
1304 if (ret)
1305 return ret;
1306
1307 mem->bus.offset = node->bar_vma.offset;
1308 }
1309 break;
1310 default:
1311 return -EINVAL;
1312 }
1313 return 0;
1314 }
1315
1316 static void
1317 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1318 {
1319 struct nouveau_drm *drm = nouveau_bdev(bdev);
1320 struct nouveau_bar *bar = nouveau_bar(drm->device);
1321 struct nouveau_mem *node = mem->mm_node;
1322
1323 if (!node->bar_vma.node)
1324 return;
1325
1326 bar->unmap(bar, &node->bar_vma);
1327 }
1328
1329 static int
1330 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1331 {
1332 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1333 struct nouveau_bo *nvbo = nouveau_bo(bo);
1334 struct nouveau_device *device = nv_device(drm->device);
1335 u32 mappable = pci_resource_len(device->pdev, 1) >> PAGE_SHIFT;
1336
1337 /* as long as the bo isn't in vram, and isn't tiled, we've got
1338 * nothing to do here.
1339 */
1340 if (bo->mem.mem_type != TTM_PL_VRAM) {
1341 if (nv_device(drm->device)->card_type < NV_50 ||
1342 !nouveau_bo_tile_layout(nvbo))
1343 return 0;
1344 }
1345
1346 /* make sure bo is in mappable vram */
1347 if (bo->mem.start + bo->mem.num_pages < mappable)
1348 return 0;
1349
1350
1351 nvbo->placement.fpfn = 0;
1352 nvbo->placement.lpfn = mappable;
1353 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
1354 return nouveau_bo_validate(nvbo, false, false);
1355 }
1356
1357 static int
1358 nouveau_ttm_tt_populate(struct ttm_tt *ttm)
1359 {
1360 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1361 struct nouveau_drm *drm;
1362 struct drm_device *dev;
1363 unsigned i;
1364 int r;
1365 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1366
1367 if (ttm->state != tt_unpopulated)
1368 return 0;
1369
1370 if (slave && ttm->sg) {
1371 /* make userspace faulting work */
1372 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1373 ttm_dma->dma_address, ttm->num_pages);
1374 ttm->state = tt_unbound;
1375 return 0;
1376 }
1377
1378 drm = nouveau_bdev(ttm->bdev);
1379 dev = drm->dev;
1380
1381 #if __OS_HAS_AGP
1382 if (drm->agp.stat == ENABLED) {
1383 return ttm_agp_tt_populate(ttm);
1384 }
1385 #endif
1386
1387 #ifdef CONFIG_SWIOTLB
1388 if (swiotlb_nr_tbl()) {
1389 return ttm_dma_populate((void *)ttm, dev->dev);
1390 }
1391 #endif
1392
1393 r = ttm_pool_populate(ttm);
1394 if (r) {
1395 return r;
1396 }
1397
1398 for (i = 0; i < ttm->num_pages; i++) {
1399 ttm_dma->dma_address[i] = pci_map_page(dev->pdev, ttm->pages[i],
1400 0, PAGE_SIZE,
1401 PCI_DMA_BIDIRECTIONAL);
1402 if (pci_dma_mapping_error(dev->pdev, ttm_dma->dma_address[i])) {
1403 while (--i) {
1404 pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
1405 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1406 ttm_dma->dma_address[i] = 0;
1407 }
1408 ttm_pool_unpopulate(ttm);
1409 return -EFAULT;
1410 }
1411 }
1412 return 0;
1413 }
1414
1415 static void
1416 nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1417 {
1418 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1419 struct nouveau_drm *drm;
1420 struct drm_device *dev;
1421 unsigned i;
1422 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1423
1424 if (slave)
1425 return;
1426
1427 drm = nouveau_bdev(ttm->bdev);
1428 dev = drm->dev;
1429
1430 #if __OS_HAS_AGP
1431 if (drm->agp.stat == ENABLED) {
1432 ttm_agp_tt_unpopulate(ttm);
1433 return;
1434 }
1435 #endif
1436
1437 #ifdef CONFIG_SWIOTLB
1438 if (swiotlb_nr_tbl()) {
1439 ttm_dma_unpopulate((void *)ttm, dev->dev);
1440 return;
1441 }
1442 #endif
1443
1444 for (i = 0; i < ttm->num_pages; i++) {
1445 if (ttm_dma->dma_address[i]) {
1446 pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
1447 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1448 }
1449 }
1450
1451 ttm_pool_unpopulate(ttm);
1452 }
1453
1454 void
1455 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
1456 {
1457 struct nouveau_fence *old_fence = NULL;
1458
1459 if (likely(fence))
1460 nouveau_fence_ref(fence);
1461
1462 spin_lock(&nvbo->bo.bdev->fence_lock);
1463 old_fence = nvbo->bo.sync_obj;
1464 nvbo->bo.sync_obj = fence;
1465 spin_unlock(&nvbo->bo.bdev->fence_lock);
1466
1467 nouveau_fence_unref(&old_fence);
1468 }
1469
1470 static void
1471 nouveau_bo_fence_unref(void **sync_obj)
1472 {
1473 nouveau_fence_unref((struct nouveau_fence **)sync_obj);
1474 }
1475
1476 static void *
1477 nouveau_bo_fence_ref(void *sync_obj)
1478 {
1479 return nouveau_fence_ref(sync_obj);
1480 }
1481
1482 static bool
1483 nouveau_bo_fence_signalled(void *sync_obj)
1484 {
1485 return nouveau_fence_done(sync_obj);
1486 }
1487
1488 static int
1489 nouveau_bo_fence_wait(void *sync_obj, bool lazy, bool intr)
1490 {
1491 return nouveau_fence_wait(sync_obj, lazy, intr);
1492 }
1493
1494 static int
1495 nouveau_bo_fence_flush(void *sync_obj)
1496 {
1497 return 0;
1498 }
1499
1500 struct ttm_bo_driver nouveau_bo_driver = {
1501 .ttm_tt_create = &nouveau_ttm_tt_create,
1502 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1503 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1504 .invalidate_caches = nouveau_bo_invalidate_caches,
1505 .init_mem_type = nouveau_bo_init_mem_type,
1506 .evict_flags = nouveau_bo_evict_flags,
1507 .move_notify = nouveau_bo_move_ntfy,
1508 .move = nouveau_bo_move,
1509 .verify_access = nouveau_bo_verify_access,
1510 .sync_obj_signaled = nouveau_bo_fence_signalled,
1511 .sync_obj_wait = nouveau_bo_fence_wait,
1512 .sync_obj_flush = nouveau_bo_fence_flush,
1513 .sync_obj_unref = nouveau_bo_fence_unref,
1514 .sync_obj_ref = nouveau_bo_fence_ref,
1515 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1516 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1517 .io_mem_free = &nouveau_ttm_io_mem_free,
1518 };
1519
1520 struct nouveau_vma *
1521 nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm)
1522 {
1523 struct nouveau_vma *vma;
1524 list_for_each_entry(vma, &nvbo->vma_list, head) {
1525 if (vma->vm == vm)
1526 return vma;
1527 }
1528
1529 return NULL;
1530 }
1531
1532 int
1533 nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
1534 struct nouveau_vma *vma)
1535 {
1536 const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
1537 struct nouveau_mem *node = nvbo->bo.mem.mm_node;
1538 int ret;
1539
1540 ret = nouveau_vm_get(vm, size, nvbo->page_shift,
1541 NV_MEM_ACCESS_RW, vma);
1542 if (ret)
1543 return ret;
1544
1545 if (nvbo->bo.mem.mem_type == TTM_PL_VRAM)
1546 nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
1547 else if (nvbo->bo.mem.mem_type == TTM_PL_TT) {
1548 if (node->sg)
1549 nouveau_vm_map_sg_table(vma, 0, size, node);
1550 else
1551 nouveau_vm_map_sg(vma, 0, size, node);
1552 }
1553
1554 list_add_tail(&vma->head, &nvbo->vma_list);
1555 vma->refcount = 1;
1556 return 0;
1557 }
1558
1559 void
1560 nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
1561 {
1562 if (vma->node) {
1563 if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM)
1564 nouveau_vm_unmap(vma);
1565 nouveau_vm_put(vma);
1566 list_del(&vma->head);
1567 }
1568 }
Linux kernel - Deliverables
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