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drm/nv50-nvc0: restrict memtype to those specified at creation time
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_bo.c
1 /*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24 /*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30 #include "drmP.h"
31
32 #include "nouveau_drm.h"
33 #include "nouveau_drv.h"
34 #include "nouveau_dma.h"
35 #include "nouveau_mm.h"
36 #include "nouveau_vm.h"
37
38 #include <linux/log2.h>
39 #include <linux/slab.h>
40
41 static void
42 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
43 {
44 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
45 struct drm_device *dev = dev_priv->dev;
46 struct nouveau_bo *nvbo = nouveau_bo(bo);
47
48 if (unlikely(nvbo->gem))
49 DRM_ERROR("bo %p still attached to GEM object\n", bo);
50
51 nv10_mem_put_tile_region(dev, nvbo->tile, NULL);
52 nouveau_vm_put(&nvbo->vma);
53 kfree(nvbo);
54 }
55
56 static void
57 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
58 int *align, int *size, int *page_shift)
59 {
60 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
61
62 if (dev_priv->card_type < NV_50) {
63 if (nvbo->tile_mode) {
64 if (dev_priv->chipset >= 0x40) {
65 *align = 65536;
66 *size = roundup(*size, 64 * nvbo->tile_mode);
67
68 } else if (dev_priv->chipset >= 0x30) {
69 *align = 32768;
70 *size = roundup(*size, 64 * nvbo->tile_mode);
71
72 } else if (dev_priv->chipset >= 0x20) {
73 *align = 16384;
74 *size = roundup(*size, 64 * nvbo->tile_mode);
75
76 } else if (dev_priv->chipset >= 0x10) {
77 *align = 16384;
78 *size = roundup(*size, 32 * nvbo->tile_mode);
79 }
80 }
81 } else {
82 if (likely(dev_priv->chan_vm)) {
83 if (!(flags & TTM_PL_FLAG_TT) && *size > 256 * 1024)
84 *page_shift = dev_priv->chan_vm->lpg_shift;
85 else
86 *page_shift = dev_priv->chan_vm->spg_shift;
87 } else {
88 *page_shift = 12;
89 }
90
91 *size = roundup(*size, (1 << *page_shift));
92 *align = max((1 << *page_shift), *align);
93 }
94
95 *size = roundup(*size, PAGE_SIZE);
96 }
97
98 int
99 nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
100 int size, int align, uint32_t flags, uint32_t tile_mode,
101 uint32_t tile_flags, struct nouveau_bo **pnvbo)
102 {
103 struct drm_nouveau_private *dev_priv = dev->dev_private;
104 struct nouveau_bo *nvbo;
105 int ret = 0, page_shift = 0;
106
107 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
108 if (!nvbo)
109 return -ENOMEM;
110 INIT_LIST_HEAD(&nvbo->head);
111 INIT_LIST_HEAD(&nvbo->entry);
112 nvbo->tile_mode = tile_mode;
113 nvbo->tile_flags = tile_flags;
114 nvbo->bo.bdev = &dev_priv->ttm.bdev;
115
116 nouveau_bo_fixup_align(nvbo, flags, &align, &size, &page_shift);
117 align >>= PAGE_SHIFT;
118
119 if (dev_priv->chan_vm) {
120 ret = nouveau_vm_get(dev_priv->chan_vm, size, page_shift,
121 NV_MEM_ACCESS_RW, &nvbo->vma);
122 if (ret) {
123 kfree(nvbo);
124 return ret;
125 }
126 }
127
128 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
129 nouveau_bo_placement_set(nvbo, flags, 0);
130
131 nvbo->channel = chan;
132 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
133 ttm_bo_type_device, &nvbo->placement, align, 0,
134 false, NULL, size, nouveau_bo_del_ttm);
135 if (ret) {
136 /* ttm will call nouveau_bo_del_ttm if it fails.. */
137 return ret;
138 }
139 nvbo->channel = NULL;
140
141 if (nvbo->vma.node) {
142 if (nvbo->bo.mem.mem_type == TTM_PL_VRAM)
143 nvbo->bo.offset = nvbo->vma.offset;
144 }
145
146 *pnvbo = nvbo;
147 return 0;
148 }
149
150 static void
151 set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
152 {
153 *n = 0;
154
155 if (type & TTM_PL_FLAG_VRAM)
156 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
157 if (type & TTM_PL_FLAG_TT)
158 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
159 if (type & TTM_PL_FLAG_SYSTEM)
160 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
161 }
162
163 static void
164 set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
165 {
166 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
167 int vram_pages = dev_priv->vram_size >> PAGE_SHIFT;
168
169 if (dev_priv->card_type == NV_10 &&
170 nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
171 nvbo->bo.mem.num_pages < vram_pages / 2) {
172 /*
173 * Make sure that the color and depth buffers are handled
174 * by independent memory controller units. Up to a 9x
175 * speed up when alpha-blending and depth-test are enabled
176 * at the same time.
177 */
178 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
179 nvbo->placement.fpfn = vram_pages / 2;
180 nvbo->placement.lpfn = ~0;
181 } else {
182 nvbo->placement.fpfn = 0;
183 nvbo->placement.lpfn = vram_pages / 2;
184 }
185 }
186 }
187
188 void
189 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
190 {
191 struct ttm_placement *pl = &nvbo->placement;
192 uint32_t flags = TTM_PL_MASK_CACHING |
193 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
194
195 pl->placement = nvbo->placements;
196 set_placement_list(nvbo->placements, &pl->num_placement,
197 type, flags);
198
199 pl->busy_placement = nvbo->busy_placements;
200 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
201 type | busy, flags);
202
203 set_placement_range(nvbo, type);
204 }
205
206 int
207 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
208 {
209 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
210 struct ttm_buffer_object *bo = &nvbo->bo;
211 int ret;
212
213 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
214 NV_ERROR(nouveau_bdev(bo->bdev)->dev,
215 "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
216 1 << bo->mem.mem_type, memtype);
217 return -EINVAL;
218 }
219
220 if (nvbo->pin_refcnt++)
221 return 0;
222
223 ret = ttm_bo_reserve(bo, false, false, false, 0);
224 if (ret)
225 goto out;
226
227 nouveau_bo_placement_set(nvbo, memtype, 0);
228
229 ret = nouveau_bo_validate(nvbo, false, false, false);
230 if (ret == 0) {
231 switch (bo->mem.mem_type) {
232 case TTM_PL_VRAM:
233 dev_priv->fb_aper_free -= bo->mem.size;
234 break;
235 case TTM_PL_TT:
236 dev_priv->gart_info.aper_free -= bo->mem.size;
237 break;
238 default:
239 break;
240 }
241 }
242 ttm_bo_unreserve(bo);
243 out:
244 if (unlikely(ret))
245 nvbo->pin_refcnt--;
246 return ret;
247 }
248
249 int
250 nouveau_bo_unpin(struct nouveau_bo *nvbo)
251 {
252 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
253 struct ttm_buffer_object *bo = &nvbo->bo;
254 int ret;
255
256 if (--nvbo->pin_refcnt)
257 return 0;
258
259 ret = ttm_bo_reserve(bo, false, false, false, 0);
260 if (ret)
261 return ret;
262
263 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
264
265 ret = nouveau_bo_validate(nvbo, false, false, false);
266 if (ret == 0) {
267 switch (bo->mem.mem_type) {
268 case TTM_PL_VRAM:
269 dev_priv->fb_aper_free += bo->mem.size;
270 break;
271 case TTM_PL_TT:
272 dev_priv->gart_info.aper_free += bo->mem.size;
273 break;
274 default:
275 break;
276 }
277 }
278
279 ttm_bo_unreserve(bo);
280 return ret;
281 }
282
283 int
284 nouveau_bo_map(struct nouveau_bo *nvbo)
285 {
286 int ret;
287
288 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
289 if (ret)
290 return ret;
291
292 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
293 ttm_bo_unreserve(&nvbo->bo);
294 return ret;
295 }
296
297 void
298 nouveau_bo_unmap(struct nouveau_bo *nvbo)
299 {
300 if (nvbo)
301 ttm_bo_kunmap(&nvbo->kmap);
302 }
303
304 int
305 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
306 bool no_wait_reserve, bool no_wait_gpu)
307 {
308 int ret;
309
310 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, interruptible,
311 no_wait_reserve, no_wait_gpu);
312 if (ret)
313 return ret;
314
315 if (nvbo->vma.node) {
316 if (nvbo->bo.mem.mem_type == TTM_PL_VRAM)
317 nvbo->bo.offset = nvbo->vma.offset;
318 }
319
320 return 0;
321 }
322
323 u16
324 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
325 {
326 bool is_iomem;
327 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
328 mem = &mem[index];
329 if (is_iomem)
330 return ioread16_native((void __force __iomem *)mem);
331 else
332 return *mem;
333 }
334
335 void
336 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
337 {
338 bool is_iomem;
339 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
340 mem = &mem[index];
341 if (is_iomem)
342 iowrite16_native(val, (void __force __iomem *)mem);
343 else
344 *mem = val;
345 }
346
347 u32
348 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
349 {
350 bool is_iomem;
351 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
352 mem = &mem[index];
353 if (is_iomem)
354 return ioread32_native((void __force __iomem *)mem);
355 else
356 return *mem;
357 }
358
359 void
360 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
361 {
362 bool is_iomem;
363 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
364 mem = &mem[index];
365 if (is_iomem)
366 iowrite32_native(val, (void __force __iomem *)mem);
367 else
368 *mem = val;
369 }
370
371 static struct ttm_backend *
372 nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
373 {
374 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
375 struct drm_device *dev = dev_priv->dev;
376
377 switch (dev_priv->gart_info.type) {
378 #if __OS_HAS_AGP
379 case NOUVEAU_GART_AGP:
380 return ttm_agp_backend_init(bdev, dev->agp->bridge);
381 #endif
382 case NOUVEAU_GART_PDMA:
383 case NOUVEAU_GART_HW:
384 return nouveau_sgdma_init_ttm(dev);
385 default:
386 NV_ERROR(dev, "Unknown GART type %d\n",
387 dev_priv->gart_info.type);
388 break;
389 }
390
391 return NULL;
392 }
393
394 static int
395 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
396 {
397 /* We'll do this from user space. */
398 return 0;
399 }
400
401 static int
402 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
403 struct ttm_mem_type_manager *man)
404 {
405 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
406 struct drm_device *dev = dev_priv->dev;
407
408 switch (type) {
409 case TTM_PL_SYSTEM:
410 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
411 man->available_caching = TTM_PL_MASK_CACHING;
412 man->default_caching = TTM_PL_FLAG_CACHED;
413 break;
414 case TTM_PL_VRAM:
415 if (dev_priv->card_type >= NV_50) {
416 man->func = &nouveau_vram_manager;
417 man->io_reserve_fastpath = false;
418 man->use_io_reserve_lru = true;
419 } else {
420 man->func = &ttm_bo_manager_func;
421 }
422 man->flags = TTM_MEMTYPE_FLAG_FIXED |
423 TTM_MEMTYPE_FLAG_MAPPABLE;
424 man->available_caching = TTM_PL_FLAG_UNCACHED |
425 TTM_PL_FLAG_WC;
426 man->default_caching = TTM_PL_FLAG_WC;
427 break;
428 case TTM_PL_TT:
429 man->func = &ttm_bo_manager_func;
430 switch (dev_priv->gart_info.type) {
431 case NOUVEAU_GART_AGP:
432 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
433 man->available_caching = TTM_PL_FLAG_UNCACHED |
434 TTM_PL_FLAG_WC;
435 man->default_caching = TTM_PL_FLAG_WC;
436 break;
437 case NOUVEAU_GART_PDMA:
438 case NOUVEAU_GART_HW:
439 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
440 TTM_MEMTYPE_FLAG_CMA;
441 man->available_caching = TTM_PL_MASK_CACHING;
442 man->default_caching = TTM_PL_FLAG_CACHED;
443 man->gpu_offset = dev_priv->gart_info.aper_base;
444 break;
445 default:
446 NV_ERROR(dev, "Unknown GART type: %d\n",
447 dev_priv->gart_info.type);
448 return -EINVAL;
449 }
450 break;
451 default:
452 NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
453 return -EINVAL;
454 }
455 return 0;
456 }
457
458 static void
459 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
460 {
461 struct nouveau_bo *nvbo = nouveau_bo(bo);
462
463 switch (bo->mem.mem_type) {
464 case TTM_PL_VRAM:
465 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
466 TTM_PL_FLAG_SYSTEM);
467 break;
468 default:
469 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
470 break;
471 }
472
473 *pl = nvbo->placement;
474 }
475
476
477 /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
478 * TTM_PL_{VRAM,TT} directly.
479 */
480
481 static int
482 nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
483 struct nouveau_bo *nvbo, bool evict,
484 bool no_wait_reserve, bool no_wait_gpu,
485 struct ttm_mem_reg *new_mem)
486 {
487 struct nouveau_fence *fence = NULL;
488 int ret;
489
490 ret = nouveau_fence_new(chan, &fence, true);
491 if (ret)
492 return ret;
493
494 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, evict,
495 no_wait_reserve, no_wait_gpu, new_mem);
496 nouveau_fence_unref(&fence);
497 return ret;
498 }
499
500 static int
501 nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
502 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
503 {
504 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
505 struct nouveau_bo *nvbo = nouveau_bo(bo);
506 u32 page_count = new_mem->num_pages;
507 u64 src_offset, dst_offset;
508 int ret;
509
510 src_offset = old_mem->start << PAGE_SHIFT;
511 if (old_mem->mem_type == TTM_PL_VRAM)
512 src_offset = nvbo->vma.offset;
513 else
514 src_offset += dev_priv->gart_info.aper_base;
515
516 dst_offset = new_mem->start << PAGE_SHIFT;
517 if (new_mem->mem_type == TTM_PL_VRAM)
518 dst_offset = nvbo->vma.offset;
519 else
520 dst_offset += dev_priv->gart_info.aper_base;
521
522 page_count = new_mem->num_pages;
523 while (page_count) {
524 int line_count = (page_count > 2047) ? 2047 : page_count;
525
526 ret = RING_SPACE(chan, 12);
527 if (ret)
528 return ret;
529
530 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0238, 2);
531 OUT_RING (chan, upper_32_bits(dst_offset));
532 OUT_RING (chan, lower_32_bits(dst_offset));
533 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x030c, 6);
534 OUT_RING (chan, upper_32_bits(src_offset));
535 OUT_RING (chan, lower_32_bits(src_offset));
536 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
537 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
538 OUT_RING (chan, PAGE_SIZE); /* line_length */
539 OUT_RING (chan, line_count);
540 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0300, 1);
541 OUT_RING (chan, 0x00100110);
542
543 page_count -= line_count;
544 src_offset += (PAGE_SIZE * line_count);
545 dst_offset += (PAGE_SIZE * line_count);
546 }
547
548 return 0;
549 }
550
551 static int
552 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
553 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
554 {
555 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
556 struct nouveau_bo *nvbo = nouveau_bo(bo);
557 u64 length = (new_mem->num_pages << PAGE_SHIFT);
558 u64 src_offset, dst_offset;
559 int ret;
560
561 src_offset = old_mem->start << PAGE_SHIFT;
562 if (old_mem->mem_type == TTM_PL_VRAM)
563 src_offset = nvbo->vma.offset;
564 else
565 src_offset += dev_priv->gart_info.aper_base;
566
567 dst_offset = new_mem->start << PAGE_SHIFT;
568 if (new_mem->mem_type == TTM_PL_VRAM)
569 dst_offset = nvbo->vma.offset;
570 else
571 dst_offset += dev_priv->gart_info.aper_base;
572
573 while (length) {
574 u32 amount, stride, height;
575
576 amount = min(length, (u64)(4 * 1024 * 1024));
577 stride = 16 * 4;
578 height = amount / stride;
579
580 if (new_mem->mem_type == TTM_PL_VRAM &&
581 nouveau_bo_tile_layout(nvbo)) {
582 ret = RING_SPACE(chan, 8);
583 if (ret)
584 return ret;
585
586 BEGIN_RING(chan, NvSubM2MF, 0x0200, 7);
587 OUT_RING (chan, 0);
588 OUT_RING (chan, 0);
589 OUT_RING (chan, stride);
590 OUT_RING (chan, height);
591 OUT_RING (chan, 1);
592 OUT_RING (chan, 0);
593 OUT_RING (chan, 0);
594 } else {
595 ret = RING_SPACE(chan, 2);
596 if (ret)
597 return ret;
598
599 BEGIN_RING(chan, NvSubM2MF, 0x0200, 1);
600 OUT_RING (chan, 1);
601 }
602 if (old_mem->mem_type == TTM_PL_VRAM &&
603 nouveau_bo_tile_layout(nvbo)) {
604 ret = RING_SPACE(chan, 8);
605 if (ret)
606 return ret;
607
608 BEGIN_RING(chan, NvSubM2MF, 0x021c, 7);
609 OUT_RING (chan, 0);
610 OUT_RING (chan, 0);
611 OUT_RING (chan, stride);
612 OUT_RING (chan, height);
613 OUT_RING (chan, 1);
614 OUT_RING (chan, 0);
615 OUT_RING (chan, 0);
616 } else {
617 ret = RING_SPACE(chan, 2);
618 if (ret)
619 return ret;
620
621 BEGIN_RING(chan, NvSubM2MF, 0x021c, 1);
622 OUT_RING (chan, 1);
623 }
624
625 ret = RING_SPACE(chan, 14);
626 if (ret)
627 return ret;
628
629 BEGIN_RING(chan, NvSubM2MF, 0x0238, 2);
630 OUT_RING (chan, upper_32_bits(src_offset));
631 OUT_RING (chan, upper_32_bits(dst_offset));
632 BEGIN_RING(chan, NvSubM2MF, 0x030c, 8);
633 OUT_RING (chan, lower_32_bits(src_offset));
634 OUT_RING (chan, lower_32_bits(dst_offset));
635 OUT_RING (chan, stride);
636 OUT_RING (chan, stride);
637 OUT_RING (chan, stride);
638 OUT_RING (chan, height);
639 OUT_RING (chan, 0x00000101);
640 OUT_RING (chan, 0x00000000);
641 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
642 OUT_RING (chan, 0);
643
644 length -= amount;
645 src_offset += amount;
646 dst_offset += amount;
647 }
648
649 return 0;
650 }
651
652 static inline uint32_t
653 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
654 struct nouveau_channel *chan, struct ttm_mem_reg *mem)
655 {
656 if (mem->mem_type == TTM_PL_TT)
657 return chan->gart_handle;
658 return chan->vram_handle;
659 }
660
661 static int
662 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
663 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
664 {
665 u32 src_offset = old_mem->start << PAGE_SHIFT;
666 u32 dst_offset = new_mem->start << PAGE_SHIFT;
667 u32 page_count = new_mem->num_pages;
668 int ret;
669
670 ret = RING_SPACE(chan, 3);
671 if (ret)
672 return ret;
673
674 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
675 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
676 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
677
678 page_count = new_mem->num_pages;
679 while (page_count) {
680 int line_count = (page_count > 2047) ? 2047 : page_count;
681
682 ret = RING_SPACE(chan, 11);
683 if (ret)
684 return ret;
685
686 BEGIN_RING(chan, NvSubM2MF,
687 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
688 OUT_RING (chan, src_offset);
689 OUT_RING (chan, dst_offset);
690 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
691 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
692 OUT_RING (chan, PAGE_SIZE); /* line_length */
693 OUT_RING (chan, line_count);
694 OUT_RING (chan, 0x00000101);
695 OUT_RING (chan, 0x00000000);
696 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
697 OUT_RING (chan, 0);
698
699 page_count -= line_count;
700 src_offset += (PAGE_SIZE * line_count);
701 dst_offset += (PAGE_SIZE * line_count);
702 }
703
704 return 0;
705 }
706
707 static int
708 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
709 bool no_wait_reserve, bool no_wait_gpu,
710 struct ttm_mem_reg *new_mem)
711 {
712 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
713 struct nouveau_bo *nvbo = nouveau_bo(bo);
714 struct nouveau_channel *chan;
715 int ret;
716
717 chan = nvbo->channel;
718 if (!chan) {
719 chan = dev_priv->channel;
720 mutex_lock_nested(&chan->mutex, NOUVEAU_KCHANNEL_MUTEX);
721 }
722
723 if (dev_priv->card_type < NV_50)
724 ret = nv04_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
725 else
726 if (dev_priv->card_type < NV_C0)
727 ret = nv50_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
728 else
729 ret = nvc0_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
730 if (ret == 0) {
731 ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict,
732 no_wait_reserve,
733 no_wait_gpu, new_mem);
734 }
735
736 if (chan == dev_priv->channel)
737 mutex_unlock(&chan->mutex);
738 return ret;
739 }
740
741 static int
742 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
743 bool no_wait_reserve, bool no_wait_gpu,
744 struct ttm_mem_reg *new_mem)
745 {
746 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
747 struct ttm_placement placement;
748 struct ttm_mem_reg tmp_mem;
749 int ret;
750
751 placement.fpfn = placement.lpfn = 0;
752 placement.num_placement = placement.num_busy_placement = 1;
753 placement.placement = placement.busy_placement = &placement_memtype;
754
755 tmp_mem = *new_mem;
756 tmp_mem.mm_node = NULL;
757 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
758 if (ret)
759 return ret;
760
761 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
762 if (ret)
763 goto out;
764
765 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem);
766 if (ret)
767 goto out;
768
769 ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem);
770 out:
771 ttm_bo_mem_put(bo, &tmp_mem);
772 return ret;
773 }
774
775 static int
776 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
777 bool no_wait_reserve, bool no_wait_gpu,
778 struct ttm_mem_reg *new_mem)
779 {
780 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
781 struct ttm_placement placement;
782 struct ttm_mem_reg tmp_mem;
783 int ret;
784
785 placement.fpfn = placement.lpfn = 0;
786 placement.num_placement = placement.num_busy_placement = 1;
787 placement.placement = placement.busy_placement = &placement_memtype;
788
789 tmp_mem = *new_mem;
790 tmp_mem.mm_node = NULL;
791 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
792 if (ret)
793 return ret;
794
795 ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem);
796 if (ret)
797 goto out;
798
799 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, new_mem);
800 if (ret)
801 goto out;
802
803 out:
804 ttm_bo_mem_put(bo, &tmp_mem);
805 return ret;
806 }
807
808 static int
809 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
810 struct nouveau_tile_reg **new_tile)
811 {
812 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
813 struct drm_device *dev = dev_priv->dev;
814 struct nouveau_bo *nvbo = nouveau_bo(bo);
815 uint64_t offset;
816
817 if (new_mem->mem_type != TTM_PL_VRAM) {
818 /* Nothing to do. */
819 *new_tile = NULL;
820 return 0;
821 }
822
823 offset = new_mem->start << PAGE_SHIFT;
824
825 if (dev_priv->chan_vm) {
826 nouveau_vm_map(&nvbo->vma, new_mem->mm_node);
827 } else if (dev_priv->card_type >= NV_10) {
828 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
829 nvbo->tile_mode,
830 nvbo->tile_flags);
831 }
832
833 return 0;
834 }
835
836 static void
837 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
838 struct nouveau_tile_reg *new_tile,
839 struct nouveau_tile_reg **old_tile)
840 {
841 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
842 struct drm_device *dev = dev_priv->dev;
843
844 if (dev_priv->card_type >= NV_10 &&
845 dev_priv->card_type < NV_50) {
846 nv10_mem_put_tile_region(dev, *old_tile, bo->sync_obj);
847 *old_tile = new_tile;
848 }
849 }
850
851 static int
852 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
853 bool no_wait_reserve, bool no_wait_gpu,
854 struct ttm_mem_reg *new_mem)
855 {
856 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
857 struct nouveau_bo *nvbo = nouveau_bo(bo);
858 struct ttm_mem_reg *old_mem = &bo->mem;
859 struct nouveau_tile_reg *new_tile = NULL;
860 int ret = 0;
861
862 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
863 if (ret)
864 return ret;
865
866 /* Fake bo copy. */
867 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
868 BUG_ON(bo->mem.mm_node != NULL);
869 bo->mem = *new_mem;
870 new_mem->mm_node = NULL;
871 goto out;
872 }
873
874 /* Software copy if the card isn't up and running yet. */
875 if (!dev_priv->channel) {
876 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
877 goto out;
878 }
879
880 /* Hardware assisted copy. */
881 if (new_mem->mem_type == TTM_PL_SYSTEM)
882 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
883 else if (old_mem->mem_type == TTM_PL_SYSTEM)
884 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
885 else
886 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
887
888 if (!ret)
889 goto out;
890
891 /* Fallback to software copy. */
892 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
893
894 out:
895 if (ret)
896 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
897 else
898 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
899
900 return ret;
901 }
902
903 static int
904 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
905 {
906 return 0;
907 }
908
909 static int
910 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
911 {
912 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
913 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
914 struct drm_device *dev = dev_priv->dev;
915 int ret;
916
917 mem->bus.addr = NULL;
918 mem->bus.offset = 0;
919 mem->bus.size = mem->num_pages << PAGE_SHIFT;
920 mem->bus.base = 0;
921 mem->bus.is_iomem = false;
922 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
923 return -EINVAL;
924 switch (mem->mem_type) {
925 case TTM_PL_SYSTEM:
926 /* System memory */
927 return 0;
928 case TTM_PL_TT:
929 #if __OS_HAS_AGP
930 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
931 mem->bus.offset = mem->start << PAGE_SHIFT;
932 mem->bus.base = dev_priv->gart_info.aper_base;
933 mem->bus.is_iomem = true;
934 }
935 #endif
936 break;
937 case TTM_PL_VRAM:
938 {
939 struct nouveau_vram *vram = mem->mm_node;
940 u8 page_shift;
941
942 if (!dev_priv->bar1_vm) {
943 mem->bus.offset = mem->start << PAGE_SHIFT;
944 mem->bus.base = pci_resource_start(dev->pdev, 1);
945 mem->bus.is_iomem = true;
946 break;
947 }
948
949 if (dev_priv->card_type == NV_C0)
950 page_shift = vram->page_shift;
951 else
952 page_shift = 12;
953
954 ret = nouveau_vm_get(dev_priv->bar1_vm, mem->bus.size,
955 page_shift, NV_MEM_ACCESS_RW,
956 &vram->bar_vma);
957 if (ret)
958 return ret;
959
960 nouveau_vm_map(&vram->bar_vma, vram);
961 if (ret) {
962 nouveau_vm_put(&vram->bar_vma);
963 return ret;
964 }
965
966 mem->bus.offset = vram->bar_vma.offset;
967 if (dev_priv->card_type == NV_50) /*XXX*/
968 mem->bus.offset -= 0x0020000000ULL;
969 mem->bus.base = pci_resource_start(dev->pdev, 1);
970 mem->bus.is_iomem = true;
971 }
972 break;
973 default:
974 return -EINVAL;
975 }
976 return 0;
977 }
978
979 static void
980 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
981 {
982 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
983 struct nouveau_vram *vram = mem->mm_node;
984
985 if (!dev_priv->bar1_vm || mem->mem_type != TTM_PL_VRAM)
986 return;
987
988 if (!vram->bar_vma.node)
989 return;
990
991 nouveau_vm_unmap(&vram->bar_vma);
992 nouveau_vm_put(&vram->bar_vma);
993 }
994
995 static int
996 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
997 {
998 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
999 struct nouveau_bo *nvbo = nouveau_bo(bo);
1000
1001 /* as long as the bo isn't in vram, and isn't tiled, we've got
1002 * nothing to do here.
1003 */
1004 if (bo->mem.mem_type != TTM_PL_VRAM) {
1005 if (dev_priv->card_type < NV_50 ||
1006 !nouveau_bo_tile_layout(nvbo))
1007 return 0;
1008 }
1009
1010 /* make sure bo is in mappable vram */
1011 if (bo->mem.start + bo->mem.num_pages < dev_priv->fb_mappable_pages)
1012 return 0;
1013
1014
1015 nvbo->placement.fpfn = 0;
1016 nvbo->placement.lpfn = dev_priv->fb_mappable_pages;
1017 nouveau_bo_placement_set(nvbo, TTM_PL_VRAM, 0);
1018 return nouveau_bo_validate(nvbo, false, true, false);
1019 }
1020
1021 void
1022 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
1023 {
1024 struct nouveau_fence *old_fence;
1025
1026 if (likely(fence))
1027 nouveau_fence_ref(fence);
1028
1029 spin_lock(&nvbo->bo.bdev->fence_lock);
1030 old_fence = nvbo->bo.sync_obj;
1031 nvbo->bo.sync_obj = fence;
1032 spin_unlock(&nvbo->bo.bdev->fence_lock);
1033
1034 nouveau_fence_unref(&old_fence);
1035 }
1036
1037 struct ttm_bo_driver nouveau_bo_driver = {
1038 .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry,
1039 .invalidate_caches = nouveau_bo_invalidate_caches,
1040 .init_mem_type = nouveau_bo_init_mem_type,
1041 .evict_flags = nouveau_bo_evict_flags,
1042 .move = nouveau_bo_move,
1043 .verify_access = nouveau_bo_verify_access,
1044 .sync_obj_signaled = __nouveau_fence_signalled,
1045 .sync_obj_wait = __nouveau_fence_wait,
1046 .sync_obj_flush = __nouveau_fence_flush,
1047 .sync_obj_unref = __nouveau_fence_unref,
1048 .sync_obj_ref = __nouveau_fence_ref,
1049 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1050 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1051 .io_mem_free = &nouveau_ttm_io_mem_free,
1052 };
1053
Linux kernel - Deliverables
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