2 * Copyright 2007 Dave Airlied
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
32 #include "nouveau_drm.h"
33 #include "nouveau_drv.h"
34 #include "nouveau_dma.h"
35 #include "nouveau_mm.h"
36 #include "nouveau_vm.h"
38 #include <linux/log2.h>
39 #include <linux/slab.h>
42 nouveau_bo_del_ttm(struct ttm_buffer_object
*bo
)
44 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
45 struct drm_device
*dev
= dev_priv
->dev
;
46 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
48 if (unlikely(nvbo
->gem
))
49 DRM_ERROR("bo %p still attached to GEM object\n", bo
);
51 nv10_mem_put_tile_region(dev
, nvbo
->tile
, NULL
);
52 nouveau_vm_put(&nvbo
->vma
);
57 nouveau_bo_fixup_align(struct nouveau_bo
*nvbo
, u32 flags
,
58 int *align
, int *size
, int *page_shift
)
60 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(nvbo
->bo
.bdev
);
62 if (dev_priv
->card_type
< NV_50
) {
63 if (nvbo
->tile_mode
) {
64 if (dev_priv
->chipset
>= 0x40) {
66 *size
= roundup(*size
, 64 * nvbo
->tile_mode
);
68 } else if (dev_priv
->chipset
>= 0x30) {
70 *size
= roundup(*size
, 64 * nvbo
->tile_mode
);
72 } else if (dev_priv
->chipset
>= 0x20) {
74 *size
= roundup(*size
, 64 * nvbo
->tile_mode
);
76 } else if (dev_priv
->chipset
>= 0x10) {
78 *size
= roundup(*size
, 32 * nvbo
->tile_mode
);
82 if (likely(dev_priv
->chan_vm
)) {
83 if (!(flags
& TTM_PL_FLAG_TT
) && *size
> 256 * 1024)
84 *page_shift
= dev_priv
->chan_vm
->lpg_shift
;
86 *page_shift
= dev_priv
->chan_vm
->spg_shift
;
91 *size
= roundup(*size
, (1 << *page_shift
));
92 *align
= max((1 << *page_shift
), *align
);
95 *size
= roundup(*size
, PAGE_SIZE
);
99 nouveau_bo_new(struct drm_device
*dev
, struct nouveau_channel
*chan
,
100 int size
, int align
, uint32_t flags
, uint32_t tile_mode
,
101 uint32_t tile_flags
, struct nouveau_bo
**pnvbo
)
103 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
104 struct nouveau_bo
*nvbo
;
105 int ret
= 0, page_shift
= 0;
107 nvbo
= kzalloc(sizeof(struct nouveau_bo
), GFP_KERNEL
);
110 INIT_LIST_HEAD(&nvbo
->head
);
111 INIT_LIST_HEAD(&nvbo
->entry
);
112 nvbo
->tile_mode
= tile_mode
;
113 nvbo
->tile_flags
= tile_flags
;
114 nvbo
->bo
.bdev
= &dev_priv
->ttm
.bdev
;
116 nouveau_bo_fixup_align(nvbo
, flags
, &align
, &size
, &page_shift
);
117 align
>>= PAGE_SHIFT
;
119 if (dev_priv
->chan_vm
) {
120 ret
= nouveau_vm_get(dev_priv
->chan_vm
, size
, page_shift
,
121 NV_MEM_ACCESS_RW
, &nvbo
->vma
);
128 nvbo
->bo
.mem
.num_pages
= size
>> PAGE_SHIFT
;
129 nouveau_bo_placement_set(nvbo
, flags
, 0);
131 nvbo
->channel
= chan
;
132 ret
= ttm_bo_init(&dev_priv
->ttm
.bdev
, &nvbo
->bo
, size
,
133 ttm_bo_type_device
, &nvbo
->placement
, align
, 0,
134 false, NULL
, size
, nouveau_bo_del_ttm
);
136 /* ttm will call nouveau_bo_del_ttm if it fails.. */
139 nvbo
->channel
= NULL
;
141 if (nvbo
->vma
.node
) {
142 if (nvbo
->bo
.mem
.mem_type
== TTM_PL_VRAM
)
143 nvbo
->bo
.offset
= nvbo
->vma
.offset
;
151 set_placement_list(uint32_t *pl
, unsigned *n
, uint32_t type
, uint32_t flags
)
155 if (type
& TTM_PL_FLAG_VRAM
)
156 pl
[(*n
)++] = TTM_PL_FLAG_VRAM
| flags
;
157 if (type
& TTM_PL_FLAG_TT
)
158 pl
[(*n
)++] = TTM_PL_FLAG_TT
| flags
;
159 if (type
& TTM_PL_FLAG_SYSTEM
)
160 pl
[(*n
)++] = TTM_PL_FLAG_SYSTEM
| flags
;
164 set_placement_range(struct nouveau_bo
*nvbo
, uint32_t type
)
166 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(nvbo
->bo
.bdev
);
167 int vram_pages
= dev_priv
->vram_size
>> PAGE_SHIFT
;
169 if (dev_priv
->card_type
== NV_10
&&
170 nvbo
->tile_mode
&& (type
& TTM_PL_FLAG_VRAM
) &&
171 nvbo
->bo
.mem
.num_pages
< vram_pages
/ 2) {
173 * Make sure that the color and depth buffers are handled
174 * by independent memory controller units. Up to a 9x
175 * speed up when alpha-blending and depth-test are enabled
178 if (nvbo
->tile_flags
& NOUVEAU_GEM_TILE_ZETA
) {
179 nvbo
->placement
.fpfn
= vram_pages
/ 2;
180 nvbo
->placement
.lpfn
= ~0;
182 nvbo
->placement
.fpfn
= 0;
183 nvbo
->placement
.lpfn
= vram_pages
/ 2;
189 nouveau_bo_placement_set(struct nouveau_bo
*nvbo
, uint32_t type
, uint32_t busy
)
191 struct ttm_placement
*pl
= &nvbo
->placement
;
192 uint32_t flags
= TTM_PL_MASK_CACHING
|
193 (nvbo
->pin_refcnt
? TTM_PL_FLAG_NO_EVICT
: 0);
195 pl
->placement
= nvbo
->placements
;
196 set_placement_list(nvbo
->placements
, &pl
->num_placement
,
199 pl
->busy_placement
= nvbo
->busy_placements
;
200 set_placement_list(nvbo
->busy_placements
, &pl
->num_busy_placement
,
203 set_placement_range(nvbo
, type
);
207 nouveau_bo_pin(struct nouveau_bo
*nvbo
, uint32_t memtype
)
209 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(nvbo
->bo
.bdev
);
210 struct ttm_buffer_object
*bo
= &nvbo
->bo
;
213 if (nvbo
->pin_refcnt
&& !(memtype
& (1 << bo
->mem
.mem_type
))) {
214 NV_ERROR(nouveau_bdev(bo
->bdev
)->dev
,
215 "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo
,
216 1 << bo
->mem
.mem_type
, memtype
);
220 if (nvbo
->pin_refcnt
++)
223 ret
= ttm_bo_reserve(bo
, false, false, false, 0);
227 nouveau_bo_placement_set(nvbo
, memtype
, 0);
229 ret
= nouveau_bo_validate(nvbo
, false, false, false);
231 switch (bo
->mem
.mem_type
) {
233 dev_priv
->fb_aper_free
-= bo
->mem
.size
;
236 dev_priv
->gart_info
.aper_free
-= bo
->mem
.size
;
242 ttm_bo_unreserve(bo
);
250 nouveau_bo_unpin(struct nouveau_bo
*nvbo
)
252 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(nvbo
->bo
.bdev
);
253 struct ttm_buffer_object
*bo
= &nvbo
->bo
;
256 if (--nvbo
->pin_refcnt
)
259 ret
= ttm_bo_reserve(bo
, false, false, false, 0);
263 nouveau_bo_placement_set(nvbo
, bo
->mem
.placement
, 0);
265 ret
= nouveau_bo_validate(nvbo
, false, false, false);
267 switch (bo
->mem
.mem_type
) {
269 dev_priv
->fb_aper_free
+= bo
->mem
.size
;
272 dev_priv
->gart_info
.aper_free
+= bo
->mem
.size
;
279 ttm_bo_unreserve(bo
);
284 nouveau_bo_map(struct nouveau_bo
*nvbo
)
288 ret
= ttm_bo_reserve(&nvbo
->bo
, false, false, false, 0);
292 ret
= ttm_bo_kmap(&nvbo
->bo
, 0, nvbo
->bo
.mem
.num_pages
, &nvbo
->kmap
);
293 ttm_bo_unreserve(&nvbo
->bo
);
298 nouveau_bo_unmap(struct nouveau_bo
*nvbo
)
301 ttm_bo_kunmap(&nvbo
->kmap
);
305 nouveau_bo_validate(struct nouveau_bo
*nvbo
, bool interruptible
,
306 bool no_wait_reserve
, bool no_wait_gpu
)
310 ret
= ttm_bo_validate(&nvbo
->bo
, &nvbo
->placement
, interruptible
,
311 no_wait_reserve
, no_wait_gpu
);
315 if (nvbo
->vma
.node
) {
316 if (nvbo
->bo
.mem
.mem_type
== TTM_PL_VRAM
)
317 nvbo
->bo
.offset
= nvbo
->vma
.offset
;
324 nouveau_bo_rd16(struct nouveau_bo
*nvbo
, unsigned index
)
327 u16
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
330 return ioread16_native((void __force __iomem
*)mem
);
336 nouveau_bo_wr16(struct nouveau_bo
*nvbo
, unsigned index
, u16 val
)
339 u16
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
342 iowrite16_native(val
, (void __force __iomem
*)mem
);
348 nouveau_bo_rd32(struct nouveau_bo
*nvbo
, unsigned index
)
351 u32
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
354 return ioread32_native((void __force __iomem
*)mem
);
360 nouveau_bo_wr32(struct nouveau_bo
*nvbo
, unsigned index
, u32 val
)
363 u32
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
366 iowrite32_native(val
, (void __force __iomem
*)mem
);
371 static struct ttm_backend
*
372 nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device
*bdev
)
374 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bdev
);
375 struct drm_device
*dev
= dev_priv
->dev
;
377 switch (dev_priv
->gart_info
.type
) {
379 case NOUVEAU_GART_AGP
:
380 return ttm_agp_backend_init(bdev
, dev
->agp
->bridge
);
382 case NOUVEAU_GART_PDMA
:
383 case NOUVEAU_GART_HW
:
384 return nouveau_sgdma_init_ttm(dev
);
386 NV_ERROR(dev
, "Unknown GART type %d\n",
387 dev_priv
->gart_info
.type
);
395 nouveau_bo_invalidate_caches(struct ttm_bo_device
*bdev
, uint32_t flags
)
397 /* We'll do this from user space. */
402 nouveau_bo_init_mem_type(struct ttm_bo_device
*bdev
, uint32_t type
,
403 struct ttm_mem_type_manager
*man
)
405 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bdev
);
406 struct drm_device
*dev
= dev_priv
->dev
;
410 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
;
411 man
->available_caching
= TTM_PL_MASK_CACHING
;
412 man
->default_caching
= TTM_PL_FLAG_CACHED
;
415 if (dev_priv
->card_type
>= NV_50
) {
416 man
->func
= &nouveau_vram_manager
;
417 man
->io_reserve_fastpath
= false;
418 man
->use_io_reserve_lru
= true;
420 man
->func
= &ttm_bo_manager_func
;
422 man
->flags
= TTM_MEMTYPE_FLAG_FIXED
|
423 TTM_MEMTYPE_FLAG_MAPPABLE
;
424 man
->available_caching
= TTM_PL_FLAG_UNCACHED
|
426 man
->default_caching
= TTM_PL_FLAG_WC
;
429 man
->func
= &ttm_bo_manager_func
;
430 switch (dev_priv
->gart_info
.type
) {
431 case NOUVEAU_GART_AGP
:
432 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
;
433 man
->available_caching
= TTM_PL_FLAG_UNCACHED
|
435 man
->default_caching
= TTM_PL_FLAG_WC
;
437 case NOUVEAU_GART_PDMA
:
438 case NOUVEAU_GART_HW
:
439 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
|
440 TTM_MEMTYPE_FLAG_CMA
;
441 man
->available_caching
= TTM_PL_MASK_CACHING
;
442 man
->default_caching
= TTM_PL_FLAG_CACHED
;
443 man
->gpu_offset
= dev_priv
->gart_info
.aper_base
;
446 NV_ERROR(dev
, "Unknown GART type: %d\n",
447 dev_priv
->gart_info
.type
);
452 NV_ERROR(dev
, "Unsupported memory type %u\n", (unsigned)type
);
459 nouveau_bo_evict_flags(struct ttm_buffer_object
*bo
, struct ttm_placement
*pl
)
461 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
463 switch (bo
->mem
.mem_type
) {
465 nouveau_bo_placement_set(nvbo
, TTM_PL_FLAG_TT
,
469 nouveau_bo_placement_set(nvbo
, TTM_PL_FLAG_SYSTEM
, 0);
473 *pl
= nvbo
->placement
;
477 /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
478 * TTM_PL_{VRAM,TT} directly.
482 nouveau_bo_move_accel_cleanup(struct nouveau_channel
*chan
,
483 struct nouveau_bo
*nvbo
, bool evict
,
484 bool no_wait_reserve
, bool no_wait_gpu
,
485 struct ttm_mem_reg
*new_mem
)
487 struct nouveau_fence
*fence
= NULL
;
490 ret
= nouveau_fence_new(chan
, &fence
, true);
494 ret
= ttm_bo_move_accel_cleanup(&nvbo
->bo
, fence
, NULL
, evict
,
495 no_wait_reserve
, no_wait_gpu
, new_mem
);
496 nouveau_fence_unref(&fence
);
501 nvc0_bo_move_m2mf(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
502 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
504 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
505 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
506 u32 page_count
= new_mem
->num_pages
;
507 u64 src_offset
, dst_offset
;
510 src_offset
= old_mem
->start
<< PAGE_SHIFT
;
511 if (old_mem
->mem_type
== TTM_PL_VRAM
)
512 src_offset
= nvbo
->vma
.offset
;
514 src_offset
+= dev_priv
->gart_info
.aper_base
;
516 dst_offset
= new_mem
->start
<< PAGE_SHIFT
;
517 if (new_mem
->mem_type
== TTM_PL_VRAM
)
518 dst_offset
= nvbo
->vma
.offset
;
520 dst_offset
+= dev_priv
->gart_info
.aper_base
;
522 page_count
= new_mem
->num_pages
;
524 int line_count
= (page_count
> 2047) ? 2047 : page_count
;
526 ret
= RING_SPACE(chan
, 12);
530 BEGIN_NVC0(chan
, 2, NvSubM2MF
, 0x0238, 2);
531 OUT_RING (chan
, upper_32_bits(dst_offset
));
532 OUT_RING (chan
, lower_32_bits(dst_offset
));
533 BEGIN_NVC0(chan
, 2, NvSubM2MF
, 0x030c, 6);
534 OUT_RING (chan
, upper_32_bits(src_offset
));
535 OUT_RING (chan
, lower_32_bits(src_offset
));
536 OUT_RING (chan
, PAGE_SIZE
); /* src_pitch */
537 OUT_RING (chan
, PAGE_SIZE
); /* dst_pitch */
538 OUT_RING (chan
, PAGE_SIZE
); /* line_length */
539 OUT_RING (chan
, line_count
);
540 BEGIN_NVC0(chan
, 2, NvSubM2MF
, 0x0300, 1);
541 OUT_RING (chan
, 0x00100110);
543 page_count
-= line_count
;
544 src_offset
+= (PAGE_SIZE
* line_count
);
545 dst_offset
+= (PAGE_SIZE
* line_count
);
552 nv50_bo_move_m2mf(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
553 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
555 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
556 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
557 u64 length
= (new_mem
->num_pages
<< PAGE_SHIFT
);
558 u64 src_offset
, dst_offset
;
561 src_offset
= old_mem
->start
<< PAGE_SHIFT
;
562 if (old_mem
->mem_type
== TTM_PL_VRAM
)
563 src_offset
= nvbo
->vma
.offset
;
565 src_offset
+= dev_priv
->gart_info
.aper_base
;
567 dst_offset
= new_mem
->start
<< PAGE_SHIFT
;
568 if (new_mem
->mem_type
== TTM_PL_VRAM
)
569 dst_offset
= nvbo
->vma
.offset
;
571 dst_offset
+= dev_priv
->gart_info
.aper_base
;
574 u32 amount
, stride
, height
;
576 amount
= min(length
, (u64
)(4 * 1024 * 1024));
578 height
= amount
/ stride
;
580 if (new_mem
->mem_type
== TTM_PL_VRAM
&&
581 nouveau_bo_tile_layout(nvbo
)) {
582 ret
= RING_SPACE(chan
, 8);
586 BEGIN_RING(chan
, NvSubM2MF
, 0x0200, 7);
589 OUT_RING (chan
, stride
);
590 OUT_RING (chan
, height
);
595 ret
= RING_SPACE(chan
, 2);
599 BEGIN_RING(chan
, NvSubM2MF
, 0x0200, 1);
602 if (old_mem
->mem_type
== TTM_PL_VRAM
&&
603 nouveau_bo_tile_layout(nvbo
)) {
604 ret
= RING_SPACE(chan
, 8);
608 BEGIN_RING(chan
, NvSubM2MF
, 0x021c, 7);
611 OUT_RING (chan
, stride
);
612 OUT_RING (chan
, height
);
617 ret
= RING_SPACE(chan
, 2);
621 BEGIN_RING(chan
, NvSubM2MF
, 0x021c, 1);
625 ret
= RING_SPACE(chan
, 14);
629 BEGIN_RING(chan
, NvSubM2MF
, 0x0238, 2);
630 OUT_RING (chan
, upper_32_bits(src_offset
));
631 OUT_RING (chan
, upper_32_bits(dst_offset
));
632 BEGIN_RING(chan
, NvSubM2MF
, 0x030c, 8);
633 OUT_RING (chan
, lower_32_bits(src_offset
));
634 OUT_RING (chan
, lower_32_bits(dst_offset
));
635 OUT_RING (chan
, stride
);
636 OUT_RING (chan
, stride
);
637 OUT_RING (chan
, stride
);
638 OUT_RING (chan
, height
);
639 OUT_RING (chan
, 0x00000101);
640 OUT_RING (chan
, 0x00000000);
641 BEGIN_RING(chan
, NvSubM2MF
, NV_MEMORY_TO_MEMORY_FORMAT_NOP
, 1);
645 src_offset
+= amount
;
646 dst_offset
+= amount
;
652 static inline uint32_t
653 nouveau_bo_mem_ctxdma(struct ttm_buffer_object
*bo
,
654 struct nouveau_channel
*chan
, struct ttm_mem_reg
*mem
)
656 if (mem
->mem_type
== TTM_PL_TT
)
657 return chan
->gart_handle
;
658 return chan
->vram_handle
;
662 nv04_bo_move_m2mf(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
663 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
665 u32 src_offset
= old_mem
->start
<< PAGE_SHIFT
;
666 u32 dst_offset
= new_mem
->start
<< PAGE_SHIFT
;
667 u32 page_count
= new_mem
->num_pages
;
670 ret
= RING_SPACE(chan
, 3);
674 BEGIN_RING(chan
, NvSubM2MF
, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE
, 2);
675 OUT_RING (chan
, nouveau_bo_mem_ctxdma(bo
, chan
, old_mem
));
676 OUT_RING (chan
, nouveau_bo_mem_ctxdma(bo
, chan
, new_mem
));
678 page_count
= new_mem
->num_pages
;
680 int line_count
= (page_count
> 2047) ? 2047 : page_count
;
682 ret
= RING_SPACE(chan
, 11);
686 BEGIN_RING(chan
, NvSubM2MF
,
687 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN
, 8);
688 OUT_RING (chan
, src_offset
);
689 OUT_RING (chan
, dst_offset
);
690 OUT_RING (chan
, PAGE_SIZE
); /* src_pitch */
691 OUT_RING (chan
, PAGE_SIZE
); /* dst_pitch */
692 OUT_RING (chan
, PAGE_SIZE
); /* line_length */
693 OUT_RING (chan
, line_count
);
694 OUT_RING (chan
, 0x00000101);
695 OUT_RING (chan
, 0x00000000);
696 BEGIN_RING(chan
, NvSubM2MF
, NV_MEMORY_TO_MEMORY_FORMAT_NOP
, 1);
699 page_count
-= line_count
;
700 src_offset
+= (PAGE_SIZE
* line_count
);
701 dst_offset
+= (PAGE_SIZE
* line_count
);
708 nouveau_bo_move_m2mf(struct ttm_buffer_object
*bo
, int evict
, bool intr
,
709 bool no_wait_reserve
, bool no_wait_gpu
,
710 struct ttm_mem_reg
*new_mem
)
712 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
713 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
714 struct nouveau_channel
*chan
;
717 chan
= nvbo
->channel
;
719 chan
= dev_priv
->channel
;
720 mutex_lock_nested(&chan
->mutex
, NOUVEAU_KCHANNEL_MUTEX
);
723 if (dev_priv
->card_type
< NV_50
)
724 ret
= nv04_bo_move_m2mf(chan
, bo
, &bo
->mem
, new_mem
);
726 if (dev_priv
->card_type
< NV_C0
)
727 ret
= nv50_bo_move_m2mf(chan
, bo
, &bo
->mem
, new_mem
);
729 ret
= nvc0_bo_move_m2mf(chan
, bo
, &bo
->mem
, new_mem
);
731 ret
= nouveau_bo_move_accel_cleanup(chan
, nvbo
, evict
,
733 no_wait_gpu
, new_mem
);
736 if (chan
== dev_priv
->channel
)
737 mutex_unlock(&chan
->mutex
);
742 nouveau_bo_move_flipd(struct ttm_buffer_object
*bo
, bool evict
, bool intr
,
743 bool no_wait_reserve
, bool no_wait_gpu
,
744 struct ttm_mem_reg
*new_mem
)
746 u32 placement_memtype
= TTM_PL_FLAG_TT
| TTM_PL_MASK_CACHING
;
747 struct ttm_placement placement
;
748 struct ttm_mem_reg tmp_mem
;
751 placement
.fpfn
= placement
.lpfn
= 0;
752 placement
.num_placement
= placement
.num_busy_placement
= 1;
753 placement
.placement
= placement
.busy_placement
= &placement_memtype
;
756 tmp_mem
.mm_node
= NULL
;
757 ret
= ttm_bo_mem_space(bo
, &placement
, &tmp_mem
, intr
, no_wait_reserve
, no_wait_gpu
);
761 ret
= ttm_tt_bind(bo
->ttm
, &tmp_mem
);
765 ret
= nouveau_bo_move_m2mf(bo
, true, intr
, no_wait_reserve
, no_wait_gpu
, &tmp_mem
);
769 ret
= ttm_bo_move_ttm(bo
, true, no_wait_reserve
, no_wait_gpu
, new_mem
);
771 ttm_bo_mem_put(bo
, &tmp_mem
);
776 nouveau_bo_move_flips(struct ttm_buffer_object
*bo
, bool evict
, bool intr
,
777 bool no_wait_reserve
, bool no_wait_gpu
,
778 struct ttm_mem_reg
*new_mem
)
780 u32 placement_memtype
= TTM_PL_FLAG_TT
| TTM_PL_MASK_CACHING
;
781 struct ttm_placement placement
;
782 struct ttm_mem_reg tmp_mem
;
785 placement
.fpfn
= placement
.lpfn
= 0;
786 placement
.num_placement
= placement
.num_busy_placement
= 1;
787 placement
.placement
= placement
.busy_placement
= &placement_memtype
;
790 tmp_mem
.mm_node
= NULL
;
791 ret
= ttm_bo_mem_space(bo
, &placement
, &tmp_mem
, intr
, no_wait_reserve
, no_wait_gpu
);
795 ret
= ttm_bo_move_ttm(bo
, true, no_wait_reserve
, no_wait_gpu
, &tmp_mem
);
799 ret
= nouveau_bo_move_m2mf(bo
, true, intr
, no_wait_reserve
, no_wait_gpu
, new_mem
);
804 ttm_bo_mem_put(bo
, &tmp_mem
);
809 nouveau_bo_move_ntfy(struct ttm_buffer_object
*bo
, struct ttm_mem_reg
*new_mem
)
811 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
812 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
814 if (dev_priv
->card_type
< NV_50
|| nvbo
->no_vm
)
817 switch (new_mem
->mem_type
) {
819 nouveau_vm_map(&nvbo
->vma
, new_mem
->mm_node
);
828 nouveau_bo_vm_bind(struct ttm_buffer_object
*bo
, struct ttm_mem_reg
*new_mem
,
829 struct nouveau_tile_reg
**new_tile
)
831 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
832 struct drm_device
*dev
= dev_priv
->dev
;
833 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
834 u64 offset
= new_mem
->start
<< PAGE_SHIFT
;
837 if (new_mem
->mem_type
!= TTM_PL_VRAM
)
840 if (dev_priv
->card_type
>= NV_10
) {
841 *new_tile
= nv10_mem_set_tiling(dev
, offset
, new_mem
->size
,
850 nouveau_bo_vm_cleanup(struct ttm_buffer_object
*bo
,
851 struct nouveau_tile_reg
*new_tile
,
852 struct nouveau_tile_reg
**old_tile
)
854 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
855 struct drm_device
*dev
= dev_priv
->dev
;
857 nv10_mem_put_tile_region(dev
, *old_tile
, bo
->sync_obj
);
858 *old_tile
= new_tile
;
862 nouveau_bo_move(struct ttm_buffer_object
*bo
, bool evict
, bool intr
,
863 bool no_wait_reserve
, bool no_wait_gpu
,
864 struct ttm_mem_reg
*new_mem
)
866 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
867 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
868 struct ttm_mem_reg
*old_mem
= &bo
->mem
;
869 struct nouveau_tile_reg
*new_tile
= NULL
;
872 if (dev_priv
->card_type
< NV_50
) {
873 ret
= nouveau_bo_vm_bind(bo
, new_mem
, &new_tile
);
879 if (old_mem
->mem_type
== TTM_PL_SYSTEM
&& !bo
->ttm
) {
880 BUG_ON(bo
->mem
.mm_node
!= NULL
);
882 new_mem
->mm_node
= NULL
;
886 /* Software copy if the card isn't up and running yet. */
887 if (!dev_priv
->channel
) {
888 ret
= ttm_bo_move_memcpy(bo
, evict
, no_wait_reserve
, no_wait_gpu
, new_mem
);
892 /* Hardware assisted copy. */
893 if (new_mem
->mem_type
== TTM_PL_SYSTEM
)
894 ret
= nouveau_bo_move_flipd(bo
, evict
, intr
, no_wait_reserve
, no_wait_gpu
, new_mem
);
895 else if (old_mem
->mem_type
== TTM_PL_SYSTEM
)
896 ret
= nouveau_bo_move_flips(bo
, evict
, intr
, no_wait_reserve
, no_wait_gpu
, new_mem
);
898 ret
= nouveau_bo_move_m2mf(bo
, evict
, intr
, no_wait_reserve
, no_wait_gpu
, new_mem
);
903 /* Fallback to software copy. */
904 ret
= ttm_bo_move_memcpy(bo
, evict
, no_wait_reserve
, no_wait_gpu
, new_mem
);
907 if (dev_priv
->card_type
< NV_50
) {
909 nouveau_bo_vm_cleanup(bo
, NULL
, &new_tile
);
911 nouveau_bo_vm_cleanup(bo
, new_tile
, &nvbo
->tile
);
918 nouveau_bo_verify_access(struct ttm_buffer_object
*bo
, struct file
*filp
)
924 nouveau_ttm_io_mem_reserve(struct ttm_bo_device
*bdev
, struct ttm_mem_reg
*mem
)
926 struct ttm_mem_type_manager
*man
= &bdev
->man
[mem
->mem_type
];
927 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bdev
);
928 struct drm_device
*dev
= dev_priv
->dev
;
931 mem
->bus
.addr
= NULL
;
933 mem
->bus
.size
= mem
->num_pages
<< PAGE_SHIFT
;
935 mem
->bus
.is_iomem
= false;
936 if (!(man
->flags
& TTM_MEMTYPE_FLAG_MAPPABLE
))
938 switch (mem
->mem_type
) {
944 if (dev_priv
->gart_info
.type
== NOUVEAU_GART_AGP
) {
945 mem
->bus
.offset
= mem
->start
<< PAGE_SHIFT
;
946 mem
->bus
.base
= dev_priv
->gart_info
.aper_base
;
947 mem
->bus
.is_iomem
= true;
953 struct nouveau_vram
*vram
= mem
->mm_node
;
956 if (!dev_priv
->bar1_vm
) {
957 mem
->bus
.offset
= mem
->start
<< PAGE_SHIFT
;
958 mem
->bus
.base
= pci_resource_start(dev
->pdev
, 1);
959 mem
->bus
.is_iomem
= true;
963 if (dev_priv
->card_type
== NV_C0
)
964 page_shift
= vram
->page_shift
;
968 ret
= nouveau_vm_get(dev_priv
->bar1_vm
, mem
->bus
.size
,
969 page_shift
, NV_MEM_ACCESS_RW
,
974 nouveau_vm_map(&vram
->bar_vma
, vram
);
976 nouveau_vm_put(&vram
->bar_vma
);
980 mem
->bus
.offset
= vram
->bar_vma
.offset
;
981 if (dev_priv
->card_type
== NV_50
) /*XXX*/
982 mem
->bus
.offset
-= 0x0020000000ULL
;
983 mem
->bus
.base
= pci_resource_start(dev
->pdev
, 1);
984 mem
->bus
.is_iomem
= true;
994 nouveau_ttm_io_mem_free(struct ttm_bo_device
*bdev
, struct ttm_mem_reg
*mem
)
996 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bdev
);
997 struct nouveau_vram
*vram
= mem
->mm_node
;
999 if (!dev_priv
->bar1_vm
|| mem
->mem_type
!= TTM_PL_VRAM
)
1002 if (!vram
->bar_vma
.node
)
1005 nouveau_vm_unmap(&vram
->bar_vma
);
1006 nouveau_vm_put(&vram
->bar_vma
);
1010 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object
*bo
)
1012 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
1013 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
1015 /* as long as the bo isn't in vram, and isn't tiled, we've got
1016 * nothing to do here.
1018 if (bo
->mem
.mem_type
!= TTM_PL_VRAM
) {
1019 if (dev_priv
->card_type
< NV_50
||
1020 !nouveau_bo_tile_layout(nvbo
))
1024 /* make sure bo is in mappable vram */
1025 if (bo
->mem
.start
+ bo
->mem
.num_pages
< dev_priv
->fb_mappable_pages
)
1029 nvbo
->placement
.fpfn
= 0;
1030 nvbo
->placement
.lpfn
= dev_priv
->fb_mappable_pages
;
1031 nouveau_bo_placement_set(nvbo
, TTM_PL_VRAM
, 0);
1032 return nouveau_bo_validate(nvbo
, false, true, false);
1036 nouveau_bo_fence(struct nouveau_bo
*nvbo
, struct nouveau_fence
*fence
)
1038 struct nouveau_fence
*old_fence
;
1041 nouveau_fence_ref(fence
);
1043 spin_lock(&nvbo
->bo
.bdev
->fence_lock
);
1044 old_fence
= nvbo
->bo
.sync_obj
;
1045 nvbo
->bo
.sync_obj
= fence
;
1046 spin_unlock(&nvbo
->bo
.bdev
->fence_lock
);
1048 nouveau_fence_unref(&old_fence
);
1051 struct ttm_bo_driver nouveau_bo_driver
= {
1052 .create_ttm_backend_entry
= nouveau_bo_create_ttm_backend_entry
,
1053 .invalidate_caches
= nouveau_bo_invalidate_caches
,
1054 .init_mem_type
= nouveau_bo_init_mem_type
,
1055 .evict_flags
= nouveau_bo_evict_flags
,
1056 .move_notify
= nouveau_bo_move_ntfy
,
1057 .move
= nouveau_bo_move
,
1058 .verify_access
= nouveau_bo_verify_access
,
1059 .sync_obj_signaled
= __nouveau_fence_signalled
,
1060 .sync_obj_wait
= __nouveau_fence_wait
,
1061 .sync_obj_flush
= __nouveau_fence_flush
,
1062 .sync_obj_unref
= __nouveau_fence_unref
,
1063 .sync_obj_ref
= __nouveau_fence_ref
,
1064 .fault_reserve_notify
= &nouveau_ttm_fault_reserve_notify
,
1065 .io_mem_reserve
= &nouveau_ttm_io_mem_reserve
,
1066 .io_mem_free
= &nouveau_ttm_io_mem_free
,