2 * Copyright 2007 Dave Airlied
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
32 #include "nouveau_drm.h"
33 #include "nouveau_drv.h"
34 #include "nouveau_dma.h"
36 #include <linux/log2.h>
37 #include <linux/slab.h>
40 nouveau_bo_del_ttm(struct ttm_buffer_object
*bo
)
42 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
43 struct drm_device
*dev
= dev_priv
->dev
;
44 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
46 if (unlikely(nvbo
->gem
))
47 DRM_ERROR("bo %p still attached to GEM object\n", bo
);
50 nv10_mem_expire_tiling(dev
, nvbo
->tile
, NULL
);
56 nouveau_bo_fixup_align(struct drm_device
*dev
,
57 uint32_t tile_mode
, uint32_t tile_flags
,
58 int *align
, int *size
)
60 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
63 * Some of the tile_flags have a periodic structure of N*4096 bytes,
64 * align to to that as well as the page size. Align the size to the
65 * appropriate boundaries. This does imply that sizes are rounded up
66 * 3-7 pages, so be aware of this and do not waste memory by allocating
69 if (dev_priv
->card_type
== NV_50
) {
70 uint32_t block_size
= dev_priv
->vram_size
>> 15;
78 if (is_power_of_2(block_size
)) {
79 for (i
= 1; i
< 10; i
++) {
80 *align
= 12 * i
* block_size
;
81 if (!(*align
% 65536))
85 for (i
= 1; i
< 10; i
++) {
86 *align
= 8 * i
* block_size
;
87 if (!(*align
% 65536))
91 *size
= roundup(*size
, *align
);
99 if (dev_priv
->chipset
>= 0x40) {
101 *size
= roundup(*size
, 64 * tile_mode
);
103 } else if (dev_priv
->chipset
>= 0x30) {
105 *size
= roundup(*size
, 64 * tile_mode
);
107 } else if (dev_priv
->chipset
>= 0x20) {
109 *size
= roundup(*size
, 64 * tile_mode
);
111 } else if (dev_priv
->chipset
>= 0x10) {
113 *size
= roundup(*size
, 32 * tile_mode
);
118 /* ALIGN works only on powers of two. */
119 *size
= roundup(*size
, PAGE_SIZE
);
121 if (dev_priv
->card_type
== NV_50
) {
122 *size
= roundup(*size
, 65536);
123 *align
= max(65536, *align
);
128 nouveau_bo_new(struct drm_device
*dev
, struct nouveau_channel
*chan
,
129 int size
, int align
, uint32_t flags
, uint32_t tile_mode
,
130 uint32_t tile_flags
, bool no_vm
, bool mappable
,
131 struct nouveau_bo
**pnvbo
)
133 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
134 struct nouveau_bo
*nvbo
;
137 nvbo
= kzalloc(sizeof(struct nouveau_bo
), GFP_KERNEL
);
140 INIT_LIST_HEAD(&nvbo
->head
);
141 INIT_LIST_HEAD(&nvbo
->entry
);
142 nvbo
->mappable
= mappable
;
144 nvbo
->tile_mode
= tile_mode
;
145 nvbo
->tile_flags
= tile_flags
;
147 nouveau_bo_fixup_align(dev
, tile_mode
, tile_flags
, &align
, &size
);
148 align
>>= PAGE_SHIFT
;
150 nouveau_bo_placement_set(nvbo
, flags
, 0);
152 nvbo
->channel
= chan
;
153 ret
= ttm_bo_init(&dev_priv
->ttm
.bdev
, &nvbo
->bo
, size
,
154 ttm_bo_type_device
, &nvbo
->placement
, align
, 0,
155 false, NULL
, size
, nouveau_bo_del_ttm
);
157 /* ttm will call nouveau_bo_del_ttm if it fails.. */
160 nvbo
->channel
= NULL
;
167 set_placement_list(uint32_t *pl
, unsigned *n
, uint32_t type
, uint32_t flags
)
171 if (type
& TTM_PL_FLAG_VRAM
)
172 pl
[(*n
)++] = TTM_PL_FLAG_VRAM
| flags
;
173 if (type
& TTM_PL_FLAG_TT
)
174 pl
[(*n
)++] = TTM_PL_FLAG_TT
| flags
;
175 if (type
& TTM_PL_FLAG_SYSTEM
)
176 pl
[(*n
)++] = TTM_PL_FLAG_SYSTEM
| flags
;
180 nouveau_bo_placement_set(struct nouveau_bo
*nvbo
, uint32_t type
, uint32_t busy
)
182 struct ttm_placement
*pl
= &nvbo
->placement
;
183 uint32_t flags
= TTM_PL_MASK_CACHING
|
184 (nvbo
->pin_refcnt
? TTM_PL_FLAG_NO_EVICT
: 0);
186 pl
->placement
= nvbo
->placements
;
187 set_placement_list(nvbo
->placements
, &pl
->num_placement
,
190 pl
->busy_placement
= nvbo
->busy_placements
;
191 set_placement_list(nvbo
->busy_placements
, &pl
->num_busy_placement
,
196 nouveau_bo_pin(struct nouveau_bo
*nvbo
, uint32_t memtype
)
198 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(nvbo
->bo
.bdev
);
199 struct ttm_buffer_object
*bo
= &nvbo
->bo
;
202 if (nvbo
->pin_refcnt
&& !(memtype
& (1 << bo
->mem
.mem_type
))) {
203 NV_ERROR(nouveau_bdev(bo
->bdev
)->dev
,
204 "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo
,
205 1 << bo
->mem
.mem_type
, memtype
);
209 if (nvbo
->pin_refcnt
++)
212 ret
= ttm_bo_reserve(bo
, false, false, false, 0);
216 nouveau_bo_placement_set(nvbo
, memtype
, 0);
218 ret
= ttm_bo_validate(bo
, &nvbo
->placement
, false, false, false);
220 switch (bo
->mem
.mem_type
) {
222 dev_priv
->fb_aper_free
-= bo
->mem
.size
;
225 dev_priv
->gart_info
.aper_free
-= bo
->mem
.size
;
231 ttm_bo_unreserve(bo
);
239 nouveau_bo_unpin(struct nouveau_bo
*nvbo
)
241 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(nvbo
->bo
.bdev
);
242 struct ttm_buffer_object
*bo
= &nvbo
->bo
;
245 if (--nvbo
->pin_refcnt
)
248 ret
= ttm_bo_reserve(bo
, false, false, false, 0);
252 nouveau_bo_placement_set(nvbo
, bo
->mem
.placement
, 0);
254 ret
= ttm_bo_validate(bo
, &nvbo
->placement
, false, false, false);
256 switch (bo
->mem
.mem_type
) {
258 dev_priv
->fb_aper_free
+= bo
->mem
.size
;
261 dev_priv
->gart_info
.aper_free
+= bo
->mem
.size
;
268 ttm_bo_unreserve(bo
);
273 nouveau_bo_map(struct nouveau_bo
*nvbo
)
277 ret
= ttm_bo_reserve(&nvbo
->bo
, false, false, false, 0);
281 ret
= ttm_bo_kmap(&nvbo
->bo
, 0, nvbo
->bo
.mem
.num_pages
, &nvbo
->kmap
);
282 ttm_bo_unreserve(&nvbo
->bo
);
287 nouveau_bo_unmap(struct nouveau_bo
*nvbo
)
290 ttm_bo_kunmap(&nvbo
->kmap
);
294 nouveau_bo_rd16(struct nouveau_bo
*nvbo
, unsigned index
)
297 u16
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
300 return ioread16_native((void __force __iomem
*)mem
);
306 nouveau_bo_wr16(struct nouveau_bo
*nvbo
, unsigned index
, u16 val
)
309 u16
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
312 iowrite16_native(val
, (void __force __iomem
*)mem
);
318 nouveau_bo_rd32(struct nouveau_bo
*nvbo
, unsigned index
)
321 u32
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
324 return ioread32_native((void __force __iomem
*)mem
);
330 nouveau_bo_wr32(struct nouveau_bo
*nvbo
, unsigned index
, u32 val
)
333 u32
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
336 iowrite32_native(val
, (void __force __iomem
*)mem
);
341 static struct ttm_backend
*
342 nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device
*bdev
)
344 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bdev
);
345 struct drm_device
*dev
= dev_priv
->dev
;
347 switch (dev_priv
->gart_info
.type
) {
349 case NOUVEAU_GART_AGP
:
350 return ttm_agp_backend_init(bdev
, dev
->agp
->bridge
);
352 case NOUVEAU_GART_SGDMA
:
353 return nouveau_sgdma_init_ttm(dev
);
355 NV_ERROR(dev
, "Unknown GART type %d\n",
356 dev_priv
->gart_info
.type
);
364 nouveau_bo_invalidate_caches(struct ttm_bo_device
*bdev
, uint32_t flags
)
366 /* We'll do this from user space. */
371 nouveau_bo_init_mem_type(struct ttm_bo_device
*bdev
, uint32_t type
,
372 struct ttm_mem_type_manager
*man
)
374 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bdev
);
375 struct drm_device
*dev
= dev_priv
->dev
;
379 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
;
380 man
->available_caching
= TTM_PL_MASK_CACHING
;
381 man
->default_caching
= TTM_PL_FLAG_CACHED
;
384 man
->func
= &ttm_bo_manager_func
;
385 man
->flags
= TTM_MEMTYPE_FLAG_FIXED
|
386 TTM_MEMTYPE_FLAG_MAPPABLE
;
387 man
->available_caching
= TTM_PL_FLAG_UNCACHED
|
389 man
->default_caching
= TTM_PL_FLAG_WC
;
390 if (dev_priv
->card_type
== NV_50
)
391 man
->gpu_offset
= 0x40000000;
396 man
->func
= &ttm_bo_manager_func
;
397 switch (dev_priv
->gart_info
.type
) {
398 case NOUVEAU_GART_AGP
:
399 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
;
400 man
->available_caching
= TTM_PL_FLAG_UNCACHED
;
401 man
->default_caching
= TTM_PL_FLAG_UNCACHED
;
403 case NOUVEAU_GART_SGDMA
:
404 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
|
405 TTM_MEMTYPE_FLAG_CMA
;
406 man
->available_caching
= TTM_PL_MASK_CACHING
;
407 man
->default_caching
= TTM_PL_FLAG_CACHED
;
410 NV_ERROR(dev
, "Unknown GART type: %d\n",
411 dev_priv
->gart_info
.type
);
414 man
->gpu_offset
= dev_priv
->vm_gart_base
;
417 NV_ERROR(dev
, "Unsupported memory type %u\n", (unsigned)type
);
424 nouveau_bo_evict_flags(struct ttm_buffer_object
*bo
, struct ttm_placement
*pl
)
426 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
428 switch (bo
->mem
.mem_type
) {
430 nouveau_bo_placement_set(nvbo
, TTM_PL_FLAG_TT
,
434 nouveau_bo_placement_set(nvbo
, TTM_PL_FLAG_SYSTEM
, 0);
438 *pl
= nvbo
->placement
;
442 /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
443 * TTM_PL_{VRAM,TT} directly.
447 nouveau_bo_move_accel_cleanup(struct nouveau_channel
*chan
,
448 struct nouveau_bo
*nvbo
, bool evict
,
449 bool no_wait_reserve
, bool no_wait_gpu
,
450 struct ttm_mem_reg
*new_mem
)
452 struct nouveau_fence
*fence
= NULL
;
455 ret
= nouveau_fence_new(chan
, &fence
, true);
460 ret
= nouveau_fence_sync(fence
, nvbo
->channel
);
465 ret
= ttm_bo_move_accel_cleanup(&nvbo
->bo
, fence
, NULL
, evict
,
466 no_wait_reserve
, no_wait_gpu
, new_mem
);
468 nouveau_fence_unref((void *)&fence
);
472 static inline uint32_t
473 nouveau_bo_mem_ctxdma(struct ttm_buffer_object
*bo
,
474 struct nouveau_channel
*chan
, struct ttm_mem_reg
*mem
)
476 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
479 if (mem
->mem_type
== TTM_PL_TT
)
484 if (mem
->mem_type
== TTM_PL_TT
)
485 return chan
->gart_handle
;
486 return chan
->vram_handle
;
490 nv50_bo_move_m2mf(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
491 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
493 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
494 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
495 u64 length
= (new_mem
->num_pages
<< PAGE_SHIFT
);
496 u64 src_offset
, dst_offset
;
499 src_offset
= old_mem
->start
<< PAGE_SHIFT
;
500 dst_offset
= new_mem
->start
<< PAGE_SHIFT
;
502 if (old_mem
->mem_type
== TTM_PL_VRAM
)
503 src_offset
+= dev_priv
->vm_vram_base
;
505 src_offset
+= dev_priv
->vm_gart_base
;
507 if (new_mem
->mem_type
== TTM_PL_VRAM
)
508 dst_offset
+= dev_priv
->vm_vram_base
;
510 dst_offset
+= dev_priv
->vm_gart_base
;
513 ret
= RING_SPACE(chan
, 3);
517 BEGIN_RING(chan
, NvSubM2MF
, 0x0184, 2);
518 OUT_RING (chan
, nouveau_bo_mem_ctxdma(bo
, chan
, old_mem
));
519 OUT_RING (chan
, nouveau_bo_mem_ctxdma(bo
, chan
, new_mem
));
522 u32 amount
, stride
, height
;
524 amount
= min(length
, (u64
)(4 * 1024 * 1024));
526 height
= amount
/ stride
;
528 if (new_mem
->mem_type
== TTM_PL_VRAM
&& nvbo
->tile_flags
) {
529 ret
= RING_SPACE(chan
, 8);
533 BEGIN_RING(chan
, NvSubM2MF
, 0x0200, 7);
536 OUT_RING (chan
, stride
);
537 OUT_RING (chan
, height
);
542 ret
= RING_SPACE(chan
, 2);
546 BEGIN_RING(chan
, NvSubM2MF
, 0x0200, 1);
549 if (old_mem
->mem_type
== TTM_PL_VRAM
&& nvbo
->tile_flags
) {
550 ret
= RING_SPACE(chan
, 8);
554 BEGIN_RING(chan
, NvSubM2MF
, 0x021c, 7);
557 OUT_RING (chan
, stride
);
558 OUT_RING (chan
, height
);
563 ret
= RING_SPACE(chan
, 2);
567 BEGIN_RING(chan
, NvSubM2MF
, 0x021c, 1);
571 ret
= RING_SPACE(chan
, 14);
575 BEGIN_RING(chan
, NvSubM2MF
, 0x0238, 2);
576 OUT_RING (chan
, upper_32_bits(src_offset
));
577 OUT_RING (chan
, upper_32_bits(dst_offset
));
578 BEGIN_RING(chan
, NvSubM2MF
, 0x030c, 8);
579 OUT_RING (chan
, lower_32_bits(src_offset
));
580 OUT_RING (chan
, lower_32_bits(dst_offset
));
581 OUT_RING (chan
, stride
);
582 OUT_RING (chan
, stride
);
583 OUT_RING (chan
, stride
);
584 OUT_RING (chan
, height
);
585 OUT_RING (chan
, 0x00000101);
586 OUT_RING (chan
, 0x00000000);
587 BEGIN_RING(chan
, NvSubM2MF
, NV_MEMORY_TO_MEMORY_FORMAT_NOP
, 1);
591 src_offset
+= amount
;
592 dst_offset
+= amount
;
599 nv04_bo_move_m2mf(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
600 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
602 u32 src_offset
= old_mem
->start
<< PAGE_SHIFT
;
603 u32 dst_offset
= new_mem
->start
<< PAGE_SHIFT
;
604 u32 page_count
= new_mem
->num_pages
;
607 ret
= RING_SPACE(chan
, 3);
611 BEGIN_RING(chan
, NvSubM2MF
, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE
, 2);
612 OUT_RING (chan
, nouveau_bo_mem_ctxdma(bo
, chan
, old_mem
));
613 OUT_RING (chan
, nouveau_bo_mem_ctxdma(bo
, chan
, new_mem
));
615 page_count
= new_mem
->num_pages
;
617 int line_count
= (page_count
> 2047) ? 2047 : page_count
;
619 ret
= RING_SPACE(chan
, 11);
623 BEGIN_RING(chan
, NvSubM2MF
,
624 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN
, 8);
625 OUT_RING (chan
, src_offset
);
626 OUT_RING (chan
, dst_offset
);
627 OUT_RING (chan
, PAGE_SIZE
); /* src_pitch */
628 OUT_RING (chan
, PAGE_SIZE
); /* dst_pitch */
629 OUT_RING (chan
, PAGE_SIZE
); /* line_length */
630 OUT_RING (chan
, line_count
);
631 OUT_RING (chan
, 0x00000101);
632 OUT_RING (chan
, 0x00000000);
633 BEGIN_RING(chan
, NvSubM2MF
, NV_MEMORY_TO_MEMORY_FORMAT_NOP
, 1);
636 page_count
-= line_count
;
637 src_offset
+= (PAGE_SIZE
* line_count
);
638 dst_offset
+= (PAGE_SIZE
* line_count
);
645 nouveau_bo_move_m2mf(struct ttm_buffer_object
*bo
, int evict
, bool intr
,
646 bool no_wait_reserve
, bool no_wait_gpu
,
647 struct ttm_mem_reg
*new_mem
)
649 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
650 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
651 struct nouveau_channel
*chan
;
654 chan
= nvbo
->channel
;
655 if (!chan
|| nvbo
->no_vm
)
656 chan
= dev_priv
->channel
;
658 if (dev_priv
->card_type
< NV_50
)
659 ret
= nv04_bo_move_m2mf(chan
, bo
, &bo
->mem
, new_mem
);
661 ret
= nv50_bo_move_m2mf(chan
, bo
, &bo
->mem
, new_mem
);
665 return nouveau_bo_move_accel_cleanup(chan
, nvbo
, evict
, no_wait_reserve
, no_wait_gpu
, new_mem
);
669 nouveau_bo_move_flipd(struct ttm_buffer_object
*bo
, bool evict
, bool intr
,
670 bool no_wait_reserve
, bool no_wait_gpu
,
671 struct ttm_mem_reg
*new_mem
)
673 u32 placement_memtype
= TTM_PL_FLAG_TT
| TTM_PL_MASK_CACHING
;
674 struct ttm_placement placement
;
675 struct ttm_mem_reg tmp_mem
;
678 placement
.fpfn
= placement
.lpfn
= 0;
679 placement
.num_placement
= placement
.num_busy_placement
= 1;
680 placement
.placement
= placement
.busy_placement
= &placement_memtype
;
683 tmp_mem
.mm_node
= NULL
;
684 ret
= ttm_bo_mem_space(bo
, &placement
, &tmp_mem
, intr
, no_wait_reserve
, no_wait_gpu
);
688 ret
= ttm_tt_bind(bo
->ttm
, &tmp_mem
);
692 ret
= nouveau_bo_move_m2mf(bo
, true, intr
, no_wait_reserve
, no_wait_gpu
, &tmp_mem
);
696 ret
= ttm_bo_move_ttm(bo
, evict
, no_wait_reserve
, no_wait_gpu
, new_mem
);
698 ttm_bo_mem_put(bo
, &tmp_mem
);
703 nouveau_bo_move_flips(struct ttm_buffer_object
*bo
, bool evict
, bool intr
,
704 bool no_wait_reserve
, bool no_wait_gpu
,
705 struct ttm_mem_reg
*new_mem
)
707 u32 placement_memtype
= TTM_PL_FLAG_TT
| TTM_PL_MASK_CACHING
;
708 struct ttm_placement placement
;
709 struct ttm_mem_reg tmp_mem
;
712 placement
.fpfn
= placement
.lpfn
= 0;
713 placement
.num_placement
= placement
.num_busy_placement
= 1;
714 placement
.placement
= placement
.busy_placement
= &placement_memtype
;
717 tmp_mem
.mm_node
= NULL
;
718 ret
= ttm_bo_mem_space(bo
, &placement
, &tmp_mem
, intr
, no_wait_reserve
, no_wait_gpu
);
722 ret
= ttm_bo_move_ttm(bo
, evict
, no_wait_reserve
, no_wait_gpu
, &tmp_mem
);
726 ret
= nouveau_bo_move_m2mf(bo
, evict
, intr
, no_wait_reserve
, no_wait_gpu
, new_mem
);
731 ttm_bo_mem_put(bo
, &tmp_mem
);
736 nouveau_bo_vm_bind(struct ttm_buffer_object
*bo
, struct ttm_mem_reg
*new_mem
,
737 struct nouveau_tile_reg
**new_tile
)
739 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
740 struct drm_device
*dev
= dev_priv
->dev
;
741 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
745 if (nvbo
->no_vm
|| new_mem
->mem_type
!= TTM_PL_VRAM
) {
751 offset
= new_mem
->start
<< PAGE_SHIFT
;
753 if (dev_priv
->card_type
== NV_50
) {
754 ret
= nv50_mem_vm_bind_linear(dev
,
755 offset
+ dev_priv
->vm_vram_base
,
756 new_mem
->size
, nvbo
->tile_flags
,
761 } else if (dev_priv
->card_type
>= NV_10
) {
762 *new_tile
= nv10_mem_set_tiling(dev
, offset
, new_mem
->size
,
770 nouveau_bo_vm_cleanup(struct ttm_buffer_object
*bo
,
771 struct nouveau_tile_reg
*new_tile
,
772 struct nouveau_tile_reg
**old_tile
)
774 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
775 struct drm_device
*dev
= dev_priv
->dev
;
777 if (dev_priv
->card_type
>= NV_10
&&
778 dev_priv
->card_type
< NV_50
) {
780 nv10_mem_expire_tiling(dev
, *old_tile
, bo
->sync_obj
);
782 *old_tile
= new_tile
;
787 nouveau_bo_move(struct ttm_buffer_object
*bo
, bool evict
, bool intr
,
788 bool no_wait_reserve
, bool no_wait_gpu
,
789 struct ttm_mem_reg
*new_mem
)
791 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
792 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
793 struct ttm_mem_reg
*old_mem
= &bo
->mem
;
794 struct nouveau_tile_reg
*new_tile
= NULL
;
797 ret
= nouveau_bo_vm_bind(bo
, new_mem
, &new_tile
);
802 if (old_mem
->mem_type
== TTM_PL_SYSTEM
&& !bo
->ttm
) {
803 BUG_ON(bo
->mem
.mm_node
!= NULL
);
805 new_mem
->mm_node
= NULL
;
809 /* Software copy if the card isn't up and running yet. */
810 if (!dev_priv
->channel
) {
811 ret
= ttm_bo_move_memcpy(bo
, evict
, no_wait_reserve
, no_wait_gpu
, new_mem
);
815 /* Hardware assisted copy. */
816 if (new_mem
->mem_type
== TTM_PL_SYSTEM
)
817 ret
= nouveau_bo_move_flipd(bo
, evict
, intr
, no_wait_reserve
, no_wait_gpu
, new_mem
);
818 else if (old_mem
->mem_type
== TTM_PL_SYSTEM
)
819 ret
= nouveau_bo_move_flips(bo
, evict
, intr
, no_wait_reserve
, no_wait_gpu
, new_mem
);
821 ret
= nouveau_bo_move_m2mf(bo
, evict
, intr
, no_wait_reserve
, no_wait_gpu
, new_mem
);
826 /* Fallback to software copy. */
827 ret
= ttm_bo_move_memcpy(bo
, evict
, no_wait_reserve
, no_wait_gpu
, new_mem
);
831 nouveau_bo_vm_cleanup(bo
, NULL
, &new_tile
);
833 nouveau_bo_vm_cleanup(bo
, new_tile
, &nvbo
->tile
);
839 nouveau_bo_verify_access(struct ttm_buffer_object
*bo
, struct file
*filp
)
845 nouveau_ttm_io_mem_reserve(struct ttm_bo_device
*bdev
, struct ttm_mem_reg
*mem
)
847 struct ttm_mem_type_manager
*man
= &bdev
->man
[mem
->mem_type
];
848 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bdev
);
849 struct drm_device
*dev
= dev_priv
->dev
;
851 mem
->bus
.addr
= NULL
;
853 mem
->bus
.size
= mem
->num_pages
<< PAGE_SHIFT
;
855 mem
->bus
.is_iomem
= false;
856 if (!(man
->flags
& TTM_MEMTYPE_FLAG_MAPPABLE
))
858 switch (mem
->mem_type
) {
864 if (dev_priv
->gart_info
.type
== NOUVEAU_GART_AGP
) {
865 mem
->bus
.offset
= mem
->start
<< PAGE_SHIFT
;
866 mem
->bus
.base
= dev_priv
->gart_info
.aper_base
;
867 mem
->bus
.is_iomem
= true;
872 mem
->bus
.offset
= mem
->start
<< PAGE_SHIFT
;
873 mem
->bus
.base
= pci_resource_start(dev
->pdev
, 1);
874 mem
->bus
.is_iomem
= true;
883 nouveau_ttm_io_mem_free(struct ttm_bo_device
*bdev
, struct ttm_mem_reg
*mem
)
888 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object
*bo
)
890 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
891 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
893 /* as long as the bo isn't in vram, and isn't tiled, we've got
894 * nothing to do here.
896 if (bo
->mem
.mem_type
!= TTM_PL_VRAM
) {
897 if (dev_priv
->card_type
< NV_50
|| !nvbo
->tile_flags
)
901 /* make sure bo is in mappable vram */
902 if (bo
->mem
.start
+ bo
->mem
.num_pages
< dev_priv
->fb_mappable_pages
)
906 nvbo
->placement
.fpfn
= 0;
907 nvbo
->placement
.lpfn
= dev_priv
->fb_mappable_pages
;
908 nouveau_bo_placement_set(nvbo
, TTM_PL_VRAM
, 0);
909 return ttm_bo_validate(bo
, &nvbo
->placement
, false, true, false);
912 struct ttm_bo_driver nouveau_bo_driver
= {
913 .create_ttm_backend_entry
= nouveau_bo_create_ttm_backend_entry
,
914 .invalidate_caches
= nouveau_bo_invalidate_caches
,
915 .init_mem_type
= nouveau_bo_init_mem_type
,
916 .evict_flags
= nouveau_bo_evict_flags
,
917 .move
= nouveau_bo_move
,
918 .verify_access
= nouveau_bo_verify_access
,
919 .sync_obj_signaled
= nouveau_fence_signalled
,
920 .sync_obj_wait
= nouveau_fence_wait
,
921 .sync_obj_flush
= nouveau_fence_flush
,
922 .sync_obj_unref
= nouveau_fence_unref
,
923 .sync_obj_ref
= nouveau_fence_ref
,
924 .fault_reserve_notify
= &nouveau_ttm_fault_reserve_notify
,
925 .io_mem_reserve
= &nouveau_ttm_io_mem_reserve
,
926 .io_mem_free
= &nouveau_ttm_io_mem_free
,