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drm/nouveau: store a pointer to vm in nouveau_cli
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_bo.c
1 /*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24 /*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30 #include <core/engine.h>
31 #include <linux/swiotlb.h>
32
33 #include <subdev/fb.h>
34 #include <subdev/vm.h>
35 #include <subdev/bar.h>
36
37 #include "nouveau_drm.h"
38 #include "nouveau_dma.h"
39 #include "nouveau_fence.h"
40
41 #include "nouveau_bo.h"
42 #include "nouveau_ttm.h"
43 #include "nouveau_gem.h"
44
45 /*
46 * NV10-NV40 tiling helpers
47 */
48
49 static void
50 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
51 u32 addr, u32 size, u32 pitch, u32 flags)
52 {
53 struct nouveau_drm *drm = nouveau_drm(dev);
54 int i = reg - drm->tile.reg;
55 struct nouveau_fb *pfb = nouveau_fb(drm->device);
56 struct nouveau_fb_tile *tile = &pfb->tile.region[i];
57 struct nouveau_engine *engine;
58
59 nouveau_fence_unref(&reg->fence);
60
61 if (tile->pitch)
62 pfb->tile.fini(pfb, i, tile);
63
64 if (pitch)
65 pfb->tile.init(pfb, i, addr, size, pitch, flags, tile);
66
67 pfb->tile.prog(pfb, i, tile);
68
69 if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_GR)))
70 engine->tile_prog(engine, i);
71 if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_MPEG)))
72 engine->tile_prog(engine, i);
73 }
74
75 static struct nouveau_drm_tile *
76 nv10_bo_get_tile_region(struct drm_device *dev, int i)
77 {
78 struct nouveau_drm *drm = nouveau_drm(dev);
79 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
80
81 spin_lock(&drm->tile.lock);
82
83 if (!tile->used &&
84 (!tile->fence || nouveau_fence_done(tile->fence)))
85 tile->used = true;
86 else
87 tile = NULL;
88
89 spin_unlock(&drm->tile.lock);
90 return tile;
91 }
92
93 static void
94 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
95 struct nouveau_fence *fence)
96 {
97 struct nouveau_drm *drm = nouveau_drm(dev);
98
99 if (tile) {
100 spin_lock(&drm->tile.lock);
101 tile->fence = nouveau_fence_ref(fence);
102 tile->used = false;
103 spin_unlock(&drm->tile.lock);
104 }
105 }
106
107 static struct nouveau_drm_tile *
108 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
109 u32 size, u32 pitch, u32 flags)
110 {
111 struct nouveau_drm *drm = nouveau_drm(dev);
112 struct nouveau_fb *pfb = nouveau_fb(drm->device);
113 struct nouveau_drm_tile *tile, *found = NULL;
114 int i;
115
116 for (i = 0; i < pfb->tile.regions; i++) {
117 tile = nv10_bo_get_tile_region(dev, i);
118
119 if (pitch && !found) {
120 found = tile;
121 continue;
122
123 } else if (tile && pfb->tile.region[i].pitch) {
124 /* Kill an unused tile region. */
125 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
126 }
127
128 nv10_bo_put_tile_region(dev, tile, NULL);
129 }
130
131 if (found)
132 nv10_bo_update_tile_region(dev, found, addr, size,
133 pitch, flags);
134 return found;
135 }
136
137 static void
138 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
139 {
140 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
141 struct drm_device *dev = drm->dev;
142 struct nouveau_bo *nvbo = nouveau_bo(bo);
143
144 if (unlikely(nvbo->gem.filp))
145 DRM_ERROR("bo %p still attached to GEM object\n", bo);
146 WARN_ON(nvbo->pin_refcnt > 0);
147 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
148 kfree(nvbo);
149 }
150
151 static void
152 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
153 int *align, int *size)
154 {
155 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
156 struct nouveau_device *device = nv_device(drm->device);
157
158 if (device->card_type < NV_50) {
159 if (nvbo->tile_mode) {
160 if (device->chipset >= 0x40) {
161 *align = 65536;
162 *size = roundup(*size, 64 * nvbo->tile_mode);
163
164 } else if (device->chipset >= 0x30) {
165 *align = 32768;
166 *size = roundup(*size, 64 * nvbo->tile_mode);
167
168 } else if (device->chipset >= 0x20) {
169 *align = 16384;
170 *size = roundup(*size, 64 * nvbo->tile_mode);
171
172 } else if (device->chipset >= 0x10) {
173 *align = 16384;
174 *size = roundup(*size, 32 * nvbo->tile_mode);
175 }
176 }
177 } else {
178 *size = roundup(*size, (1 << nvbo->page_shift));
179 *align = max((1 << nvbo->page_shift), *align);
180 }
181
182 *size = roundup(*size, PAGE_SIZE);
183 }
184
185 int
186 nouveau_bo_new(struct drm_device *dev, int size, int align,
187 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
188 struct sg_table *sg,
189 struct nouveau_bo **pnvbo)
190 {
191 struct nouveau_drm *drm = nouveau_drm(dev);
192 struct nouveau_bo *nvbo;
193 size_t acc_size;
194 int ret;
195 int type = ttm_bo_type_device;
196 int lpg_shift = 12;
197 int max_size;
198
199 if (drm->client.vm)
200 lpg_shift = drm->client.vm->vmm->lpg_shift;
201 max_size = INT_MAX & ~((1 << lpg_shift) - 1);
202
203 if (size <= 0 || size > max_size) {
204 nv_warn(drm, "skipped size %x\n", (u32)size);
205 return -EINVAL;
206 }
207
208 if (sg)
209 type = ttm_bo_type_sg;
210
211 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
212 if (!nvbo)
213 return -ENOMEM;
214 INIT_LIST_HEAD(&nvbo->head);
215 INIT_LIST_HEAD(&nvbo->entry);
216 INIT_LIST_HEAD(&nvbo->vma_list);
217 nvbo->tile_mode = tile_mode;
218 nvbo->tile_flags = tile_flags;
219 nvbo->bo.bdev = &drm->ttm.bdev;
220
221 nvbo->page_shift = 12;
222 if (drm->client.vm) {
223 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
224 nvbo->page_shift = drm->client.vm->vmm->lpg_shift;
225 }
226
227 nouveau_bo_fixup_align(nvbo, flags, &align, &size);
228 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
229 nouveau_bo_placement_set(nvbo, flags, 0);
230
231 acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size,
232 sizeof(struct nouveau_bo));
233
234 ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size,
235 type, &nvbo->placement,
236 align >> PAGE_SHIFT, false, NULL, acc_size, sg,
237 nouveau_bo_del_ttm);
238 if (ret) {
239 /* ttm will call nouveau_bo_del_ttm if it fails.. */
240 return ret;
241 }
242
243 *pnvbo = nvbo;
244 return 0;
245 }
246
247 static void
248 set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
249 {
250 *n = 0;
251
252 if (type & TTM_PL_FLAG_VRAM)
253 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
254 if (type & TTM_PL_FLAG_TT)
255 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
256 if (type & TTM_PL_FLAG_SYSTEM)
257 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
258 }
259
260 static void
261 set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
262 {
263 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
264 struct nouveau_fb *pfb = nouveau_fb(drm->device);
265 u32 vram_pages = pfb->ram->size >> PAGE_SHIFT;
266
267 if ((nv_device(drm->device)->card_type == NV_10 ||
268 nv_device(drm->device)->card_type == NV_11) &&
269 nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
270 nvbo->bo.mem.num_pages < vram_pages / 4) {
271 /*
272 * Make sure that the color and depth buffers are handled
273 * by independent memory controller units. Up to a 9x
274 * speed up when alpha-blending and depth-test are enabled
275 * at the same time.
276 */
277 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
278 nvbo->placement.fpfn = vram_pages / 2;
279 nvbo->placement.lpfn = ~0;
280 } else {
281 nvbo->placement.fpfn = 0;
282 nvbo->placement.lpfn = vram_pages / 2;
283 }
284 }
285 }
286
287 void
288 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
289 {
290 struct ttm_placement *pl = &nvbo->placement;
291 uint32_t flags = TTM_PL_MASK_CACHING |
292 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
293
294 pl->placement = nvbo->placements;
295 set_placement_list(nvbo->placements, &pl->num_placement,
296 type, flags);
297
298 pl->busy_placement = nvbo->busy_placements;
299 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
300 type | busy, flags);
301
302 set_placement_range(nvbo, type);
303 }
304
305 int
306 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
307 {
308 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
309 struct ttm_buffer_object *bo = &nvbo->bo;
310 int ret;
311
312 ret = ttm_bo_reserve(bo, false, false, false, NULL);
313 if (ret)
314 goto out;
315
316 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
317 NV_ERROR(drm, "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
318 1 << bo->mem.mem_type, memtype);
319 ret = -EINVAL;
320 goto out;
321 }
322
323 if (nvbo->pin_refcnt++)
324 goto out;
325
326 nouveau_bo_placement_set(nvbo, memtype, 0);
327
328 ret = nouveau_bo_validate(nvbo, false, false);
329 if (ret == 0) {
330 switch (bo->mem.mem_type) {
331 case TTM_PL_VRAM:
332 drm->gem.vram_available -= bo->mem.size;
333 break;
334 case TTM_PL_TT:
335 drm->gem.gart_available -= bo->mem.size;
336 break;
337 default:
338 break;
339 }
340 }
341 out:
342 ttm_bo_unreserve(bo);
343 return ret;
344 }
345
346 int
347 nouveau_bo_unpin(struct nouveau_bo *nvbo)
348 {
349 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
350 struct ttm_buffer_object *bo = &nvbo->bo;
351 int ret, ref;
352
353 ret = ttm_bo_reserve(bo, false, false, false, NULL);
354 if (ret)
355 return ret;
356
357 ref = --nvbo->pin_refcnt;
358 WARN_ON_ONCE(ref < 0);
359 if (ref)
360 goto out;
361
362 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
363
364 ret = nouveau_bo_validate(nvbo, false, false);
365 if (ret == 0) {
366 switch (bo->mem.mem_type) {
367 case TTM_PL_VRAM:
368 drm->gem.vram_available += bo->mem.size;
369 break;
370 case TTM_PL_TT:
371 drm->gem.gart_available += bo->mem.size;
372 break;
373 default:
374 break;
375 }
376 }
377
378 out:
379 ttm_bo_unreserve(bo);
380 return ret;
381 }
382
383 int
384 nouveau_bo_map(struct nouveau_bo *nvbo)
385 {
386 int ret;
387
388 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, NULL);
389 if (ret)
390 return ret;
391
392 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
393 ttm_bo_unreserve(&nvbo->bo);
394 return ret;
395 }
396
397 void
398 nouveau_bo_unmap(struct nouveau_bo *nvbo)
399 {
400 if (nvbo)
401 ttm_bo_kunmap(&nvbo->kmap);
402 }
403
404 int
405 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
406 bool no_wait_gpu)
407 {
408 int ret;
409
410 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement,
411 interruptible, no_wait_gpu);
412 if (ret)
413 return ret;
414
415 return 0;
416 }
417
418 u16
419 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
420 {
421 bool is_iomem;
422 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
423 mem = &mem[index];
424 if (is_iomem)
425 return ioread16_native((void __force __iomem *)mem);
426 else
427 return *mem;
428 }
429
430 void
431 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
432 {
433 bool is_iomem;
434 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
435 mem = &mem[index];
436 if (is_iomem)
437 iowrite16_native(val, (void __force __iomem *)mem);
438 else
439 *mem = val;
440 }
441
442 u32
443 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
444 {
445 bool is_iomem;
446 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
447 mem = &mem[index];
448 if (is_iomem)
449 return ioread32_native((void __force __iomem *)mem);
450 else
451 return *mem;
452 }
453
454 void
455 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
456 {
457 bool is_iomem;
458 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
459 mem = &mem[index];
460 if (is_iomem)
461 iowrite32_native(val, (void __force __iomem *)mem);
462 else
463 *mem = val;
464 }
465
466 static struct ttm_tt *
467 nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size,
468 uint32_t page_flags, struct page *dummy_read)
469 {
470 #if __OS_HAS_AGP
471 struct nouveau_drm *drm = nouveau_bdev(bdev);
472 struct drm_device *dev = drm->dev;
473
474 if (drm->agp.stat == ENABLED) {
475 return ttm_agp_tt_create(bdev, dev->agp->bridge, size,
476 page_flags, dummy_read);
477 }
478 #endif
479
480 return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read);
481 }
482
483 static int
484 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
485 {
486 /* We'll do this from user space. */
487 return 0;
488 }
489
490 static int
491 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
492 struct ttm_mem_type_manager *man)
493 {
494 struct nouveau_drm *drm = nouveau_bdev(bdev);
495
496 switch (type) {
497 case TTM_PL_SYSTEM:
498 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
499 man->available_caching = TTM_PL_MASK_CACHING;
500 man->default_caching = TTM_PL_FLAG_CACHED;
501 break;
502 case TTM_PL_VRAM:
503 man->flags = TTM_MEMTYPE_FLAG_FIXED |
504 TTM_MEMTYPE_FLAG_MAPPABLE;
505 man->available_caching = TTM_PL_FLAG_UNCACHED |
506 TTM_PL_FLAG_WC;
507 man->default_caching = TTM_PL_FLAG_WC;
508
509 if (nv_device(drm->device)->card_type >= NV_50) {
510 /* Some BARs do not support being ioremapped WC */
511 if (nouveau_bar(drm->device)->iomap_uncached) {
512 man->available_caching = TTM_PL_FLAG_UNCACHED;
513 man->default_caching = TTM_PL_FLAG_UNCACHED;
514 }
515
516 man->func = &nouveau_vram_manager;
517 man->io_reserve_fastpath = false;
518 man->use_io_reserve_lru = true;
519 } else {
520 man->func = &ttm_bo_manager_func;
521 }
522 break;
523 case TTM_PL_TT:
524 if (nv_device(drm->device)->card_type >= NV_50)
525 man->func = &nouveau_gart_manager;
526 else
527 if (drm->agp.stat != ENABLED)
528 man->func = &nv04_gart_manager;
529 else
530 man->func = &ttm_bo_manager_func;
531
532 if (drm->agp.stat == ENABLED) {
533 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
534 man->available_caching = TTM_PL_FLAG_UNCACHED |
535 TTM_PL_FLAG_WC;
536 man->default_caching = TTM_PL_FLAG_WC;
537 } else {
538 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
539 TTM_MEMTYPE_FLAG_CMA;
540 man->available_caching = TTM_PL_MASK_CACHING;
541 man->default_caching = TTM_PL_FLAG_CACHED;
542 }
543
544 break;
545 default:
546 return -EINVAL;
547 }
548 return 0;
549 }
550
551 static void
552 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
553 {
554 struct nouveau_bo *nvbo = nouveau_bo(bo);
555
556 switch (bo->mem.mem_type) {
557 case TTM_PL_VRAM:
558 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
559 TTM_PL_FLAG_SYSTEM);
560 break;
561 default:
562 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
563 break;
564 }
565
566 *pl = nvbo->placement;
567 }
568
569
570 static int
571 nve0_bo_move_init(struct nouveau_channel *chan, u32 handle)
572 {
573 int ret = RING_SPACE(chan, 2);
574 if (ret == 0) {
575 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
576 OUT_RING (chan, handle & 0x0000ffff);
577 FIRE_RING (chan);
578 }
579 return ret;
580 }
581
582 static int
583 nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
584 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
585 {
586 struct nouveau_mem *node = old_mem->mm_node;
587 int ret = RING_SPACE(chan, 10);
588 if (ret == 0) {
589 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
590 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
591 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
592 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
593 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
594 OUT_RING (chan, PAGE_SIZE);
595 OUT_RING (chan, PAGE_SIZE);
596 OUT_RING (chan, PAGE_SIZE);
597 OUT_RING (chan, new_mem->num_pages);
598 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
599 }
600 return ret;
601 }
602
603 static int
604 nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
605 {
606 int ret = RING_SPACE(chan, 2);
607 if (ret == 0) {
608 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
609 OUT_RING (chan, handle);
610 }
611 return ret;
612 }
613
614 static int
615 nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
616 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
617 {
618 struct nouveau_mem *node = old_mem->mm_node;
619 u64 src_offset = node->vma[0].offset;
620 u64 dst_offset = node->vma[1].offset;
621 u32 page_count = new_mem->num_pages;
622 int ret;
623
624 page_count = new_mem->num_pages;
625 while (page_count) {
626 int line_count = (page_count > 8191) ? 8191 : page_count;
627
628 ret = RING_SPACE(chan, 11);
629 if (ret)
630 return ret;
631
632 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8);
633 OUT_RING (chan, upper_32_bits(src_offset));
634 OUT_RING (chan, lower_32_bits(src_offset));
635 OUT_RING (chan, upper_32_bits(dst_offset));
636 OUT_RING (chan, lower_32_bits(dst_offset));
637 OUT_RING (chan, PAGE_SIZE);
638 OUT_RING (chan, PAGE_SIZE);
639 OUT_RING (chan, PAGE_SIZE);
640 OUT_RING (chan, line_count);
641 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
642 OUT_RING (chan, 0x00000110);
643
644 page_count -= line_count;
645 src_offset += (PAGE_SIZE * line_count);
646 dst_offset += (PAGE_SIZE * line_count);
647 }
648
649 return 0;
650 }
651
652 static int
653 nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
654 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
655 {
656 struct nouveau_mem *node = old_mem->mm_node;
657 u64 src_offset = node->vma[0].offset;
658 u64 dst_offset = node->vma[1].offset;
659 u32 page_count = new_mem->num_pages;
660 int ret;
661
662 page_count = new_mem->num_pages;
663 while (page_count) {
664 int line_count = (page_count > 2047) ? 2047 : page_count;
665
666 ret = RING_SPACE(chan, 12);
667 if (ret)
668 return ret;
669
670 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
671 OUT_RING (chan, upper_32_bits(dst_offset));
672 OUT_RING (chan, lower_32_bits(dst_offset));
673 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
674 OUT_RING (chan, upper_32_bits(src_offset));
675 OUT_RING (chan, lower_32_bits(src_offset));
676 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
677 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
678 OUT_RING (chan, PAGE_SIZE); /* line_length */
679 OUT_RING (chan, line_count);
680 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
681 OUT_RING (chan, 0x00100110);
682
683 page_count -= line_count;
684 src_offset += (PAGE_SIZE * line_count);
685 dst_offset += (PAGE_SIZE * line_count);
686 }
687
688 return 0;
689 }
690
691 static int
692 nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
693 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
694 {
695 struct nouveau_mem *node = old_mem->mm_node;
696 u64 src_offset = node->vma[0].offset;
697 u64 dst_offset = node->vma[1].offset;
698 u32 page_count = new_mem->num_pages;
699 int ret;
700
701 page_count = new_mem->num_pages;
702 while (page_count) {
703 int line_count = (page_count > 8191) ? 8191 : page_count;
704
705 ret = RING_SPACE(chan, 11);
706 if (ret)
707 return ret;
708
709 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
710 OUT_RING (chan, upper_32_bits(src_offset));
711 OUT_RING (chan, lower_32_bits(src_offset));
712 OUT_RING (chan, upper_32_bits(dst_offset));
713 OUT_RING (chan, lower_32_bits(dst_offset));
714 OUT_RING (chan, PAGE_SIZE);
715 OUT_RING (chan, PAGE_SIZE);
716 OUT_RING (chan, PAGE_SIZE);
717 OUT_RING (chan, line_count);
718 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1);
719 OUT_RING (chan, 0x00000110);
720
721 page_count -= line_count;
722 src_offset += (PAGE_SIZE * line_count);
723 dst_offset += (PAGE_SIZE * line_count);
724 }
725
726 return 0;
727 }
728
729 static int
730 nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
731 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
732 {
733 struct nouveau_mem *node = old_mem->mm_node;
734 int ret = RING_SPACE(chan, 7);
735 if (ret == 0) {
736 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
737 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
738 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
739 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
740 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
741 OUT_RING (chan, 0x00000000 /* COPY */);
742 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
743 }
744 return ret;
745 }
746
747 static int
748 nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
749 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
750 {
751 struct nouveau_mem *node = old_mem->mm_node;
752 int ret = RING_SPACE(chan, 7);
753 if (ret == 0) {
754 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
755 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
756 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
757 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
758 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
759 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
760 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */);
761 }
762 return ret;
763 }
764
765 static int
766 nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
767 {
768 int ret = RING_SPACE(chan, 6);
769 if (ret == 0) {
770 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
771 OUT_RING (chan, handle);
772 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
773 OUT_RING (chan, NvNotify0);
774 OUT_RING (chan, NvDmaFB);
775 OUT_RING (chan, NvDmaFB);
776 }
777
778 return ret;
779 }
780
781 static int
782 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
783 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
784 {
785 struct nouveau_mem *node = old_mem->mm_node;
786 u64 length = (new_mem->num_pages << PAGE_SHIFT);
787 u64 src_offset = node->vma[0].offset;
788 u64 dst_offset = node->vma[1].offset;
789 int src_tiled = !!node->memtype;
790 int dst_tiled = !!((struct nouveau_mem *)new_mem->mm_node)->memtype;
791 int ret;
792
793 while (length) {
794 u32 amount, stride, height;
795
796 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled));
797 if (ret)
798 return ret;
799
800 amount = min(length, (u64)(4 * 1024 * 1024));
801 stride = 16 * 4;
802 height = amount / stride;
803
804 if (src_tiled) {
805 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
806 OUT_RING (chan, 0);
807 OUT_RING (chan, 0);
808 OUT_RING (chan, stride);
809 OUT_RING (chan, height);
810 OUT_RING (chan, 1);
811 OUT_RING (chan, 0);
812 OUT_RING (chan, 0);
813 } else {
814 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
815 OUT_RING (chan, 1);
816 }
817 if (dst_tiled) {
818 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
819 OUT_RING (chan, 0);
820 OUT_RING (chan, 0);
821 OUT_RING (chan, stride);
822 OUT_RING (chan, height);
823 OUT_RING (chan, 1);
824 OUT_RING (chan, 0);
825 OUT_RING (chan, 0);
826 } else {
827 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
828 OUT_RING (chan, 1);
829 }
830
831 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
832 OUT_RING (chan, upper_32_bits(src_offset));
833 OUT_RING (chan, upper_32_bits(dst_offset));
834 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
835 OUT_RING (chan, lower_32_bits(src_offset));
836 OUT_RING (chan, lower_32_bits(dst_offset));
837 OUT_RING (chan, stride);
838 OUT_RING (chan, stride);
839 OUT_RING (chan, stride);
840 OUT_RING (chan, height);
841 OUT_RING (chan, 0x00000101);
842 OUT_RING (chan, 0x00000000);
843 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
844 OUT_RING (chan, 0);
845
846 length -= amount;
847 src_offset += amount;
848 dst_offset += amount;
849 }
850
851 return 0;
852 }
853
854 static int
855 nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
856 {
857 int ret = RING_SPACE(chan, 4);
858 if (ret == 0) {
859 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
860 OUT_RING (chan, handle);
861 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
862 OUT_RING (chan, NvNotify0);
863 }
864
865 return ret;
866 }
867
868 static inline uint32_t
869 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
870 struct nouveau_channel *chan, struct ttm_mem_reg *mem)
871 {
872 if (mem->mem_type == TTM_PL_TT)
873 return NvDmaTT;
874 return NvDmaFB;
875 }
876
877 static int
878 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
879 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
880 {
881 u32 src_offset = old_mem->start << PAGE_SHIFT;
882 u32 dst_offset = new_mem->start << PAGE_SHIFT;
883 u32 page_count = new_mem->num_pages;
884 int ret;
885
886 ret = RING_SPACE(chan, 3);
887 if (ret)
888 return ret;
889
890 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
891 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
892 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
893
894 page_count = new_mem->num_pages;
895 while (page_count) {
896 int line_count = (page_count > 2047) ? 2047 : page_count;
897
898 ret = RING_SPACE(chan, 11);
899 if (ret)
900 return ret;
901
902 BEGIN_NV04(chan, NvSubCopy,
903 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
904 OUT_RING (chan, src_offset);
905 OUT_RING (chan, dst_offset);
906 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
907 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
908 OUT_RING (chan, PAGE_SIZE); /* line_length */
909 OUT_RING (chan, line_count);
910 OUT_RING (chan, 0x00000101);
911 OUT_RING (chan, 0x00000000);
912 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
913 OUT_RING (chan, 0);
914
915 page_count -= line_count;
916 src_offset += (PAGE_SIZE * line_count);
917 dst_offset += (PAGE_SIZE * line_count);
918 }
919
920 return 0;
921 }
922
923 static int
924 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
925 struct ttm_mem_reg *mem)
926 {
927 struct nouveau_mem *old_node = bo->mem.mm_node;
928 struct nouveau_mem *new_node = mem->mm_node;
929 u64 size = (u64)mem->num_pages << PAGE_SHIFT;
930 int ret;
931
932 ret = nouveau_vm_get(drm->client.vm, size, old_node->page_shift,
933 NV_MEM_ACCESS_RW, &old_node->vma[0]);
934 if (ret)
935 return ret;
936
937 ret = nouveau_vm_get(drm->client.vm, size, new_node->page_shift,
938 NV_MEM_ACCESS_RW, &old_node->vma[1]);
939 if (ret) {
940 nouveau_vm_put(&old_node->vma[0]);
941 return ret;
942 }
943
944 nouveau_vm_map(&old_node->vma[0], old_node);
945 nouveau_vm_map(&old_node->vma[1], new_node);
946 return 0;
947 }
948
949 static int
950 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
951 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
952 {
953 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
954 struct nouveau_channel *chan = drm->ttm.chan;
955 struct nouveau_fence *fence;
956 int ret;
957
958 /* create temporary vmas for the transfer and attach them to the
959 * old nouveau_mem node, these will get cleaned up after ttm has
960 * destroyed the ttm_mem_reg
961 */
962 if (nv_device(drm->device)->card_type >= NV_50) {
963 ret = nouveau_bo_move_prep(drm, bo, new_mem);
964 if (ret)
965 return ret;
966 }
967
968 mutex_lock_nested(&chan->cli->mutex, SINGLE_DEPTH_NESTING);
969 ret = nouveau_fence_sync(bo->sync_obj, chan);
970 if (ret == 0) {
971 ret = drm->ttm.move(chan, bo, &bo->mem, new_mem);
972 if (ret == 0) {
973 ret = nouveau_fence_new(chan, false, &fence);
974 if (ret == 0) {
975 ret = ttm_bo_move_accel_cleanup(bo, fence,
976 evict,
977 no_wait_gpu,
978 new_mem);
979 nouveau_fence_unref(&fence);
980 }
981 }
982 }
983 mutex_unlock(&chan->cli->mutex);
984 return ret;
985 }
986
987 void
988 nouveau_bo_move_init(struct nouveau_drm *drm)
989 {
990 static const struct {
991 const char *name;
992 int engine;
993 u32 oclass;
994 int (*exec)(struct nouveau_channel *,
995 struct ttm_buffer_object *,
996 struct ttm_mem_reg *, struct ttm_mem_reg *);
997 int (*init)(struct nouveau_channel *, u32 handle);
998 } _methods[] = {
999 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
1000 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1001 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
1002 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
1003 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
1004 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
1005 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
1006 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
1007 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
1008 {},
1009 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init },
1010 }, *mthd = _methods;
1011 const char *name = "CPU";
1012 int ret;
1013
1014 do {
1015 struct nouveau_object *object;
1016 struct nouveau_channel *chan;
1017 u32 handle = (mthd->engine << 16) | mthd->oclass;
1018
1019 if (mthd->engine)
1020 chan = drm->cechan;
1021 else
1022 chan = drm->channel;
1023 if (chan == NULL)
1024 continue;
1025
1026 ret = nouveau_object_new(nv_object(drm), chan->handle, handle,
1027 mthd->oclass, NULL, 0, &object);
1028 if (ret == 0) {
1029 ret = mthd->init(chan, handle);
1030 if (ret) {
1031 nouveau_object_del(nv_object(drm),
1032 chan->handle, handle);
1033 continue;
1034 }
1035
1036 drm->ttm.move = mthd->exec;
1037 drm->ttm.chan = chan;
1038 name = mthd->name;
1039 break;
1040 }
1041 } while ((++mthd)->exec);
1042
1043 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
1044 }
1045
1046 static int
1047 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
1048 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1049 {
1050 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
1051 struct ttm_placement placement;
1052 struct ttm_mem_reg tmp_mem;
1053 int ret;
1054
1055 placement.fpfn = placement.lpfn = 0;
1056 placement.num_placement = placement.num_busy_placement = 1;
1057 placement.placement = placement.busy_placement = &placement_memtype;
1058
1059 tmp_mem = *new_mem;
1060 tmp_mem.mm_node = NULL;
1061 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1062 if (ret)
1063 return ret;
1064
1065 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
1066 if (ret)
1067 goto out;
1068
1069 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_mem);
1070 if (ret)
1071 goto out;
1072
1073 ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
1074 out:
1075 ttm_bo_mem_put(bo, &tmp_mem);
1076 return ret;
1077 }
1078
1079 static int
1080 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
1081 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1082 {
1083 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
1084 struct ttm_placement placement;
1085 struct ttm_mem_reg tmp_mem;
1086 int ret;
1087
1088 placement.fpfn = placement.lpfn = 0;
1089 placement.num_placement = placement.num_busy_placement = 1;
1090 placement.placement = placement.busy_placement = &placement_memtype;
1091
1092 tmp_mem = *new_mem;
1093 tmp_mem.mm_node = NULL;
1094 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1095 if (ret)
1096 return ret;
1097
1098 ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
1099 if (ret)
1100 goto out;
1101
1102 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_mem);
1103 if (ret)
1104 goto out;
1105
1106 out:
1107 ttm_bo_mem_put(bo, &tmp_mem);
1108 return ret;
1109 }
1110
1111 static void
1112 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
1113 {
1114 struct nouveau_bo *nvbo = nouveau_bo(bo);
1115 struct nouveau_vma *vma;
1116
1117 /* ttm can now (stupidly) pass the driver bos it didn't create... */
1118 if (bo->destroy != nouveau_bo_del_ttm)
1119 return;
1120
1121 list_for_each_entry(vma, &nvbo->vma_list, head) {
1122 if (new_mem && new_mem->mem_type != TTM_PL_SYSTEM &&
1123 (new_mem->mem_type == TTM_PL_VRAM ||
1124 nvbo->page_shift != vma->vm->vmm->lpg_shift)) {
1125 nouveau_vm_map(vma, new_mem->mm_node);
1126 } else {
1127 nouveau_vm_unmap(vma);
1128 }
1129 }
1130 }
1131
1132 static int
1133 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
1134 struct nouveau_drm_tile **new_tile)
1135 {
1136 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1137 struct drm_device *dev = drm->dev;
1138 struct nouveau_bo *nvbo = nouveau_bo(bo);
1139 u64 offset = new_mem->start << PAGE_SHIFT;
1140
1141 *new_tile = NULL;
1142 if (new_mem->mem_type != TTM_PL_VRAM)
1143 return 0;
1144
1145 if (nv_device(drm->device)->card_type >= NV_10) {
1146 *new_tile = nv10_bo_set_tiling(dev, offset, new_mem->size,
1147 nvbo->tile_mode,
1148 nvbo->tile_flags);
1149 }
1150
1151 return 0;
1152 }
1153
1154 static void
1155 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1156 struct nouveau_drm_tile *new_tile,
1157 struct nouveau_drm_tile **old_tile)
1158 {
1159 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1160 struct drm_device *dev = drm->dev;
1161
1162 nv10_bo_put_tile_region(dev, *old_tile, bo->sync_obj);
1163 *old_tile = new_tile;
1164 }
1165
1166 static int
1167 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
1168 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1169 {
1170 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1171 struct nouveau_bo *nvbo = nouveau_bo(bo);
1172 struct ttm_mem_reg *old_mem = &bo->mem;
1173 struct nouveau_drm_tile *new_tile = NULL;
1174 int ret = 0;
1175
1176 if (nv_device(drm->device)->card_type < NV_50) {
1177 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
1178 if (ret)
1179 return ret;
1180 }
1181
1182 /* Fake bo copy. */
1183 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1184 BUG_ON(bo->mem.mm_node != NULL);
1185 bo->mem = *new_mem;
1186 new_mem->mm_node = NULL;
1187 goto out;
1188 }
1189
1190 /* Hardware assisted copy. */
1191 if (drm->ttm.move) {
1192 if (new_mem->mem_type == TTM_PL_SYSTEM)
1193 ret = nouveau_bo_move_flipd(bo, evict, intr,
1194 no_wait_gpu, new_mem);
1195 else if (old_mem->mem_type == TTM_PL_SYSTEM)
1196 ret = nouveau_bo_move_flips(bo, evict, intr,
1197 no_wait_gpu, new_mem);
1198 else
1199 ret = nouveau_bo_move_m2mf(bo, evict, intr,
1200 no_wait_gpu, new_mem);
1201 if (!ret)
1202 goto out;
1203 }
1204
1205 /* Fallback to software copy. */
1206 spin_lock(&bo->bdev->fence_lock);
1207 ret = ttm_bo_wait(bo, true, intr, no_wait_gpu);
1208 spin_unlock(&bo->bdev->fence_lock);
1209 if (ret == 0)
1210 ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
1211
1212 out:
1213 if (nv_device(drm->device)->card_type < NV_50) {
1214 if (ret)
1215 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1216 else
1217 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1218 }
1219
1220 return ret;
1221 }
1222
1223 static int
1224 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1225 {
1226 struct nouveau_bo *nvbo = nouveau_bo(bo);
1227
1228 return drm_vma_node_verify_access(&nvbo->gem.vma_node, filp);
1229 }
1230
1231 static int
1232 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1233 {
1234 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
1235 struct nouveau_drm *drm = nouveau_bdev(bdev);
1236 struct nouveau_mem *node = mem->mm_node;
1237 struct drm_device *dev = drm->dev;
1238 int ret;
1239
1240 mem->bus.addr = NULL;
1241 mem->bus.offset = 0;
1242 mem->bus.size = mem->num_pages << PAGE_SHIFT;
1243 mem->bus.base = 0;
1244 mem->bus.is_iomem = false;
1245 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
1246 return -EINVAL;
1247 switch (mem->mem_type) {
1248 case TTM_PL_SYSTEM:
1249 /* System memory */
1250 return 0;
1251 case TTM_PL_TT:
1252 #if __OS_HAS_AGP
1253 if (drm->agp.stat == ENABLED) {
1254 mem->bus.offset = mem->start << PAGE_SHIFT;
1255 mem->bus.base = drm->agp.base;
1256 mem->bus.is_iomem = !dev->agp->cant_use_aperture;
1257 }
1258 #endif
1259 if (nv_device(drm->device)->card_type < NV_50 || !node->memtype)
1260 /* untiled */
1261 break;
1262 /* fallthrough, tiled memory */
1263 case TTM_PL_VRAM:
1264 mem->bus.offset = mem->start << PAGE_SHIFT;
1265 mem->bus.base = nv_device_resource_start(nouveau_dev(dev), 1);
1266 mem->bus.is_iomem = true;
1267 if (nv_device(drm->device)->card_type >= NV_50) {
1268 struct nouveau_bar *bar = nouveau_bar(drm->device);
1269
1270 ret = bar->umap(bar, node, NV_MEM_ACCESS_RW,
1271 &node->bar_vma);
1272 if (ret)
1273 return ret;
1274
1275 mem->bus.offset = node->bar_vma.offset;
1276 }
1277 break;
1278 default:
1279 return -EINVAL;
1280 }
1281 return 0;
1282 }
1283
1284 static void
1285 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1286 {
1287 struct nouveau_drm *drm = nouveau_bdev(bdev);
1288 struct nouveau_bar *bar = nouveau_bar(drm->device);
1289 struct nouveau_mem *node = mem->mm_node;
1290
1291 if (!node->bar_vma.node)
1292 return;
1293
1294 bar->unmap(bar, &node->bar_vma);
1295 }
1296
1297 static int
1298 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1299 {
1300 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1301 struct nouveau_bo *nvbo = nouveau_bo(bo);
1302 struct nouveau_device *device = nv_device(drm->device);
1303 u32 mappable = nv_device_resource_len(device, 1) >> PAGE_SHIFT;
1304 int ret;
1305
1306 /* as long as the bo isn't in vram, and isn't tiled, we've got
1307 * nothing to do here.
1308 */
1309 if (bo->mem.mem_type != TTM_PL_VRAM) {
1310 if (nv_device(drm->device)->card_type < NV_50 ||
1311 !nouveau_bo_tile_layout(nvbo))
1312 return 0;
1313
1314 if (bo->mem.mem_type == TTM_PL_SYSTEM) {
1315 nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0);
1316
1317 ret = nouveau_bo_validate(nvbo, false, false);
1318 if (ret)
1319 return ret;
1320 }
1321 return 0;
1322 }
1323
1324 /* make sure bo is in mappable vram */
1325 if (nv_device(drm->device)->card_type >= NV_50 ||
1326 bo->mem.start + bo->mem.num_pages < mappable)
1327 return 0;
1328
1329
1330 nvbo->placement.fpfn = 0;
1331 nvbo->placement.lpfn = mappable;
1332 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
1333 return nouveau_bo_validate(nvbo, false, false);
1334 }
1335
1336 static int
1337 nouveau_ttm_tt_populate(struct ttm_tt *ttm)
1338 {
1339 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1340 struct nouveau_drm *drm;
1341 struct nouveau_device *device;
1342 struct drm_device *dev;
1343 struct device *pdev;
1344 unsigned i;
1345 int r;
1346 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1347
1348 if (ttm->state != tt_unpopulated)
1349 return 0;
1350
1351 if (slave && ttm->sg) {
1352 /* make userspace faulting work */
1353 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1354 ttm_dma->dma_address, ttm->num_pages);
1355 ttm->state = tt_unbound;
1356 return 0;
1357 }
1358
1359 drm = nouveau_bdev(ttm->bdev);
1360 device = nv_device(drm->device);
1361 dev = drm->dev;
1362 pdev = nv_device_base(device);
1363
1364 #if __OS_HAS_AGP
1365 if (drm->agp.stat == ENABLED) {
1366 return ttm_agp_tt_populate(ttm);
1367 }
1368 #endif
1369
1370 #ifdef CONFIG_SWIOTLB
1371 if (swiotlb_nr_tbl()) {
1372 return ttm_dma_populate((void *)ttm, dev->dev);
1373 }
1374 #endif
1375
1376 r = ttm_pool_populate(ttm);
1377 if (r) {
1378 return r;
1379 }
1380
1381 for (i = 0; i < ttm->num_pages; i++) {
1382 dma_addr_t addr;
1383
1384 addr = dma_map_page(pdev, ttm->pages[i], 0, PAGE_SIZE,
1385 DMA_BIDIRECTIONAL);
1386
1387 if (dma_mapping_error(pdev, addr)) {
1388 while (--i) {
1389 dma_unmap_page(pdev, ttm_dma->dma_address[i],
1390 PAGE_SIZE, DMA_BIDIRECTIONAL);
1391 ttm_dma->dma_address[i] = 0;
1392 }
1393 ttm_pool_unpopulate(ttm);
1394 return -EFAULT;
1395 }
1396
1397 ttm_dma->dma_address[i] = addr;
1398 }
1399 return 0;
1400 }
1401
1402 static void
1403 nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1404 {
1405 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1406 struct nouveau_drm *drm;
1407 struct nouveau_device *device;
1408 struct drm_device *dev;
1409 struct device *pdev;
1410 unsigned i;
1411 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1412
1413 if (slave)
1414 return;
1415
1416 drm = nouveau_bdev(ttm->bdev);
1417 device = nv_device(drm->device);
1418 dev = drm->dev;
1419 pdev = nv_device_base(device);
1420
1421 #if __OS_HAS_AGP
1422 if (drm->agp.stat == ENABLED) {
1423 ttm_agp_tt_unpopulate(ttm);
1424 return;
1425 }
1426 #endif
1427
1428 #ifdef CONFIG_SWIOTLB
1429 if (swiotlb_nr_tbl()) {
1430 ttm_dma_unpopulate((void *)ttm, dev->dev);
1431 return;
1432 }
1433 #endif
1434
1435 for (i = 0; i < ttm->num_pages; i++) {
1436 if (ttm_dma->dma_address[i]) {
1437 dma_unmap_page(pdev, ttm_dma->dma_address[i], PAGE_SIZE,
1438 DMA_BIDIRECTIONAL);
1439 }
1440 }
1441
1442 ttm_pool_unpopulate(ttm);
1443 }
1444
1445 void
1446 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
1447 {
1448 struct nouveau_fence *new_fence = nouveau_fence_ref(fence);
1449 struct nouveau_fence *old_fence = NULL;
1450
1451 spin_lock(&nvbo->bo.bdev->fence_lock);
1452 old_fence = nvbo->bo.sync_obj;
1453 nvbo->bo.sync_obj = new_fence;
1454 spin_unlock(&nvbo->bo.bdev->fence_lock);
1455
1456 nouveau_fence_unref(&old_fence);
1457 }
1458
1459 static void
1460 nouveau_bo_fence_unref(void **sync_obj)
1461 {
1462 nouveau_fence_unref((struct nouveau_fence **)sync_obj);
1463 }
1464
1465 static void *
1466 nouveau_bo_fence_ref(void *sync_obj)
1467 {
1468 return nouveau_fence_ref(sync_obj);
1469 }
1470
1471 static bool
1472 nouveau_bo_fence_signalled(void *sync_obj)
1473 {
1474 return nouveau_fence_done(sync_obj);
1475 }
1476
1477 static int
1478 nouveau_bo_fence_wait(void *sync_obj, bool lazy, bool intr)
1479 {
1480 return nouveau_fence_wait(sync_obj, lazy, intr);
1481 }
1482
1483 static int
1484 nouveau_bo_fence_flush(void *sync_obj)
1485 {
1486 return 0;
1487 }
1488
1489 struct ttm_bo_driver nouveau_bo_driver = {
1490 .ttm_tt_create = &nouveau_ttm_tt_create,
1491 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1492 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1493 .invalidate_caches = nouveau_bo_invalidate_caches,
1494 .init_mem_type = nouveau_bo_init_mem_type,
1495 .evict_flags = nouveau_bo_evict_flags,
1496 .move_notify = nouveau_bo_move_ntfy,
1497 .move = nouveau_bo_move,
1498 .verify_access = nouveau_bo_verify_access,
1499 .sync_obj_signaled = nouveau_bo_fence_signalled,
1500 .sync_obj_wait = nouveau_bo_fence_wait,
1501 .sync_obj_flush = nouveau_bo_fence_flush,
1502 .sync_obj_unref = nouveau_bo_fence_unref,
1503 .sync_obj_ref = nouveau_bo_fence_ref,
1504 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1505 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1506 .io_mem_free = &nouveau_ttm_io_mem_free,
1507 };
1508
1509 struct nouveau_vma *
1510 nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm)
1511 {
1512 struct nouveau_vma *vma;
1513 list_for_each_entry(vma, &nvbo->vma_list, head) {
1514 if (vma->vm == vm)
1515 return vma;
1516 }
1517
1518 return NULL;
1519 }
1520
1521 int
1522 nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
1523 struct nouveau_vma *vma)
1524 {
1525 const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
1526 int ret;
1527
1528 ret = nouveau_vm_get(vm, size, nvbo->page_shift,
1529 NV_MEM_ACCESS_RW, vma);
1530 if (ret)
1531 return ret;
1532
1533 if ( nvbo->bo.mem.mem_type != TTM_PL_SYSTEM &&
1534 (nvbo->bo.mem.mem_type == TTM_PL_VRAM ||
1535 nvbo->page_shift != vma->vm->vmm->lpg_shift))
1536 nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
1537
1538 list_add_tail(&vma->head, &nvbo->vma_list);
1539 vma->refcount = 1;
1540 return 0;
1541 }
1542
1543 void
1544 nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
1545 {
1546 if (vma->node) {
1547 if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM)
1548 nouveau_vm_unmap(vma);
1549 nouveau_vm_put(vma);
1550 list_del(&vma->head);
1551 }
1552 }
Linux kernel - Deliverables
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