2 * Copyright 2007 Dave Airlied
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
30 #include <core/engine.h>
31 #include <linux/swiotlb.h>
33 #include <subdev/fb.h>
34 #include <subdev/vm.h>
35 #include <subdev/bar.h>
37 #include "nouveau_drm.h"
38 #include "nouveau_dma.h"
39 #include "nouveau_fence.h"
41 #include "nouveau_bo.h"
42 #include "nouveau_ttm.h"
43 #include "nouveau_gem.h"
46 * NV10-NV40 tiling helpers
50 nv10_bo_update_tile_region(struct drm_device
*dev
, struct nouveau_drm_tile
*reg
,
51 u32 addr
, u32 size
, u32 pitch
, u32 flags
)
53 struct nouveau_drm
*drm
= nouveau_drm(dev
);
54 int i
= reg
- drm
->tile
.reg
;
55 struct nouveau_fb
*pfb
= nouveau_fb(drm
->device
);
56 struct nouveau_fb_tile
*tile
= &pfb
->tile
.region
[i
];
57 struct nouveau_engine
*engine
;
59 nouveau_fence_unref(®
->fence
);
62 pfb
->tile
.fini(pfb
, i
, tile
);
65 pfb
->tile
.init(pfb
, i
, addr
, size
, pitch
, flags
, tile
);
67 pfb
->tile
.prog(pfb
, i
, tile
);
69 if ((engine
= nouveau_engine(pfb
, NVDEV_ENGINE_GR
)))
70 engine
->tile_prog(engine
, i
);
71 if ((engine
= nouveau_engine(pfb
, NVDEV_ENGINE_MPEG
)))
72 engine
->tile_prog(engine
, i
);
75 static struct nouveau_drm_tile
*
76 nv10_bo_get_tile_region(struct drm_device
*dev
, int i
)
78 struct nouveau_drm
*drm
= nouveau_drm(dev
);
79 struct nouveau_drm_tile
*tile
= &drm
->tile
.reg
[i
];
81 spin_lock(&drm
->tile
.lock
);
84 (!tile
->fence
|| nouveau_fence_done(tile
->fence
)))
89 spin_unlock(&drm
->tile
.lock
);
94 nv10_bo_put_tile_region(struct drm_device
*dev
, struct nouveau_drm_tile
*tile
,
95 struct nouveau_fence
*fence
)
97 struct nouveau_drm
*drm
= nouveau_drm(dev
);
100 spin_lock(&drm
->tile
.lock
);
101 tile
->fence
= nouveau_fence_ref(fence
);
103 spin_unlock(&drm
->tile
.lock
);
107 static struct nouveau_drm_tile
*
108 nv10_bo_set_tiling(struct drm_device
*dev
, u32 addr
,
109 u32 size
, u32 pitch
, u32 flags
)
111 struct nouveau_drm
*drm
= nouveau_drm(dev
);
112 struct nouveau_fb
*pfb
= nouveau_fb(drm
->device
);
113 struct nouveau_drm_tile
*tile
, *found
= NULL
;
116 for (i
= 0; i
< pfb
->tile
.regions
; i
++) {
117 tile
= nv10_bo_get_tile_region(dev
, i
);
119 if (pitch
&& !found
) {
123 } else if (tile
&& pfb
->tile
.region
[i
].pitch
) {
124 /* Kill an unused tile region. */
125 nv10_bo_update_tile_region(dev
, tile
, 0, 0, 0, 0);
128 nv10_bo_put_tile_region(dev
, tile
, NULL
);
132 nv10_bo_update_tile_region(dev
, found
, addr
, size
,
138 nouveau_bo_del_ttm(struct ttm_buffer_object
*bo
)
140 struct nouveau_drm
*drm
= nouveau_bdev(bo
->bdev
);
141 struct drm_device
*dev
= drm
->dev
;
142 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
144 if (unlikely(nvbo
->gem
.filp
))
145 DRM_ERROR("bo %p still attached to GEM object\n", bo
);
146 WARN_ON(nvbo
->pin_refcnt
> 0);
147 nv10_bo_put_tile_region(dev
, nvbo
->tile
, NULL
);
152 nouveau_bo_fixup_align(struct nouveau_bo
*nvbo
, u32 flags
,
153 int *align
, int *size
)
155 struct nouveau_drm
*drm
= nouveau_bdev(nvbo
->bo
.bdev
);
156 struct nouveau_device
*device
= nv_device(drm
->device
);
158 if (device
->card_type
< NV_50
) {
159 if (nvbo
->tile_mode
) {
160 if (device
->chipset
>= 0x40) {
162 *size
= roundup(*size
, 64 * nvbo
->tile_mode
);
164 } else if (device
->chipset
>= 0x30) {
166 *size
= roundup(*size
, 64 * nvbo
->tile_mode
);
168 } else if (device
->chipset
>= 0x20) {
170 *size
= roundup(*size
, 64 * nvbo
->tile_mode
);
172 } else if (device
->chipset
>= 0x10) {
174 *size
= roundup(*size
, 32 * nvbo
->tile_mode
);
178 *size
= roundup(*size
, (1 << nvbo
->page_shift
));
179 *align
= max((1 << nvbo
->page_shift
), *align
);
182 *size
= roundup(*size
, PAGE_SIZE
);
186 nouveau_bo_new(struct drm_device
*dev
, int size
, int align
,
187 uint32_t flags
, uint32_t tile_mode
, uint32_t tile_flags
,
189 struct nouveau_bo
**pnvbo
)
191 struct nouveau_drm
*drm
= nouveau_drm(dev
);
192 struct nouveau_bo
*nvbo
;
195 int type
= ttm_bo_type_device
;
200 lpg_shift
= drm
->client
.vm
->vmm
->lpg_shift
;
201 max_size
= INT_MAX
& ~((1 << lpg_shift
) - 1);
203 if (size
<= 0 || size
> max_size
) {
204 NV_WARN(drm
, "skipped size %x\n", (u32
)size
);
209 type
= ttm_bo_type_sg
;
211 nvbo
= kzalloc(sizeof(struct nouveau_bo
), GFP_KERNEL
);
214 INIT_LIST_HEAD(&nvbo
->head
);
215 INIT_LIST_HEAD(&nvbo
->entry
);
216 INIT_LIST_HEAD(&nvbo
->vma_list
);
217 nvbo
->tile_mode
= tile_mode
;
218 nvbo
->tile_flags
= tile_flags
;
219 nvbo
->bo
.bdev
= &drm
->ttm
.bdev
;
221 nvbo
->page_shift
= 12;
222 if (drm
->client
.vm
) {
223 if (!(flags
& TTM_PL_FLAG_TT
) && size
> 256 * 1024)
224 nvbo
->page_shift
= drm
->client
.vm
->vmm
->lpg_shift
;
227 nouveau_bo_fixup_align(nvbo
, flags
, &align
, &size
);
228 nvbo
->bo
.mem
.num_pages
= size
>> PAGE_SHIFT
;
229 nouveau_bo_placement_set(nvbo
, flags
, 0);
231 acc_size
= ttm_bo_dma_acc_size(&drm
->ttm
.bdev
, size
,
232 sizeof(struct nouveau_bo
));
234 ret
= ttm_bo_init(&drm
->ttm
.bdev
, &nvbo
->bo
, size
,
235 type
, &nvbo
->placement
,
236 align
>> PAGE_SHIFT
, false, NULL
, acc_size
, sg
,
239 /* ttm will call nouveau_bo_del_ttm if it fails.. */
248 set_placement_list(uint32_t *pl
, unsigned *n
, uint32_t type
, uint32_t flags
)
252 if (type
& TTM_PL_FLAG_VRAM
)
253 pl
[(*n
)++] = TTM_PL_FLAG_VRAM
| flags
;
254 if (type
& TTM_PL_FLAG_TT
)
255 pl
[(*n
)++] = TTM_PL_FLAG_TT
| flags
;
256 if (type
& TTM_PL_FLAG_SYSTEM
)
257 pl
[(*n
)++] = TTM_PL_FLAG_SYSTEM
| flags
;
261 set_placement_range(struct nouveau_bo
*nvbo
, uint32_t type
)
263 struct nouveau_drm
*drm
= nouveau_bdev(nvbo
->bo
.bdev
);
264 struct nouveau_fb
*pfb
= nouveau_fb(drm
->device
);
265 u32 vram_pages
= pfb
->ram
->size
>> PAGE_SHIFT
;
267 if ((nv_device(drm
->device
)->card_type
== NV_10
||
268 nv_device(drm
->device
)->card_type
== NV_11
) &&
269 nvbo
->tile_mode
&& (type
& TTM_PL_FLAG_VRAM
) &&
270 nvbo
->bo
.mem
.num_pages
< vram_pages
/ 4) {
272 * Make sure that the color and depth buffers are handled
273 * by independent memory controller units. Up to a 9x
274 * speed up when alpha-blending and depth-test are enabled
277 if (nvbo
->tile_flags
& NOUVEAU_GEM_TILE_ZETA
) {
278 nvbo
->placement
.fpfn
= vram_pages
/ 2;
279 nvbo
->placement
.lpfn
= ~0;
281 nvbo
->placement
.fpfn
= 0;
282 nvbo
->placement
.lpfn
= vram_pages
/ 2;
288 nouveau_bo_placement_set(struct nouveau_bo
*nvbo
, uint32_t type
, uint32_t busy
)
290 struct ttm_placement
*pl
= &nvbo
->placement
;
291 uint32_t flags
= TTM_PL_MASK_CACHING
|
292 (nvbo
->pin_refcnt
? TTM_PL_FLAG_NO_EVICT
: 0);
294 pl
->placement
= nvbo
->placements
;
295 set_placement_list(nvbo
->placements
, &pl
->num_placement
,
298 pl
->busy_placement
= nvbo
->busy_placements
;
299 set_placement_list(nvbo
->busy_placements
, &pl
->num_busy_placement
,
302 set_placement_range(nvbo
, type
);
306 nouveau_bo_pin(struct nouveau_bo
*nvbo
, uint32_t memtype
)
308 struct nouveau_drm
*drm
= nouveau_bdev(nvbo
->bo
.bdev
);
309 struct ttm_buffer_object
*bo
= &nvbo
->bo
;
312 ret
= ttm_bo_reserve(bo
, false, false, false, NULL
);
316 if (nvbo
->pin_refcnt
&& !(memtype
& (1 << bo
->mem
.mem_type
))) {
317 NV_ERROR(drm
, "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo
,
318 1 << bo
->mem
.mem_type
, memtype
);
323 if (nvbo
->pin_refcnt
++)
326 nouveau_bo_placement_set(nvbo
, memtype
, 0);
328 ret
= nouveau_bo_validate(nvbo
, false, false);
330 switch (bo
->mem
.mem_type
) {
332 drm
->gem
.vram_available
-= bo
->mem
.size
;
335 drm
->gem
.gart_available
-= bo
->mem
.size
;
342 ttm_bo_unreserve(bo
);
347 nouveau_bo_unpin(struct nouveau_bo
*nvbo
)
349 struct nouveau_drm
*drm
= nouveau_bdev(nvbo
->bo
.bdev
);
350 struct ttm_buffer_object
*bo
= &nvbo
->bo
;
353 ret
= ttm_bo_reserve(bo
, false, false, false, NULL
);
357 ref
= --nvbo
->pin_refcnt
;
358 WARN_ON_ONCE(ref
< 0);
362 nouveau_bo_placement_set(nvbo
, bo
->mem
.placement
, 0);
364 ret
= nouveau_bo_validate(nvbo
, false, false);
366 switch (bo
->mem
.mem_type
) {
368 drm
->gem
.vram_available
+= bo
->mem
.size
;
371 drm
->gem
.gart_available
+= bo
->mem
.size
;
379 ttm_bo_unreserve(bo
);
384 nouveau_bo_map(struct nouveau_bo
*nvbo
)
388 ret
= ttm_bo_reserve(&nvbo
->bo
, false, false, false, NULL
);
392 ret
= ttm_bo_kmap(&nvbo
->bo
, 0, nvbo
->bo
.mem
.num_pages
, &nvbo
->kmap
);
393 ttm_bo_unreserve(&nvbo
->bo
);
398 nouveau_bo_unmap(struct nouveau_bo
*nvbo
)
401 ttm_bo_kunmap(&nvbo
->kmap
);
405 nouveau_bo_validate(struct nouveau_bo
*nvbo
, bool interruptible
,
410 ret
= ttm_bo_validate(&nvbo
->bo
, &nvbo
->placement
,
411 interruptible
, no_wait_gpu
);
419 nouveau_bo_rd16(struct nouveau_bo
*nvbo
, unsigned index
)
422 u16
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
425 return ioread16_native((void __force __iomem
*)mem
);
431 nouveau_bo_wr16(struct nouveau_bo
*nvbo
, unsigned index
, u16 val
)
434 u16
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
437 iowrite16_native(val
, (void __force __iomem
*)mem
);
443 nouveau_bo_rd32(struct nouveau_bo
*nvbo
, unsigned index
)
446 u32
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
449 return ioread32_native((void __force __iomem
*)mem
);
455 nouveau_bo_wr32(struct nouveau_bo
*nvbo
, unsigned index
, u32 val
)
458 u32
*mem
= ttm_kmap_obj_virtual(&nvbo
->kmap
, &is_iomem
);
461 iowrite32_native(val
, (void __force __iomem
*)mem
);
466 static struct ttm_tt
*
467 nouveau_ttm_tt_create(struct ttm_bo_device
*bdev
, unsigned long size
,
468 uint32_t page_flags
, struct page
*dummy_read
)
471 struct nouveau_drm
*drm
= nouveau_bdev(bdev
);
472 struct drm_device
*dev
= drm
->dev
;
474 if (drm
->agp
.stat
== ENABLED
) {
475 return ttm_agp_tt_create(bdev
, dev
->agp
->bridge
, size
,
476 page_flags
, dummy_read
);
480 return nouveau_sgdma_create_ttm(bdev
, size
, page_flags
, dummy_read
);
484 nouveau_bo_invalidate_caches(struct ttm_bo_device
*bdev
, uint32_t flags
)
486 /* We'll do this from user space. */
491 nouveau_bo_init_mem_type(struct ttm_bo_device
*bdev
, uint32_t type
,
492 struct ttm_mem_type_manager
*man
)
494 struct nouveau_drm
*drm
= nouveau_bdev(bdev
);
498 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
;
499 man
->available_caching
= TTM_PL_MASK_CACHING
;
500 man
->default_caching
= TTM_PL_FLAG_CACHED
;
503 man
->flags
= TTM_MEMTYPE_FLAG_FIXED
|
504 TTM_MEMTYPE_FLAG_MAPPABLE
;
505 man
->available_caching
= TTM_PL_FLAG_UNCACHED
|
507 man
->default_caching
= TTM_PL_FLAG_WC
;
509 if (nv_device(drm
->device
)->card_type
>= NV_50
) {
510 /* Some BARs do not support being ioremapped WC */
511 if (nouveau_bar(drm
->device
)->iomap_uncached
) {
512 man
->available_caching
= TTM_PL_FLAG_UNCACHED
;
513 man
->default_caching
= TTM_PL_FLAG_UNCACHED
;
516 man
->func
= &nouveau_vram_manager
;
517 man
->io_reserve_fastpath
= false;
518 man
->use_io_reserve_lru
= true;
520 man
->func
= &ttm_bo_manager_func
;
524 if (nv_device(drm
->device
)->card_type
>= NV_50
)
525 man
->func
= &nouveau_gart_manager
;
527 if (drm
->agp
.stat
!= ENABLED
)
528 man
->func
= &nv04_gart_manager
;
530 man
->func
= &ttm_bo_manager_func
;
532 if (drm
->agp
.stat
== ENABLED
) {
533 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
;
534 man
->available_caching
= TTM_PL_FLAG_UNCACHED
|
536 man
->default_caching
= TTM_PL_FLAG_WC
;
538 man
->flags
= TTM_MEMTYPE_FLAG_MAPPABLE
|
539 TTM_MEMTYPE_FLAG_CMA
;
540 man
->available_caching
= TTM_PL_MASK_CACHING
;
541 man
->default_caching
= TTM_PL_FLAG_CACHED
;
552 nouveau_bo_evict_flags(struct ttm_buffer_object
*bo
, struct ttm_placement
*pl
)
554 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
556 switch (bo
->mem
.mem_type
) {
558 nouveau_bo_placement_set(nvbo
, TTM_PL_FLAG_TT
,
562 nouveau_bo_placement_set(nvbo
, TTM_PL_FLAG_SYSTEM
, 0);
566 *pl
= nvbo
->placement
;
571 nve0_bo_move_init(struct nouveau_channel
*chan
, u32 handle
)
573 int ret
= RING_SPACE(chan
, 2);
575 BEGIN_NVC0(chan
, NvSubCopy
, 0x0000, 1);
576 OUT_RING (chan
, handle
& 0x0000ffff);
583 nve0_bo_move_copy(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
584 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
586 struct nouveau_mem
*node
= old_mem
->mm_node
;
587 int ret
= RING_SPACE(chan
, 10);
589 BEGIN_NVC0(chan
, NvSubCopy
, 0x0400, 8);
590 OUT_RING (chan
, upper_32_bits(node
->vma
[0].offset
));
591 OUT_RING (chan
, lower_32_bits(node
->vma
[0].offset
));
592 OUT_RING (chan
, upper_32_bits(node
->vma
[1].offset
));
593 OUT_RING (chan
, lower_32_bits(node
->vma
[1].offset
));
594 OUT_RING (chan
, PAGE_SIZE
);
595 OUT_RING (chan
, PAGE_SIZE
);
596 OUT_RING (chan
, PAGE_SIZE
);
597 OUT_RING (chan
, new_mem
->num_pages
);
598 BEGIN_IMC0(chan
, NvSubCopy
, 0x0300, 0x0386);
604 nvc0_bo_move_init(struct nouveau_channel
*chan
, u32 handle
)
606 int ret
= RING_SPACE(chan
, 2);
608 BEGIN_NVC0(chan
, NvSubCopy
, 0x0000, 1);
609 OUT_RING (chan
, handle
);
615 nvc0_bo_move_copy(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
616 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
618 struct nouveau_mem
*node
= old_mem
->mm_node
;
619 u64 src_offset
= node
->vma
[0].offset
;
620 u64 dst_offset
= node
->vma
[1].offset
;
621 u32 page_count
= new_mem
->num_pages
;
624 page_count
= new_mem
->num_pages
;
626 int line_count
= (page_count
> 8191) ? 8191 : page_count
;
628 ret
= RING_SPACE(chan
, 11);
632 BEGIN_NVC0(chan
, NvSubCopy
, 0x030c, 8);
633 OUT_RING (chan
, upper_32_bits(src_offset
));
634 OUT_RING (chan
, lower_32_bits(src_offset
));
635 OUT_RING (chan
, upper_32_bits(dst_offset
));
636 OUT_RING (chan
, lower_32_bits(dst_offset
));
637 OUT_RING (chan
, PAGE_SIZE
);
638 OUT_RING (chan
, PAGE_SIZE
);
639 OUT_RING (chan
, PAGE_SIZE
);
640 OUT_RING (chan
, line_count
);
641 BEGIN_NVC0(chan
, NvSubCopy
, 0x0300, 1);
642 OUT_RING (chan
, 0x00000110);
644 page_count
-= line_count
;
645 src_offset
+= (PAGE_SIZE
* line_count
);
646 dst_offset
+= (PAGE_SIZE
* line_count
);
653 nvc0_bo_move_m2mf(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
654 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
656 struct nouveau_mem
*node
= old_mem
->mm_node
;
657 u64 src_offset
= node
->vma
[0].offset
;
658 u64 dst_offset
= node
->vma
[1].offset
;
659 u32 page_count
= new_mem
->num_pages
;
662 page_count
= new_mem
->num_pages
;
664 int line_count
= (page_count
> 2047) ? 2047 : page_count
;
666 ret
= RING_SPACE(chan
, 12);
670 BEGIN_NVC0(chan
, NvSubCopy
, 0x0238, 2);
671 OUT_RING (chan
, upper_32_bits(dst_offset
));
672 OUT_RING (chan
, lower_32_bits(dst_offset
));
673 BEGIN_NVC0(chan
, NvSubCopy
, 0x030c, 6);
674 OUT_RING (chan
, upper_32_bits(src_offset
));
675 OUT_RING (chan
, lower_32_bits(src_offset
));
676 OUT_RING (chan
, PAGE_SIZE
); /* src_pitch */
677 OUT_RING (chan
, PAGE_SIZE
); /* dst_pitch */
678 OUT_RING (chan
, PAGE_SIZE
); /* line_length */
679 OUT_RING (chan
, line_count
);
680 BEGIN_NVC0(chan
, NvSubCopy
, 0x0300, 1);
681 OUT_RING (chan
, 0x00100110);
683 page_count
-= line_count
;
684 src_offset
+= (PAGE_SIZE
* line_count
);
685 dst_offset
+= (PAGE_SIZE
* line_count
);
692 nva3_bo_move_copy(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
693 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
695 struct nouveau_mem
*node
= old_mem
->mm_node
;
696 u64 src_offset
= node
->vma
[0].offset
;
697 u64 dst_offset
= node
->vma
[1].offset
;
698 u32 page_count
= new_mem
->num_pages
;
701 page_count
= new_mem
->num_pages
;
703 int line_count
= (page_count
> 8191) ? 8191 : page_count
;
705 ret
= RING_SPACE(chan
, 11);
709 BEGIN_NV04(chan
, NvSubCopy
, 0x030c, 8);
710 OUT_RING (chan
, upper_32_bits(src_offset
));
711 OUT_RING (chan
, lower_32_bits(src_offset
));
712 OUT_RING (chan
, upper_32_bits(dst_offset
));
713 OUT_RING (chan
, lower_32_bits(dst_offset
));
714 OUT_RING (chan
, PAGE_SIZE
);
715 OUT_RING (chan
, PAGE_SIZE
);
716 OUT_RING (chan
, PAGE_SIZE
);
717 OUT_RING (chan
, line_count
);
718 BEGIN_NV04(chan
, NvSubCopy
, 0x0300, 1);
719 OUT_RING (chan
, 0x00000110);
721 page_count
-= line_count
;
722 src_offset
+= (PAGE_SIZE
* line_count
);
723 dst_offset
+= (PAGE_SIZE
* line_count
);
730 nv98_bo_move_exec(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
731 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
733 struct nouveau_mem
*node
= old_mem
->mm_node
;
734 int ret
= RING_SPACE(chan
, 7);
736 BEGIN_NV04(chan
, NvSubCopy
, 0x0320, 6);
737 OUT_RING (chan
, upper_32_bits(node
->vma
[0].offset
));
738 OUT_RING (chan
, lower_32_bits(node
->vma
[0].offset
));
739 OUT_RING (chan
, upper_32_bits(node
->vma
[1].offset
));
740 OUT_RING (chan
, lower_32_bits(node
->vma
[1].offset
));
741 OUT_RING (chan
, 0x00000000 /* COPY */);
742 OUT_RING (chan
, new_mem
->num_pages
<< PAGE_SHIFT
);
748 nv84_bo_move_exec(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
749 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
751 struct nouveau_mem
*node
= old_mem
->mm_node
;
752 int ret
= RING_SPACE(chan
, 7);
754 BEGIN_NV04(chan
, NvSubCopy
, 0x0304, 6);
755 OUT_RING (chan
, new_mem
->num_pages
<< PAGE_SHIFT
);
756 OUT_RING (chan
, upper_32_bits(node
->vma
[0].offset
));
757 OUT_RING (chan
, lower_32_bits(node
->vma
[0].offset
));
758 OUT_RING (chan
, upper_32_bits(node
->vma
[1].offset
));
759 OUT_RING (chan
, lower_32_bits(node
->vma
[1].offset
));
760 OUT_RING (chan
, 0x00000000 /* MODE_COPY, QUERY_NONE */);
766 nv50_bo_move_init(struct nouveau_channel
*chan
, u32 handle
)
768 int ret
= RING_SPACE(chan
, 6);
770 BEGIN_NV04(chan
, NvSubCopy
, 0x0000, 1);
771 OUT_RING (chan
, handle
);
772 BEGIN_NV04(chan
, NvSubCopy
, 0x0180, 3);
773 OUT_RING (chan
, NvNotify0
);
774 OUT_RING (chan
, NvDmaFB
);
775 OUT_RING (chan
, NvDmaFB
);
782 nv50_bo_move_m2mf(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
783 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
785 struct nouveau_mem
*node
= old_mem
->mm_node
;
786 u64 length
= (new_mem
->num_pages
<< PAGE_SHIFT
);
787 u64 src_offset
= node
->vma
[0].offset
;
788 u64 dst_offset
= node
->vma
[1].offset
;
789 int src_tiled
= !!node
->memtype
;
790 int dst_tiled
= !!((struct nouveau_mem
*)new_mem
->mm_node
)->memtype
;
794 u32 amount
, stride
, height
;
796 ret
= RING_SPACE(chan
, 18 + 6 * (src_tiled
+ dst_tiled
));
800 amount
= min(length
, (u64
)(4 * 1024 * 1024));
802 height
= amount
/ stride
;
805 BEGIN_NV04(chan
, NvSubCopy
, 0x0200, 7);
808 OUT_RING (chan
, stride
);
809 OUT_RING (chan
, height
);
814 BEGIN_NV04(chan
, NvSubCopy
, 0x0200, 1);
818 BEGIN_NV04(chan
, NvSubCopy
, 0x021c, 7);
821 OUT_RING (chan
, stride
);
822 OUT_RING (chan
, height
);
827 BEGIN_NV04(chan
, NvSubCopy
, 0x021c, 1);
831 BEGIN_NV04(chan
, NvSubCopy
, 0x0238, 2);
832 OUT_RING (chan
, upper_32_bits(src_offset
));
833 OUT_RING (chan
, upper_32_bits(dst_offset
));
834 BEGIN_NV04(chan
, NvSubCopy
, 0x030c, 8);
835 OUT_RING (chan
, lower_32_bits(src_offset
));
836 OUT_RING (chan
, lower_32_bits(dst_offset
));
837 OUT_RING (chan
, stride
);
838 OUT_RING (chan
, stride
);
839 OUT_RING (chan
, stride
);
840 OUT_RING (chan
, height
);
841 OUT_RING (chan
, 0x00000101);
842 OUT_RING (chan
, 0x00000000);
843 BEGIN_NV04(chan
, NvSubCopy
, NV_MEMORY_TO_MEMORY_FORMAT_NOP
, 1);
847 src_offset
+= amount
;
848 dst_offset
+= amount
;
855 nv04_bo_move_init(struct nouveau_channel
*chan
, u32 handle
)
857 int ret
= RING_SPACE(chan
, 4);
859 BEGIN_NV04(chan
, NvSubCopy
, 0x0000, 1);
860 OUT_RING (chan
, handle
);
861 BEGIN_NV04(chan
, NvSubCopy
, 0x0180, 1);
862 OUT_RING (chan
, NvNotify0
);
868 static inline uint32_t
869 nouveau_bo_mem_ctxdma(struct ttm_buffer_object
*bo
,
870 struct nouveau_channel
*chan
, struct ttm_mem_reg
*mem
)
872 if (mem
->mem_type
== TTM_PL_TT
)
878 nv04_bo_move_m2mf(struct nouveau_channel
*chan
, struct ttm_buffer_object
*bo
,
879 struct ttm_mem_reg
*old_mem
, struct ttm_mem_reg
*new_mem
)
881 u32 src_offset
= old_mem
->start
<< PAGE_SHIFT
;
882 u32 dst_offset
= new_mem
->start
<< PAGE_SHIFT
;
883 u32 page_count
= new_mem
->num_pages
;
886 ret
= RING_SPACE(chan
, 3);
890 BEGIN_NV04(chan
, NvSubCopy
, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE
, 2);
891 OUT_RING (chan
, nouveau_bo_mem_ctxdma(bo
, chan
, old_mem
));
892 OUT_RING (chan
, nouveau_bo_mem_ctxdma(bo
, chan
, new_mem
));
894 page_count
= new_mem
->num_pages
;
896 int line_count
= (page_count
> 2047) ? 2047 : page_count
;
898 ret
= RING_SPACE(chan
, 11);
902 BEGIN_NV04(chan
, NvSubCopy
,
903 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN
, 8);
904 OUT_RING (chan
, src_offset
);
905 OUT_RING (chan
, dst_offset
);
906 OUT_RING (chan
, PAGE_SIZE
); /* src_pitch */
907 OUT_RING (chan
, PAGE_SIZE
); /* dst_pitch */
908 OUT_RING (chan
, PAGE_SIZE
); /* line_length */
909 OUT_RING (chan
, line_count
);
910 OUT_RING (chan
, 0x00000101);
911 OUT_RING (chan
, 0x00000000);
912 BEGIN_NV04(chan
, NvSubCopy
, NV_MEMORY_TO_MEMORY_FORMAT_NOP
, 1);
915 page_count
-= line_count
;
916 src_offset
+= (PAGE_SIZE
* line_count
);
917 dst_offset
+= (PAGE_SIZE
* line_count
);
924 nouveau_bo_move_prep(struct nouveau_drm
*drm
, struct ttm_buffer_object
*bo
,
925 struct ttm_mem_reg
*mem
)
927 struct nouveau_mem
*old_node
= bo
->mem
.mm_node
;
928 struct nouveau_mem
*new_node
= mem
->mm_node
;
929 u64 size
= (u64
)mem
->num_pages
<< PAGE_SHIFT
;
932 ret
= nouveau_vm_get(drm
->client
.vm
, size
, old_node
->page_shift
,
933 NV_MEM_ACCESS_RW
, &old_node
->vma
[0]);
937 ret
= nouveau_vm_get(drm
->client
.vm
, size
, new_node
->page_shift
,
938 NV_MEM_ACCESS_RW
, &old_node
->vma
[1]);
940 nouveau_vm_put(&old_node
->vma
[0]);
944 nouveau_vm_map(&old_node
->vma
[0], old_node
);
945 nouveau_vm_map(&old_node
->vma
[1], new_node
);
950 nouveau_bo_move_m2mf(struct ttm_buffer_object
*bo
, int evict
, bool intr
,
951 bool no_wait_gpu
, struct ttm_mem_reg
*new_mem
)
953 struct nouveau_drm
*drm
= nouveau_bdev(bo
->bdev
);
954 struct nouveau_channel
*chan
= drm
->ttm
.chan
;
955 struct nouveau_fence
*fence
;
958 /* create temporary vmas for the transfer and attach them to the
959 * old nouveau_mem node, these will get cleaned up after ttm has
960 * destroyed the ttm_mem_reg
962 if (nv_device(drm
->device
)->card_type
>= NV_50
) {
963 ret
= nouveau_bo_move_prep(drm
, bo
, new_mem
);
968 mutex_lock_nested(&chan
->cli
->mutex
, SINGLE_DEPTH_NESTING
);
969 ret
= nouveau_fence_sync(bo
->sync_obj
, chan
);
971 ret
= drm
->ttm
.move(chan
, bo
, &bo
->mem
, new_mem
);
973 ret
= nouveau_fence_new(chan
, false, &fence
);
975 ret
= ttm_bo_move_accel_cleanup(bo
, fence
,
979 nouveau_fence_unref(&fence
);
983 mutex_unlock(&chan
->cli
->mutex
);
988 nouveau_bo_move_init(struct nouveau_drm
*drm
)
990 static const struct {
994 int (*exec
)(struct nouveau_channel
*,
995 struct ttm_buffer_object
*,
996 struct ttm_mem_reg
*, struct ttm_mem_reg
*);
997 int (*init
)(struct nouveau_channel
*, u32 handle
);
999 { "COPY", 4, 0xa0b5, nve0_bo_move_copy
, nve0_bo_move_init
},
1000 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy
, nvc0_bo_move_init
},
1001 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy
, nvc0_bo_move_init
},
1002 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy
, nvc0_bo_move_init
},
1003 { "COPY", 0, 0x85b5, nva3_bo_move_copy
, nv50_bo_move_init
},
1004 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec
, nv50_bo_move_init
},
1005 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf
, nvc0_bo_move_init
},
1006 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf
, nv50_bo_move_init
},
1007 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf
, nv04_bo_move_init
},
1009 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec
, nv50_bo_move_init
},
1010 }, *mthd
= _methods
;
1011 const char *name
= "CPU";
1015 struct nouveau_object
*object
;
1016 struct nouveau_channel
*chan
;
1017 u32 handle
= (mthd
->engine
<< 16) | mthd
->oclass
;
1022 chan
= drm
->channel
;
1026 ret
= nouveau_object_new(nv_object(drm
), chan
->handle
, handle
,
1027 mthd
->oclass
, NULL
, 0, &object
);
1029 ret
= mthd
->init(chan
, handle
);
1031 nouveau_object_del(nv_object(drm
),
1032 chan
->handle
, handle
);
1036 drm
->ttm
.move
= mthd
->exec
;
1037 drm
->ttm
.chan
= chan
;
1041 } while ((++mthd
)->exec
);
1043 NV_INFO(drm
, "MM: using %s for buffer copies\n", name
);
1047 nouveau_bo_move_flipd(struct ttm_buffer_object
*bo
, bool evict
, bool intr
,
1048 bool no_wait_gpu
, struct ttm_mem_reg
*new_mem
)
1050 u32 placement_memtype
= TTM_PL_FLAG_TT
| TTM_PL_MASK_CACHING
;
1051 struct ttm_placement placement
;
1052 struct ttm_mem_reg tmp_mem
;
1055 placement
.fpfn
= placement
.lpfn
= 0;
1056 placement
.num_placement
= placement
.num_busy_placement
= 1;
1057 placement
.placement
= placement
.busy_placement
= &placement_memtype
;
1060 tmp_mem
.mm_node
= NULL
;
1061 ret
= ttm_bo_mem_space(bo
, &placement
, &tmp_mem
, intr
, no_wait_gpu
);
1065 ret
= ttm_tt_bind(bo
->ttm
, &tmp_mem
);
1069 ret
= nouveau_bo_move_m2mf(bo
, true, intr
, no_wait_gpu
, &tmp_mem
);
1073 ret
= ttm_bo_move_ttm(bo
, true, no_wait_gpu
, new_mem
);
1075 ttm_bo_mem_put(bo
, &tmp_mem
);
1080 nouveau_bo_move_flips(struct ttm_buffer_object
*bo
, bool evict
, bool intr
,
1081 bool no_wait_gpu
, struct ttm_mem_reg
*new_mem
)
1083 u32 placement_memtype
= TTM_PL_FLAG_TT
| TTM_PL_MASK_CACHING
;
1084 struct ttm_placement placement
;
1085 struct ttm_mem_reg tmp_mem
;
1088 placement
.fpfn
= placement
.lpfn
= 0;
1089 placement
.num_placement
= placement
.num_busy_placement
= 1;
1090 placement
.placement
= placement
.busy_placement
= &placement_memtype
;
1093 tmp_mem
.mm_node
= NULL
;
1094 ret
= ttm_bo_mem_space(bo
, &placement
, &tmp_mem
, intr
, no_wait_gpu
);
1098 ret
= ttm_bo_move_ttm(bo
, true, no_wait_gpu
, &tmp_mem
);
1102 ret
= nouveau_bo_move_m2mf(bo
, true, intr
, no_wait_gpu
, new_mem
);
1107 ttm_bo_mem_put(bo
, &tmp_mem
);
1112 nouveau_bo_move_ntfy(struct ttm_buffer_object
*bo
, struct ttm_mem_reg
*new_mem
)
1114 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
1115 struct nouveau_vma
*vma
;
1117 /* ttm can now (stupidly) pass the driver bos it didn't create... */
1118 if (bo
->destroy
!= nouveau_bo_del_ttm
)
1121 list_for_each_entry(vma
, &nvbo
->vma_list
, head
) {
1122 if (new_mem
&& new_mem
->mem_type
!= TTM_PL_SYSTEM
&&
1123 (new_mem
->mem_type
== TTM_PL_VRAM
||
1124 nvbo
->page_shift
!= vma
->vm
->vmm
->lpg_shift
)) {
1125 nouveau_vm_map(vma
, new_mem
->mm_node
);
1127 nouveau_vm_unmap(vma
);
1133 nouveau_bo_vm_bind(struct ttm_buffer_object
*bo
, struct ttm_mem_reg
*new_mem
,
1134 struct nouveau_drm_tile
**new_tile
)
1136 struct nouveau_drm
*drm
= nouveau_bdev(bo
->bdev
);
1137 struct drm_device
*dev
= drm
->dev
;
1138 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
1139 u64 offset
= new_mem
->start
<< PAGE_SHIFT
;
1142 if (new_mem
->mem_type
!= TTM_PL_VRAM
)
1145 if (nv_device(drm
->device
)->card_type
>= NV_10
) {
1146 *new_tile
= nv10_bo_set_tiling(dev
, offset
, new_mem
->size
,
1155 nouveau_bo_vm_cleanup(struct ttm_buffer_object
*bo
,
1156 struct nouveau_drm_tile
*new_tile
,
1157 struct nouveau_drm_tile
**old_tile
)
1159 struct nouveau_drm
*drm
= nouveau_bdev(bo
->bdev
);
1160 struct drm_device
*dev
= drm
->dev
;
1162 nv10_bo_put_tile_region(dev
, *old_tile
, bo
->sync_obj
);
1163 *old_tile
= new_tile
;
1167 nouveau_bo_move(struct ttm_buffer_object
*bo
, bool evict
, bool intr
,
1168 bool no_wait_gpu
, struct ttm_mem_reg
*new_mem
)
1170 struct nouveau_drm
*drm
= nouveau_bdev(bo
->bdev
);
1171 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
1172 struct ttm_mem_reg
*old_mem
= &bo
->mem
;
1173 struct nouveau_drm_tile
*new_tile
= NULL
;
1176 if (nv_device(drm
->device
)->card_type
< NV_50
) {
1177 ret
= nouveau_bo_vm_bind(bo
, new_mem
, &new_tile
);
1183 if (old_mem
->mem_type
== TTM_PL_SYSTEM
&& !bo
->ttm
) {
1184 BUG_ON(bo
->mem
.mm_node
!= NULL
);
1186 new_mem
->mm_node
= NULL
;
1190 /* Hardware assisted copy. */
1191 if (drm
->ttm
.move
) {
1192 if (new_mem
->mem_type
== TTM_PL_SYSTEM
)
1193 ret
= nouveau_bo_move_flipd(bo
, evict
, intr
,
1194 no_wait_gpu
, new_mem
);
1195 else if (old_mem
->mem_type
== TTM_PL_SYSTEM
)
1196 ret
= nouveau_bo_move_flips(bo
, evict
, intr
,
1197 no_wait_gpu
, new_mem
);
1199 ret
= nouveau_bo_move_m2mf(bo
, evict
, intr
,
1200 no_wait_gpu
, new_mem
);
1205 /* Fallback to software copy. */
1206 spin_lock(&bo
->bdev
->fence_lock
);
1207 ret
= ttm_bo_wait(bo
, true, intr
, no_wait_gpu
);
1208 spin_unlock(&bo
->bdev
->fence_lock
);
1210 ret
= ttm_bo_move_memcpy(bo
, evict
, no_wait_gpu
, new_mem
);
1213 if (nv_device(drm
->device
)->card_type
< NV_50
) {
1215 nouveau_bo_vm_cleanup(bo
, NULL
, &new_tile
);
1217 nouveau_bo_vm_cleanup(bo
, new_tile
, &nvbo
->tile
);
1224 nouveau_bo_verify_access(struct ttm_buffer_object
*bo
, struct file
*filp
)
1226 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
1228 return drm_vma_node_verify_access(&nvbo
->gem
.vma_node
, filp
);
1232 nouveau_ttm_io_mem_reserve(struct ttm_bo_device
*bdev
, struct ttm_mem_reg
*mem
)
1234 struct ttm_mem_type_manager
*man
= &bdev
->man
[mem
->mem_type
];
1235 struct nouveau_drm
*drm
= nouveau_bdev(bdev
);
1236 struct nouveau_mem
*node
= mem
->mm_node
;
1237 struct drm_device
*dev
= drm
->dev
;
1240 mem
->bus
.addr
= NULL
;
1241 mem
->bus
.offset
= 0;
1242 mem
->bus
.size
= mem
->num_pages
<< PAGE_SHIFT
;
1244 mem
->bus
.is_iomem
= false;
1245 if (!(man
->flags
& TTM_MEMTYPE_FLAG_MAPPABLE
))
1247 switch (mem
->mem_type
) {
1253 if (drm
->agp
.stat
== ENABLED
) {
1254 mem
->bus
.offset
= mem
->start
<< PAGE_SHIFT
;
1255 mem
->bus
.base
= drm
->agp
.base
;
1256 mem
->bus
.is_iomem
= !dev
->agp
->cant_use_aperture
;
1259 if (nv_device(drm
->device
)->card_type
< NV_50
|| !node
->memtype
)
1262 /* fallthrough, tiled memory */
1264 mem
->bus
.offset
= mem
->start
<< PAGE_SHIFT
;
1265 mem
->bus
.base
= nv_device_resource_start(nv_device(drm
->device
), 1);
1266 mem
->bus
.is_iomem
= true;
1267 if (nv_device(drm
->device
)->card_type
>= NV_50
) {
1268 struct nouveau_bar
*bar
= nouveau_bar(drm
->device
);
1270 ret
= bar
->umap(bar
, node
, NV_MEM_ACCESS_RW
,
1275 mem
->bus
.offset
= node
->bar_vma
.offset
;
1285 nouveau_ttm_io_mem_free(struct ttm_bo_device
*bdev
, struct ttm_mem_reg
*mem
)
1287 struct nouveau_drm
*drm
= nouveau_bdev(bdev
);
1288 struct nouveau_bar
*bar
= nouveau_bar(drm
->device
);
1289 struct nouveau_mem
*node
= mem
->mm_node
;
1291 if (!node
->bar_vma
.node
)
1294 bar
->unmap(bar
, &node
->bar_vma
);
1298 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object
*bo
)
1300 struct nouveau_drm
*drm
= nouveau_bdev(bo
->bdev
);
1301 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
1302 struct nouveau_device
*device
= nv_device(drm
->device
);
1303 u32 mappable
= nv_device_resource_len(device
, 1) >> PAGE_SHIFT
;
1306 /* as long as the bo isn't in vram, and isn't tiled, we've got
1307 * nothing to do here.
1309 if (bo
->mem
.mem_type
!= TTM_PL_VRAM
) {
1310 if (nv_device(drm
->device
)->card_type
< NV_50
||
1311 !nouveau_bo_tile_layout(nvbo
))
1314 if (bo
->mem
.mem_type
== TTM_PL_SYSTEM
) {
1315 nouveau_bo_placement_set(nvbo
, TTM_PL_TT
, 0);
1317 ret
= nouveau_bo_validate(nvbo
, false, false);
1324 /* make sure bo is in mappable vram */
1325 if (nv_device(drm
->device
)->card_type
>= NV_50
||
1326 bo
->mem
.start
+ bo
->mem
.num_pages
< mappable
)
1330 nvbo
->placement
.fpfn
= 0;
1331 nvbo
->placement
.lpfn
= mappable
;
1332 nouveau_bo_placement_set(nvbo
, TTM_PL_FLAG_VRAM
, 0);
1333 return nouveau_bo_validate(nvbo
, false, false);
1337 nouveau_ttm_tt_populate(struct ttm_tt
*ttm
)
1339 struct ttm_dma_tt
*ttm_dma
= (void *)ttm
;
1340 struct nouveau_drm
*drm
;
1341 struct nouveau_device
*device
;
1342 struct drm_device
*dev
;
1343 struct device
*pdev
;
1346 bool slave
= !!(ttm
->page_flags
& TTM_PAGE_FLAG_SG
);
1348 if (ttm
->state
!= tt_unpopulated
)
1351 if (slave
&& ttm
->sg
) {
1352 /* make userspace faulting work */
1353 drm_prime_sg_to_page_addr_arrays(ttm
->sg
, ttm
->pages
,
1354 ttm_dma
->dma_address
, ttm
->num_pages
);
1355 ttm
->state
= tt_unbound
;
1359 drm
= nouveau_bdev(ttm
->bdev
);
1360 device
= nv_device(drm
->device
);
1362 pdev
= nv_device_base(device
);
1365 if (drm
->agp
.stat
== ENABLED
) {
1366 return ttm_agp_tt_populate(ttm
);
1370 #ifdef CONFIG_SWIOTLB
1371 if (swiotlb_nr_tbl()) {
1372 return ttm_dma_populate((void *)ttm
, dev
->dev
);
1376 r
= ttm_pool_populate(ttm
);
1381 for (i
= 0; i
< ttm
->num_pages
; i
++) {
1384 addr
= dma_map_page(pdev
, ttm
->pages
[i
], 0, PAGE_SIZE
,
1387 if (dma_mapping_error(pdev
, addr
)) {
1389 dma_unmap_page(pdev
, ttm_dma
->dma_address
[i
],
1390 PAGE_SIZE
, DMA_BIDIRECTIONAL
);
1391 ttm_dma
->dma_address
[i
] = 0;
1393 ttm_pool_unpopulate(ttm
);
1397 ttm_dma
->dma_address
[i
] = addr
;
1403 nouveau_ttm_tt_unpopulate(struct ttm_tt
*ttm
)
1405 struct ttm_dma_tt
*ttm_dma
= (void *)ttm
;
1406 struct nouveau_drm
*drm
;
1407 struct nouveau_device
*device
;
1408 struct drm_device
*dev
;
1409 struct device
*pdev
;
1411 bool slave
= !!(ttm
->page_flags
& TTM_PAGE_FLAG_SG
);
1416 drm
= nouveau_bdev(ttm
->bdev
);
1417 device
= nv_device(drm
->device
);
1419 pdev
= nv_device_base(device
);
1422 if (drm
->agp
.stat
== ENABLED
) {
1423 ttm_agp_tt_unpopulate(ttm
);
1428 #ifdef CONFIG_SWIOTLB
1429 if (swiotlb_nr_tbl()) {
1430 ttm_dma_unpopulate((void *)ttm
, dev
->dev
);
1435 for (i
= 0; i
< ttm
->num_pages
; i
++) {
1436 if (ttm_dma
->dma_address
[i
]) {
1437 dma_unmap_page(pdev
, ttm_dma
->dma_address
[i
], PAGE_SIZE
,
1442 ttm_pool_unpopulate(ttm
);
1446 nouveau_bo_fence(struct nouveau_bo
*nvbo
, struct nouveau_fence
*fence
)
1448 struct nouveau_fence
*new_fence
= nouveau_fence_ref(fence
);
1449 struct nouveau_fence
*old_fence
= NULL
;
1451 spin_lock(&nvbo
->bo
.bdev
->fence_lock
);
1452 old_fence
= nvbo
->bo
.sync_obj
;
1453 nvbo
->bo
.sync_obj
= new_fence
;
1454 spin_unlock(&nvbo
->bo
.bdev
->fence_lock
);
1456 nouveau_fence_unref(&old_fence
);
1460 nouveau_bo_fence_unref(void **sync_obj
)
1462 nouveau_fence_unref((struct nouveau_fence
**)sync_obj
);
1466 nouveau_bo_fence_ref(void *sync_obj
)
1468 return nouveau_fence_ref(sync_obj
);
1472 nouveau_bo_fence_signalled(void *sync_obj
)
1474 return nouveau_fence_done(sync_obj
);
1478 nouveau_bo_fence_wait(void *sync_obj
, bool lazy
, bool intr
)
1480 return nouveau_fence_wait(sync_obj
, lazy
, intr
);
1484 nouveau_bo_fence_flush(void *sync_obj
)
1489 struct ttm_bo_driver nouveau_bo_driver
= {
1490 .ttm_tt_create
= &nouveau_ttm_tt_create
,
1491 .ttm_tt_populate
= &nouveau_ttm_tt_populate
,
1492 .ttm_tt_unpopulate
= &nouveau_ttm_tt_unpopulate
,
1493 .invalidate_caches
= nouveau_bo_invalidate_caches
,
1494 .init_mem_type
= nouveau_bo_init_mem_type
,
1495 .evict_flags
= nouveau_bo_evict_flags
,
1496 .move_notify
= nouveau_bo_move_ntfy
,
1497 .move
= nouveau_bo_move
,
1498 .verify_access
= nouveau_bo_verify_access
,
1499 .sync_obj_signaled
= nouveau_bo_fence_signalled
,
1500 .sync_obj_wait
= nouveau_bo_fence_wait
,
1501 .sync_obj_flush
= nouveau_bo_fence_flush
,
1502 .sync_obj_unref
= nouveau_bo_fence_unref
,
1503 .sync_obj_ref
= nouveau_bo_fence_ref
,
1504 .fault_reserve_notify
= &nouveau_ttm_fault_reserve_notify
,
1505 .io_mem_reserve
= &nouveau_ttm_io_mem_reserve
,
1506 .io_mem_free
= &nouveau_ttm_io_mem_free
,
1509 struct nouveau_vma
*
1510 nouveau_bo_vma_find(struct nouveau_bo
*nvbo
, struct nouveau_vm
*vm
)
1512 struct nouveau_vma
*vma
;
1513 list_for_each_entry(vma
, &nvbo
->vma_list
, head
) {
1522 nouveau_bo_vma_add(struct nouveau_bo
*nvbo
, struct nouveau_vm
*vm
,
1523 struct nouveau_vma
*vma
)
1525 const u32 size
= nvbo
->bo
.mem
.num_pages
<< PAGE_SHIFT
;
1528 ret
= nouveau_vm_get(vm
, size
, nvbo
->page_shift
,
1529 NV_MEM_ACCESS_RW
, vma
);
1533 if ( nvbo
->bo
.mem
.mem_type
!= TTM_PL_SYSTEM
&&
1534 (nvbo
->bo
.mem
.mem_type
== TTM_PL_VRAM
||
1535 nvbo
->page_shift
!= vma
->vm
->vmm
->lpg_shift
))
1536 nouveau_vm_map(vma
, nvbo
->bo
.mem
.mm_node
);
1538 list_add_tail(&vma
->head
, &nvbo
->vma_list
);
1544 nouveau_bo_vma_del(struct nouveau_bo
*nvbo
, struct nouveau_vma
*vma
)
1547 if (nvbo
->bo
.mem
.mem_type
!= TTM_PL_SYSTEM
)
1548 nouveau_vm_unmap(vma
);
1549 nouveau_vm_put(vma
);
1550 list_del(&vma
->head
);