drivers/gpu/drm/nouveau/nouveau_chan.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <nvif/os.h>
  26 #include <nvif/class.h>
  27 #include <nvif/cl0002.h>
  28 #include <nvif/cl006b.h>
  29 #include <nvif/cl506f.h>
  30 #include <nvif/cl906f.h>
  31 #include <nvif/cla06f.h>
  32 #include <nvif/ioctl.h>
  33
  34 /*XXX*/
  35 #include <core/client.h>
  36
  37 #include "nouveau_drm.h"
  38 #include "nouveau_dma.h"
  39 #include "nouveau_bo.h"
  40 #include "nouveau_chan.h"
  41 #include "nouveau_fence.h"
  42 #include "nouveau_abi16.h"
  43
  44 MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM");
  45 int nouveau_vram_pushbuf;
  46 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
  47
  48 int
  49 nouveau_channel_idle(struct nouveau_channel *chan)
  50 {
  51         if (likely(chan && chan->fence)) {
  52                 struct nouveau_cli *cli = (void *)chan->user.client;
  53                 struct nouveau_fence *fence = NULL;
  54                 int ret;
  55
  56                 ret = nouveau_fence_new(chan, false, &fence);
  57                 if (!ret) {
  58                         ret = nouveau_fence_wait(fence, false, false);
  59                         nouveau_fence_unref(&fence);
  60                 }
  61
  62                 if (ret) {
  63                         NV_PRINTK(err, cli, "failed to idle channel %d [%s]\n",
  64                                   chan->chid, nvxx_client(&cli->base)->name);
  65                         return ret;
  66                 }
  67         }
  68         return 0;
  69 }
  70
  71 void
  72 nouveau_channel_del(struct nouveau_channel **pchan)
  73 {
  74         struct nouveau_channel *chan = *pchan;
  75         if (chan) {
  76                 if (chan->fence)
  77                         nouveau_fence(chan->drm)->context_del(chan);
  78                 nvif_object_fini(&chan->nvsw);
  79                 nvif_object_fini(&chan->gart);
  80                 nvif_object_fini(&chan->vram);
  81                 nvif_object_fini(&chan->user);
  82                 nvif_object_fini(&chan->push.ctxdma);
  83                 nouveau_bo_vma_del(chan->push.buffer, &chan->push.vma);
  84                 nouveau_bo_unmap(chan->push.buffer);
  85                 if (chan->push.buffer && chan->push.buffer->pin_refcnt)
  86                         nouveau_bo_unpin(chan->push.buffer);
  87                 nouveau_bo_ref(NULL, &chan->push.buffer);
  88                 kfree(chan);
  89         }
  90         *pchan = NULL;
  91 }
  92
  93 static int
  94 nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
  95                      u32 size, struct nouveau_channel **pchan)
  96 {
  97         struct nouveau_cli *cli = (void *)device->object.client;
  98         struct nvkm_mmu *mmu = nvxx_mmu(device);
  99         struct nv_dma_v0 args = {};
 100         struct nouveau_channel *chan;
 101         u32 target;
 102         int ret;
 103
 104         chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL);
 105         if (!chan)
 106                 return -ENOMEM;
 107
 108         chan->device = device;
 109         chan->drm = drm;
 110
 111         /* allocate memory for dma push buffer */
 112         target = TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED;
 113         if (nouveau_vram_pushbuf)
 114                 target = TTM_PL_FLAG_VRAM;
 115
 116         ret = nouveau_bo_new(drm->dev, size, 0, target, 0, 0, NULL, NULL,
 117                             &chan->push.buffer);
 118         if (ret == 0) {
 119                 ret = nouveau_bo_pin(chan->push.buffer, target, false);
 120                 if (ret == 0)
 121                         ret = nouveau_bo_map(chan->push.buffer);
 122         }
 123
 124         if (ret) {
 125                 nouveau_channel_del(pchan);
 126                 return ret;
 127         }
 128
 129         /* create dma object covering the *entire* memory space that the
 130          * pushbuf lives in, this is because the GEM code requires that
 131          * we be able to call out to other (indirect) push buffers
 132          */
 133         chan->push.vma.offset = chan->push.buffer->bo.offset;
 134
 135         if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
 136                 ret = nouveau_bo_vma_add(chan->push.buffer, cli->vm,
 137                                         &chan->push.vma);
 138                 if (ret) {
 139                         nouveau_channel_del(pchan);
 140                         return ret;
 141                 }
 142
 143                 args.target = NV_DMA_V0_TARGET_VM;
 144                 args.access = NV_DMA_V0_ACCESS_VM;
 145                 args.start = 0;
 146                 args.limit = cli->vm->mmu->limit - 1;
 147         } else
 148         if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) {
 149                 if (device->info.family == NV_DEVICE_INFO_V0_TNT) {
 150                         /* nv04 vram pushbuf hack, retarget to its location in
 151                          * the framebuffer bar rather than direct vram access..
 152                          * nfi why this exists, it came from the -nv ddx.
 153                          */
 154                         args.target = NV_DMA_V0_TARGET_PCI;
 155                         args.access = NV_DMA_V0_ACCESS_RDWR;
 156                         args.start = nvxx_device(device)->func->
 157                                 resource_addr(nvxx_device(device), 1);
 158                         args.limit = args.start + device->info.ram_user - 1;
 159                 } else {
 160                         args.target = NV_DMA_V0_TARGET_VRAM;
 161                         args.access = NV_DMA_V0_ACCESS_RDWR;
 162                         args.start = 0;
 163                         args.limit = device->info.ram_user - 1;
 164                 }
 165         } else {
 166                 if (chan->drm->agp.bridge) {
 167                         args.target = NV_DMA_V0_TARGET_AGP;
 168                         args.access = NV_DMA_V0_ACCESS_RDWR;
 169                         args.start = chan->drm->agp.base;
 170                         args.limit = chan->drm->agp.base +
 171                                      chan->drm->agp.size - 1;
 172                 } else {
 173                         args.target = NV_DMA_V0_TARGET_VM;
 174                         args.access = NV_DMA_V0_ACCESS_RDWR;
 175                         args.start = 0;
 176                         args.limit = mmu->limit - 1;
 177                 }
 178         }
 179
 180         ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY,
 181                                &args, sizeof(args), &chan->push.ctxdma);
 182         if (ret) {
 183                 nouveau_channel_del(pchan);
 184                 return ret;
 185         }
 186
 187         return 0;
 188 }
 189
 190 static int
 191 nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device,
 192                     u32 engine, struct nouveau_channel **pchan)
 193 {
 194         static const u16 oclasses[] = { MAXWELL_CHANNEL_GPFIFO_A,
 195                                         KEPLER_CHANNEL_GPFIFO_A,
 196                                         FERMI_CHANNEL_GPFIFO,
 197                                         G82_CHANNEL_GPFIFO,
 198                                         NV50_CHANNEL_GPFIFO,
 199                                         0 };
 200         const u16 *oclass = oclasses;
 201         union {
 202                 struct nv50_channel_gpfifo_v0 nv50;
 203                 struct fermi_channel_gpfifo_v0 fermi;
 204                 struct kepler_channel_gpfifo_a_v0 kepler;
 205         } args;
 206         struct nouveau_channel *chan;
 207         u32 size;
 208         int ret;
 209
 210         /* allocate dma push buffer */
 211         ret = nouveau_channel_prep(drm, device, 0x12000, &chan);
 212         *pchan = chan;
 213         if (ret)
 214                 return ret;
 215
 216         /* create channel object */
 217         do {
 218                 if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) {
 219                         args.kepler.version = 0;
 220                         args.kepler.engine  = engine;
 221                         args.kepler.ilength = 0x02000;
 222                         args.kepler.ioffset = 0x10000 + chan->push.vma.offset;
 223                         args.kepler.vm = 0;
 224                         size = sizeof(args.kepler);
 225                 } else
 226                 if (oclass[0] >= FERMI_CHANNEL_GPFIFO) {
 227                         args.fermi.version = 0;
 228                         args.fermi.ilength = 0x02000;
 229                         args.fermi.ioffset = 0x10000 + chan->push.vma.offset;
 230                         args.fermi.vm = 0;
 231                         size = sizeof(args.fermi);
 232                 } else {
 233                         args.nv50.version = 0;
 234                         args.nv50.ilength = 0x02000;
 235                         args.nv50.ioffset = 0x10000 + chan->push.vma.offset;
 236                         args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma);
 237                         args.nv50.vm = 0;
 238                         size = sizeof(args.nv50);
 239                 }
 240
 241                 ret = nvif_object_init(&device->object, 0, *oclass++,
 242                                        &args, size, &chan->user);
 243                 if (ret == 0) {
 244                         if (chan->user.oclass >= KEPLER_CHANNEL_GPFIFO_A)
 245                                 chan->chid = args.kepler.chid;
 246                         else
 247                         if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO)
 248                                 chan->chid = args.fermi.chid;
 249                         else
 250                                 chan->chid = args.nv50.chid;
 251                         return ret;
 252                 }
 253         } while (*oclass);
 254
 255         nouveau_channel_del(pchan);
 256         return ret;
 257 }
 258
 259 static int
 260 nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device,
 261                     struct nouveau_channel **pchan)
 262 {
 263         static const u16 oclasses[] = { NV40_CHANNEL_DMA,
 264                                         NV17_CHANNEL_DMA,
 265                                         NV10_CHANNEL_DMA,
 266                                         NV03_CHANNEL_DMA,
 267                                         0 };
 268         const u16 *oclass = oclasses;
 269         struct nv03_channel_dma_v0 args;
 270         struct nouveau_channel *chan;
 271         int ret;
 272
 273         /* allocate dma push buffer */
 274         ret = nouveau_channel_prep(drm, device, 0x10000, &chan);
 275         *pchan = chan;
 276         if (ret)
 277                 return ret;
 278
 279         /* create channel object */
 280         args.version = 0;
 281         args.pushbuf = nvif_handle(&chan->push.ctxdma);
 282         args.offset = chan->push.vma.offset;
 283
 284         do {
 285                 ret = nvif_object_init(&device->object, 0, *oclass++,
 286                                        &args, sizeof(args), &chan->user);
 287                 if (ret == 0) {
 288                         chan->chid = args.chid;
 289                         return ret;
 290                 }
 291         } while (ret && *oclass);
 292
 293         nouveau_channel_del(pchan);
 294         return ret;
 295 }
 296
 297 static int
 298 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
 299 {
 300         struct nvif_device *device = chan->device;
 301         struct nouveau_cli *cli = (void *)chan->user.client;
 302         struct nvkm_mmu *mmu = nvxx_mmu(device);
 303         struct nv_dma_v0 args = {};
 304         int ret, i;
 305
 306         nvif_object_map(&chan->user);
 307
 308         /* allocate dma objects to cover all allowed vram, and gart */
 309         if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
 310                 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
 311                         args.target = NV_DMA_V0_TARGET_VM;
 312                         args.access = NV_DMA_V0_ACCESS_VM;
 313                         args.start = 0;
 314                         args.limit = cli->vm->mmu->limit - 1;
 315                 } else {
 316                         args.target = NV_DMA_V0_TARGET_VRAM;
 317                         args.access = NV_DMA_V0_ACCESS_RDWR;
 318                         args.start = 0;
 319                         args.limit = device->info.ram_user - 1;
 320                 }
 321
 322                 ret = nvif_object_init(&chan->user, vram, NV_DMA_IN_MEMORY,
 323                                        &args, sizeof(args), &chan->vram);
 324                 if (ret)
 325                         return ret;
 326
 327                 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
 328                         args.target = NV_DMA_V0_TARGET_VM;
 329                         args.access = NV_DMA_V0_ACCESS_VM;
 330                         args.start = 0;
 331                         args.limit = cli->vm->mmu->limit - 1;
 332                 } else
 333                 if (chan->drm->agp.bridge) {
 334                         args.target = NV_DMA_V0_TARGET_AGP;
 335                         args.access = NV_DMA_V0_ACCESS_RDWR;
 336                         args.start = chan->drm->agp.base;
 337                         args.limit = chan->drm->agp.base +
 338                                      chan->drm->agp.size - 1;
 339                 } else {
 340                         args.target = NV_DMA_V0_TARGET_VM;
 341                         args.access = NV_DMA_V0_ACCESS_RDWR;
 342                         args.start = 0;
 343                         args.limit = mmu->limit - 1;
 344                 }
 345
 346                 ret = nvif_object_init(&chan->user, gart, NV_DMA_IN_MEMORY,
 347                                        &args, sizeof(args), &chan->gart);
 348                 if (ret)
 349                         return ret;
 350         }
 351
 352         /* initialise dma tracking parameters */
 353         switch (chan->user.oclass & 0x00ff) {
 354         case 0x006b:
 355         case 0x006e:
 356                 chan->user_put = 0x40;
 357                 chan->user_get = 0x44;
 358                 chan->dma.max = (0x10000 / 4) - 2;
 359                 break;
 360         default:
 361                 chan->user_put = 0x40;
 362                 chan->user_get = 0x44;
 363                 chan->user_get_hi = 0x60;
 364                 chan->dma.ib_base =  0x10000 / 4;
 365                 chan->dma.ib_max  = (0x02000 / 8) - 1;
 366                 chan->dma.ib_put  = 0;
 367                 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
 368                 chan->dma.max = chan->dma.ib_base;
 369                 break;
 370         }
 371
 372         chan->dma.put = 0;
 373         chan->dma.cur = chan->dma.put;
 374         chan->dma.free = chan->dma.max - chan->dma.cur;
 375
 376         ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
 377         if (ret)
 378                 return ret;
 379
 380         for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
 381                 OUT_RING(chan, 0x00000000);
 382
 383         /* allocate software object class (used for fences on <= nv05) */
 384         if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) {
 385                 ret = nvif_object_init(&chan->user, 0x006e,
 386                                        NVIF_CLASS_SW_NV04,
 387                                        NULL, 0, &chan->nvsw);
 388                 if (ret)
 389                         return ret;
 390
 391                 ret = RING_SPACE(chan, 2);
 392                 if (ret)
 393                         return ret;
 394
 395                 BEGIN_NV04(chan, NvSubSw, 0x0000, 1);
 396                 OUT_RING  (chan, chan->nvsw.handle);
 397                 FIRE_RING (chan);
 398         }
 399
 400         /* initialise synchronisation */
 401         return nouveau_fence(chan->drm)->context_new(chan);
 402 }
 403
 404 int
 405 nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device,
 406                     u32 arg0, u32 arg1, struct nouveau_channel **pchan)
 407 {
 408         struct nouveau_cli *cli = (void *)device->object.client;
 409         bool super;
 410         int ret;
 411
 412         /* hack until fencenv50 is fixed, and agp access relaxed */
 413         super = cli->base.super;
 414         cli->base.super = true;
 415
 416         ret = nouveau_channel_ind(drm, device, arg0, pchan);
 417         if (ret) {
 418                 NV_PRINTK(dbg, cli, "ib channel create, %d\n", ret);
 419                 ret = nouveau_channel_dma(drm, device, pchan);
 420                 if (ret) {
 421                         NV_PRINTK(dbg, cli, "dma channel create, %d\n", ret);
 422                         goto done;
 423                 }
 424         }
 425
 426         ret = nouveau_channel_init(*pchan, arg0, arg1);
 427         if (ret) {
 428                 NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret);
 429                 nouveau_channel_del(pchan);
 430         }
 431
 432 done:
 433         cli->base.super = super;
 434         return ret;
 435 }