2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <nvif/class.h>
27 #include <nvif/cl0002.h>
28 #include <nvif/cl006b.h>
29 #include <nvif/cl506f.h>
30 #include <nvif/cl906f.h>
31 #include <nvif/cla06f.h>
32 #include <nvif/ioctl.h>
35 #include <core/client.h>
37 #include "nouveau_drm.h"
38 #include "nouveau_dma.h"
39 #include "nouveau_bo.h"
40 #include "nouveau_chan.h"
41 #include "nouveau_fence.h"
42 #include "nouveau_abi16.h"
44 MODULE_PARM_DESC(vram_pushbuf
, "Create DMA push buffers in VRAM");
45 int nouveau_vram_pushbuf
;
46 module_param_named(vram_pushbuf
, nouveau_vram_pushbuf
, int, 0400);
49 nouveau_channel_idle(struct nouveau_channel
*chan
)
51 if (likely(chan
&& chan
->fence
)) {
52 struct nouveau_cli
*cli
= (void *)chan
->user
.client
;
53 struct nouveau_fence
*fence
= NULL
;
56 ret
= nouveau_fence_new(chan
, false, &fence
);
58 ret
= nouveau_fence_wait(fence
, false, false);
59 nouveau_fence_unref(&fence
);
63 NV_PRINTK(err
, cli
, "failed to idle channel %d [%s]\n",
64 chan
->chid
, nvxx_client(&cli
->base
)->name
);
72 nouveau_channel_del(struct nouveau_channel
**pchan
)
74 struct nouveau_channel
*chan
= *pchan
;
77 nouveau_fence(chan
->drm
)->context_del(chan
);
78 nvif_object_fini(&chan
->nvsw
);
79 nvif_object_fini(&chan
->gart
);
80 nvif_object_fini(&chan
->vram
);
81 nvif_object_fini(&chan
->user
);
82 nvif_object_fini(&chan
->push
.ctxdma
);
83 nouveau_bo_vma_del(chan
->push
.buffer
, &chan
->push
.vma
);
84 nouveau_bo_unmap(chan
->push
.buffer
);
85 if (chan
->push
.buffer
&& chan
->push
.buffer
->pin_refcnt
)
86 nouveau_bo_unpin(chan
->push
.buffer
);
87 nouveau_bo_ref(NULL
, &chan
->push
.buffer
);
94 nouveau_channel_prep(struct nouveau_drm
*drm
, struct nvif_device
*device
,
95 u32 size
, struct nouveau_channel
**pchan
)
97 struct nouveau_cli
*cli
= (void *)device
->object
.client
;
98 struct nvkm_mmu
*mmu
= nvxx_mmu(device
);
99 struct nv_dma_v0 args
= {};
100 struct nouveau_channel
*chan
;
104 chan
= *pchan
= kzalloc(sizeof(*chan
), GFP_KERNEL
);
108 chan
->device
= device
;
111 /* allocate memory for dma push buffer */
112 target
= TTM_PL_FLAG_TT
| TTM_PL_FLAG_UNCACHED
;
113 if (nouveau_vram_pushbuf
)
114 target
= TTM_PL_FLAG_VRAM
;
116 ret
= nouveau_bo_new(drm
->dev
, size
, 0, target
, 0, 0, NULL
, NULL
,
119 ret
= nouveau_bo_pin(chan
->push
.buffer
, target
, false);
121 ret
= nouveau_bo_map(chan
->push
.buffer
);
125 nouveau_channel_del(pchan
);
129 /* create dma object covering the *entire* memory space that the
130 * pushbuf lives in, this is because the GEM code requires that
131 * we be able to call out to other (indirect) push buffers
133 chan
->push
.vma
.offset
= chan
->push
.buffer
->bo
.offset
;
135 if (device
->info
.family
>= NV_DEVICE_INFO_V0_TESLA
) {
136 ret
= nouveau_bo_vma_add(chan
->push
.buffer
, cli
->vm
,
139 nouveau_channel_del(pchan
);
143 args
.target
= NV_DMA_V0_TARGET_VM
;
144 args
.access
= NV_DMA_V0_ACCESS_VM
;
146 args
.limit
= cli
->vm
->mmu
->limit
- 1;
148 if (chan
->push
.buffer
->bo
.mem
.mem_type
== TTM_PL_VRAM
) {
149 if (device
->info
.family
== NV_DEVICE_INFO_V0_TNT
) {
150 /* nv04 vram pushbuf hack, retarget to its location in
151 * the framebuffer bar rather than direct vram access..
152 * nfi why this exists, it came from the -nv ddx.
154 args
.target
= NV_DMA_V0_TARGET_PCI
;
155 args
.access
= NV_DMA_V0_ACCESS_RDWR
;
156 args
.start
= nvxx_device(device
)->func
->
157 resource_addr(nvxx_device(device
), 1);
158 args
.limit
= args
.start
+ device
->info
.ram_user
- 1;
160 args
.target
= NV_DMA_V0_TARGET_VRAM
;
161 args
.access
= NV_DMA_V0_ACCESS_RDWR
;
163 args
.limit
= device
->info
.ram_user
- 1;
166 if (chan
->drm
->agp
.bridge
) {
167 args
.target
= NV_DMA_V0_TARGET_AGP
;
168 args
.access
= NV_DMA_V0_ACCESS_RDWR
;
169 args
.start
= chan
->drm
->agp
.base
;
170 args
.limit
= chan
->drm
->agp
.base
+
171 chan
->drm
->agp
.size
- 1;
173 args
.target
= NV_DMA_V0_TARGET_VM
;
174 args
.access
= NV_DMA_V0_ACCESS_RDWR
;
176 args
.limit
= mmu
->limit
- 1;
180 ret
= nvif_object_init(&device
->object
, 0, NV_DMA_FROM_MEMORY
,
181 &args
, sizeof(args
), &chan
->push
.ctxdma
);
183 nouveau_channel_del(pchan
);
191 nouveau_channel_ind(struct nouveau_drm
*drm
, struct nvif_device
*device
,
192 u32 engine
, struct nouveau_channel
**pchan
)
194 static const u16 oclasses
[] = { MAXWELL_CHANNEL_GPFIFO_A
,
195 KEPLER_CHANNEL_GPFIFO_A
,
196 FERMI_CHANNEL_GPFIFO
,
200 const u16
*oclass
= oclasses
;
202 struct nv50_channel_gpfifo_v0 nv50
;
203 struct fermi_channel_gpfifo_v0 fermi
;
204 struct kepler_channel_gpfifo_a_v0 kepler
;
206 struct nouveau_channel
*chan
;
210 /* allocate dma push buffer */
211 ret
= nouveau_channel_prep(drm
, device
, 0x12000, &chan
);
216 /* create channel object */
218 if (oclass
[0] >= KEPLER_CHANNEL_GPFIFO_A
) {
219 args
.kepler
.version
= 0;
220 args
.kepler
.engine
= engine
;
221 args
.kepler
.ilength
= 0x02000;
222 args
.kepler
.ioffset
= 0x10000 + chan
->push
.vma
.offset
;
224 size
= sizeof(args
.kepler
);
226 if (oclass
[0] >= FERMI_CHANNEL_GPFIFO
) {
227 args
.fermi
.version
= 0;
228 args
.fermi
.ilength
= 0x02000;
229 args
.fermi
.ioffset
= 0x10000 + chan
->push
.vma
.offset
;
231 size
= sizeof(args
.fermi
);
233 args
.nv50
.version
= 0;
234 args
.nv50
.ilength
= 0x02000;
235 args
.nv50
.ioffset
= 0x10000 + chan
->push
.vma
.offset
;
236 args
.nv50
.pushbuf
= nvif_handle(&chan
->push
.ctxdma
);
238 size
= sizeof(args
.nv50
);
241 ret
= nvif_object_init(&device
->object
, 0, *oclass
++,
242 &args
, size
, &chan
->user
);
244 if (chan
->user
.oclass
>= KEPLER_CHANNEL_GPFIFO_A
)
245 chan
->chid
= args
.kepler
.chid
;
247 if (chan
->user
.oclass
>= FERMI_CHANNEL_GPFIFO
)
248 chan
->chid
= args
.fermi
.chid
;
250 chan
->chid
= args
.nv50
.chid
;
255 nouveau_channel_del(pchan
);
260 nouveau_channel_dma(struct nouveau_drm
*drm
, struct nvif_device
*device
,
261 struct nouveau_channel
**pchan
)
263 static const u16 oclasses
[] = { NV40_CHANNEL_DMA
,
268 const u16
*oclass
= oclasses
;
269 struct nv03_channel_dma_v0 args
;
270 struct nouveau_channel
*chan
;
273 /* allocate dma push buffer */
274 ret
= nouveau_channel_prep(drm
, device
, 0x10000, &chan
);
279 /* create channel object */
281 args
.pushbuf
= nvif_handle(&chan
->push
.ctxdma
);
282 args
.offset
= chan
->push
.vma
.offset
;
285 ret
= nvif_object_init(&device
->object
, 0, *oclass
++,
286 &args
, sizeof(args
), &chan
->user
);
288 chan
->chid
= args
.chid
;
291 } while (ret
&& *oclass
);
293 nouveau_channel_del(pchan
);
298 nouveau_channel_init(struct nouveau_channel
*chan
, u32 vram
, u32 gart
)
300 struct nvif_device
*device
= chan
->device
;
301 struct nouveau_cli
*cli
= (void *)chan
->user
.client
;
302 struct nvkm_mmu
*mmu
= nvxx_mmu(device
);
303 struct nv_dma_v0 args
= {};
306 nvif_object_map(&chan
->user
);
308 /* allocate dma objects to cover all allowed vram, and gart */
309 if (device
->info
.family
< NV_DEVICE_INFO_V0_FERMI
) {
310 if (device
->info
.family
>= NV_DEVICE_INFO_V0_TESLA
) {
311 args
.target
= NV_DMA_V0_TARGET_VM
;
312 args
.access
= NV_DMA_V0_ACCESS_VM
;
314 args
.limit
= cli
->vm
->mmu
->limit
- 1;
316 args
.target
= NV_DMA_V0_TARGET_VRAM
;
317 args
.access
= NV_DMA_V0_ACCESS_RDWR
;
319 args
.limit
= device
->info
.ram_user
- 1;
322 ret
= nvif_object_init(&chan
->user
, vram
, NV_DMA_IN_MEMORY
,
323 &args
, sizeof(args
), &chan
->vram
);
327 if (device
->info
.family
>= NV_DEVICE_INFO_V0_TESLA
) {
328 args
.target
= NV_DMA_V0_TARGET_VM
;
329 args
.access
= NV_DMA_V0_ACCESS_VM
;
331 args
.limit
= cli
->vm
->mmu
->limit
- 1;
333 if (chan
->drm
->agp
.bridge
) {
334 args
.target
= NV_DMA_V0_TARGET_AGP
;
335 args
.access
= NV_DMA_V0_ACCESS_RDWR
;
336 args
.start
= chan
->drm
->agp
.base
;
337 args
.limit
= chan
->drm
->agp
.base
+
338 chan
->drm
->agp
.size
- 1;
340 args
.target
= NV_DMA_V0_TARGET_VM
;
341 args
.access
= NV_DMA_V0_ACCESS_RDWR
;
343 args
.limit
= mmu
->limit
- 1;
346 ret
= nvif_object_init(&chan
->user
, gart
, NV_DMA_IN_MEMORY
,
347 &args
, sizeof(args
), &chan
->gart
);
352 /* initialise dma tracking parameters */
353 switch (chan
->user
.oclass
& 0x00ff) {
356 chan
->user_put
= 0x40;
357 chan
->user_get
= 0x44;
358 chan
->dma
.max
= (0x10000 / 4) - 2;
361 chan
->user_put
= 0x40;
362 chan
->user_get
= 0x44;
363 chan
->user_get_hi
= 0x60;
364 chan
->dma
.ib_base
= 0x10000 / 4;
365 chan
->dma
.ib_max
= (0x02000 / 8) - 1;
366 chan
->dma
.ib_put
= 0;
367 chan
->dma
.ib_free
= chan
->dma
.ib_max
- chan
->dma
.ib_put
;
368 chan
->dma
.max
= chan
->dma
.ib_base
;
373 chan
->dma
.cur
= chan
->dma
.put
;
374 chan
->dma
.free
= chan
->dma
.max
- chan
->dma
.cur
;
376 ret
= RING_SPACE(chan
, NOUVEAU_DMA_SKIPS
);
380 for (i
= 0; i
< NOUVEAU_DMA_SKIPS
; i
++)
381 OUT_RING(chan
, 0x00000000);
383 /* allocate software object class (used for fences on <= nv05) */
384 if (device
->info
.family
< NV_DEVICE_INFO_V0_CELSIUS
) {
385 ret
= nvif_object_init(&chan
->user
, 0x006e,
387 NULL
, 0, &chan
->nvsw
);
391 ret
= RING_SPACE(chan
, 2);
395 BEGIN_NV04(chan
, NvSubSw
, 0x0000, 1);
396 OUT_RING (chan
, chan
->nvsw
.handle
);
400 /* initialise synchronisation */
401 return nouveau_fence(chan
->drm
)->context_new(chan
);
405 nouveau_channel_new(struct nouveau_drm
*drm
, struct nvif_device
*device
,
406 u32 arg0
, u32 arg1
, struct nouveau_channel
**pchan
)
408 struct nouveau_cli
*cli
= (void *)device
->object
.client
;
412 /* hack until fencenv50 is fixed, and agp access relaxed */
413 super
= cli
->base
.super
;
414 cli
->base
.super
= true;
416 ret
= nouveau_channel_ind(drm
, device
, arg0
, pchan
);
418 NV_PRINTK(dbg
, cli
, "ib channel create, %d\n", ret
);
419 ret
= nouveau_channel_dma(drm
, device
, pchan
);
421 NV_PRINTK(dbg
, cli
, "dma channel create, %d\n", ret
);
426 ret
= nouveau_channel_init(*pchan
, arg0
, arg1
);
428 NV_PRINTK(err
, cli
, "channel failed to initialise, %d\n", ret
);
429 nouveau_channel_del(pchan
);
433 cli
->base
.super
= super
;