2 * Copyright 2005-2006 Stephane Marchesin
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
27 #include "nouveau_drv.h"
28 #include "nouveau_drm.h"
29 #include "nouveau_dma.h"
32 nouveau_channel_pushbuf_ctxdma_init(struct nouveau_channel
*chan
)
34 struct drm_device
*dev
= chan
->dev
;
35 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
36 struct nouveau_bo
*pb
= chan
->pushbuf_bo
;
37 struct nouveau_gpuobj
*pushbuf
= NULL
;
40 if (dev_priv
->card_type
>= NV_50
) {
41 ret
= nouveau_gpuobj_dma_new(chan
, NV_CLASS_DMA_IN_MEMORY
, 0,
42 dev_priv
->vm_end
, NV_DMA_ACCESS_RO
,
43 NV_DMA_TARGET_AGP
, &pushbuf
);
44 chan
->pushbuf_base
= pb
->bo
.offset
;
46 if (pb
->bo
.mem
.mem_type
== TTM_PL_TT
) {
47 ret
= nouveau_gpuobj_gart_dma_new(chan
, 0,
48 dev_priv
->gart_info
.aper_size
,
49 NV_DMA_ACCESS_RO
, &pushbuf
,
51 chan
->pushbuf_base
= pb
->bo
.mem
.mm_node
->start
<< PAGE_SHIFT
;
53 if (dev_priv
->card_type
!= NV_04
) {
54 ret
= nouveau_gpuobj_dma_new(chan
, NV_CLASS_DMA_IN_MEMORY
, 0,
55 dev_priv
->fb_available_size
,
57 NV_DMA_TARGET_VIDMEM
, &pushbuf
);
58 chan
->pushbuf_base
= pb
->bo
.mem
.mm_node
->start
<< PAGE_SHIFT
;
60 /* NV04 cmdbuf hack, from original ddx.. not sure of it's
61 * exact reason for existing :) PCI access to cmdbuf in
64 ret
= nouveau_gpuobj_dma_new(chan
, NV_CLASS_DMA_IN_MEMORY
,
65 pci_resource_start(dev
->pdev
,
67 dev_priv
->fb_available_size
,
69 NV_DMA_TARGET_PCI
, &pushbuf
);
70 chan
->pushbuf_base
= pb
->bo
.mem
.mm_node
->start
<< PAGE_SHIFT
;
73 ret
= nouveau_gpuobj_ref_add(dev
, chan
, 0, pushbuf
, &chan
->pushbuf
);
75 NV_ERROR(dev
, "Error referencing pushbuf ctxdma: %d\n", ret
);
76 if (pushbuf
!= dev_priv
->gart_info
.sg_ctxdma
)
77 nouveau_gpuobj_del(dev
, &pushbuf
);
84 static struct nouveau_bo
*
85 nouveau_channel_user_pushbuf_alloc(struct drm_device
*dev
)
87 struct nouveau_bo
*pushbuf
= NULL
;
90 if (nouveau_vram_pushbuf
)
91 location
= TTM_PL_FLAG_VRAM
;
93 location
= TTM_PL_FLAG_TT
;
95 ret
= nouveau_bo_new(dev
, NULL
, 65536, 0, location
, 0, 0x0000, false,
98 NV_ERROR(dev
, "error allocating DMA push buffer: %d\n", ret
);
102 ret
= nouveau_bo_pin(pushbuf
, location
);
104 NV_ERROR(dev
, "error pinning DMA push buffer: %d\n", ret
);
105 nouveau_bo_ref(NULL
, &pushbuf
);
112 /* allocates and initializes a fifo for user space consumption */
114 nouveau_channel_alloc(struct drm_device
*dev
, struct nouveau_channel
**chan_ret
,
115 struct drm_file
*file_priv
,
116 uint32_t vram_handle
, uint32_t tt_handle
)
118 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
119 struct nouveau_pgraph_engine
*pgraph
= &dev_priv
->engine
.graph
;
120 struct nouveau_fifo_engine
*pfifo
= &dev_priv
->engine
.fifo
;
121 struct nouveau_channel
*chan
;
126 * Alright, here is the full story
127 * Nvidia cards have multiple hw fifo contexts (praise them for that,
128 * no complicated crash-prone context switches)
129 * We allocate a new context for each app and let it write to it
130 * directly (woo, full userspace command submission !)
131 * When there are no more contexts, you lost
133 for (channel
= 0; channel
< pfifo
->channels
; channel
++) {
134 if (dev_priv
->fifos
[channel
] == NULL
)
138 /* no more fifos. you lost. */
139 if (channel
== pfifo
->channels
)
142 dev_priv
->fifos
[channel
] = kzalloc(sizeof(struct nouveau_channel
),
144 if (!dev_priv
->fifos
[channel
])
146 chan
= dev_priv
->fifos
[channel
];
147 INIT_LIST_HEAD(&chan
->nvsw
.vbl_wait
);
148 INIT_LIST_HEAD(&chan
->fence
.pending
);
151 chan
->file_priv
= file_priv
;
152 chan
->vram_handle
= vram_handle
;
153 chan
->gart_handle
= tt_handle
;
155 NV_INFO(dev
, "Allocating FIFO number %d\n", channel
);
157 /* Allocate DMA push buffer */
158 chan
->pushbuf_bo
= nouveau_channel_user_pushbuf_alloc(dev
);
159 if (!chan
->pushbuf_bo
) {
161 NV_ERROR(dev
, "pushbuf %d\n", ret
);
162 nouveau_channel_free(chan
);
166 nouveau_dma_pre_init(chan
);
168 /* Locate channel's user control regs */
169 if (dev_priv
->card_type
< NV_40
)
170 user
= NV03_USER(channel
);
172 if (dev_priv
->card_type
< NV_50
)
173 user
= NV40_USER(channel
);
175 user
= NV50_USER(channel
);
177 chan
->user
= ioremap(pci_resource_start(dev
->pdev
, 0) + user
,
180 NV_ERROR(dev
, "ioremap of regs failed.\n");
181 nouveau_channel_free(chan
);
184 chan
->user_put
= 0x40;
185 chan
->user_get
= 0x44;
187 /* Allocate space for per-channel fixed notifier memory */
188 ret
= nouveau_notifier_init_channel(chan
);
190 NV_ERROR(dev
, "ntfy %d\n", ret
);
191 nouveau_channel_free(chan
);
195 /* Setup channel's default objects */
196 ret
= nouveau_gpuobj_channel_init(chan
, vram_handle
, tt_handle
);
198 NV_ERROR(dev
, "gpuobj %d\n", ret
);
199 nouveau_channel_free(chan
);
203 /* Create a dma object for the push buffer */
204 ret
= nouveau_channel_pushbuf_ctxdma_init(chan
);
206 NV_ERROR(dev
, "pbctxdma %d\n", ret
);
207 nouveau_channel_free(chan
);
211 /* disable the fifo caches */
212 pfifo
->reassign(dev
, false);
214 /* Create a graphics context for new channel */
215 ret
= pgraph
->create_context(chan
);
217 nouveau_channel_free(chan
);
221 /* Construct inital RAMFC for new channel */
222 ret
= pfifo
->create_context(chan
);
224 nouveau_channel_free(chan
);
228 pfifo
->reassign(dev
, true);
230 ret
= nouveau_dma_init(chan
);
232 ret
= nouveau_fence_init(chan
);
234 nouveau_channel_free(chan
);
238 nouveau_debugfs_channel_init(chan
);
240 NV_INFO(dev
, "%s: initialised FIFO %d\n", __func__
, channel
);
247 nouveau_channel_free(struct nouveau_channel
*chan
)
249 struct drm_device
*dev
= chan
->dev
;
250 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
251 struct nouveau_pgraph_engine
*pgraph
= &dev_priv
->engine
.graph
;
252 struct nouveau_fifo_engine
*pfifo
= &dev_priv
->engine
.fifo
;
256 NV_INFO(dev
, "%s: freeing fifo %d\n", __func__
, chan
->id
);
258 nouveau_debugfs_channel_fini(chan
);
260 /* Give outstanding push buffers a chance to complete */
261 nouveau_fence_update(chan
);
262 if (chan
->fence
.sequence
!= chan
->fence
.sequence_ack
) {
263 struct nouveau_fence
*fence
= NULL
;
265 ret
= nouveau_fence_new(chan
, &fence
, true);
267 ret
= nouveau_fence_wait(fence
, NULL
, false, false);
268 nouveau_fence_unref((void *)&fence
);
272 NV_ERROR(dev
, "Failed to idle channel %d.\n", chan
->id
);
275 /* Ensure all outstanding fences are signaled. They should be if the
276 * above attempts at idling were OK, but if we failed this'll tell TTM
277 * we're done with the buffers.
279 nouveau_fence_fini(chan
);
281 /* This will prevent pfifo from switching channels. */
282 pfifo
->reassign(dev
, false);
284 /* We want to give pgraph a chance to idle and get rid of all potential
285 * errors. We need to do this before the lock, otherwise the irq handler
286 * is unable to process them.
288 if (pgraph
->channel(dev
) == chan
)
289 nouveau_wait_for_idle(dev
);
291 spin_lock_irqsave(&dev_priv
->context_switch_lock
, flags
);
293 pgraph
->fifo_access(dev
, false);
294 if (pgraph
->channel(dev
) == chan
)
295 pgraph
->unload_context(dev
);
296 pgraph
->destroy_context(chan
);
297 pgraph
->fifo_access(dev
, true);
299 if (pfifo
->channel_id(dev
) == chan
->id
) {
301 pfifo
->unload_context(dev
);
304 pfifo
->destroy_context(chan
);
306 pfifo
->reassign(dev
, true);
308 spin_unlock_irqrestore(&dev_priv
->context_switch_lock
, flags
);
310 /* Release the channel's resources */
311 nouveau_gpuobj_ref_del(dev
, &chan
->pushbuf
);
312 if (chan
->pushbuf_bo
) {
313 nouveau_bo_unpin(chan
->pushbuf_bo
);
314 nouveau_bo_ref(NULL
, &chan
->pushbuf_bo
);
316 nouveau_gpuobj_channel_takedown(chan
);
317 nouveau_notifier_takedown_channel(chan
);
321 dev_priv
->fifos
[chan
->id
] = NULL
;
325 /* cleans up all the fifos from file_priv */
327 nouveau_channel_cleanup(struct drm_device
*dev
, struct drm_file
*file_priv
)
329 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
330 struct nouveau_engine
*engine
= &dev_priv
->engine
;
333 NV_DEBUG(dev
, "clearing FIFO enables from file_priv\n");
334 for (i
= 0; i
< engine
->fifo
.channels
; i
++) {
335 struct nouveau_channel
*chan
= dev_priv
->fifos
[i
];
337 if (chan
&& chan
->file_priv
== file_priv
)
338 nouveau_channel_free(chan
);
343 nouveau_channel_owner(struct drm_device
*dev
, struct drm_file
*file_priv
,
346 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
347 struct nouveau_engine
*engine
= &dev_priv
->engine
;
349 if (channel
>= engine
->fifo
.channels
)
351 if (dev_priv
->fifos
[channel
] == NULL
)
354 return (dev_priv
->fifos
[channel
]->file_priv
== file_priv
);
357 /***********************************
358 * ioctls wrapping the functions
359 ***********************************/
362 nouveau_ioctl_fifo_alloc(struct drm_device
*dev
, void *data
,
363 struct drm_file
*file_priv
)
365 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
366 struct drm_nouveau_channel_alloc
*init
= data
;
367 struct nouveau_channel
*chan
;
370 if (dev_priv
->engine
.graph
.accel_blocked
)
373 if (init
->fb_ctxdma_handle
== ~0 || init
->tt_ctxdma_handle
== ~0)
376 ret
= nouveau_channel_alloc(dev
, &chan
, file_priv
,
377 init
->fb_ctxdma_handle
,
378 init
->tt_ctxdma_handle
);
381 init
->channel
= chan
->id
;
383 if (chan
->dma
.ib_max
)
384 init
->pushbuf_domains
= NOUVEAU_GEM_DOMAIN_VRAM
|
385 NOUVEAU_GEM_DOMAIN_GART
;
386 else if (chan
->pushbuf_bo
->bo
.mem
.mem_type
== TTM_PL_VRAM
)
387 init
->pushbuf_domains
= NOUVEAU_GEM_DOMAIN_VRAM
;
389 init
->pushbuf_domains
= NOUVEAU_GEM_DOMAIN_GART
;
391 init
->subchan
[0].handle
= NvM2MF
;
392 if (dev_priv
->card_type
< NV_50
)
393 init
->subchan
[0].grclass
= 0x0039;
395 init
->subchan
[0].grclass
= 0x5039;
396 init
->subchan
[1].handle
= NvSw
;
397 init
->subchan
[1].grclass
= NV_SW
;
398 init
->nr_subchan
= 2;
400 /* Named memory object area */
401 ret
= drm_gem_handle_create(file_priv
, chan
->notifier_bo
->gem
,
402 &init
->notifier_handle
);
404 nouveau_channel_free(chan
);
412 nouveau_ioctl_fifo_free(struct drm_device
*dev
, void *data
,
413 struct drm_file
*file_priv
)
415 struct drm_nouveau_channel_free
*cfree
= data
;
416 struct nouveau_channel
*chan
;
418 NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(cfree
->channel
, file_priv
, chan
);
420 nouveau_channel_free(chan
);
424 /***********************************
425 * finally, the ioctl table
426 ***********************************/
428 struct drm_ioctl_desc nouveau_ioctls
[] = {
429 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM
, nouveau_ioctl_getparam
, DRM_AUTH
),
430 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM
, nouveau_ioctl_setparam
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
431 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC
, nouveau_ioctl_fifo_alloc
, DRM_AUTH
),
432 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE
, nouveau_ioctl_fifo_free
, DRM_AUTH
),
433 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC
, nouveau_ioctl_grobj_alloc
, DRM_AUTH
),
434 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC
, nouveau_ioctl_notifier_alloc
, DRM_AUTH
),
435 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE
, nouveau_ioctl_gpuobj_free
, DRM_AUTH
),
436 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW
, nouveau_gem_ioctl_new
, DRM_AUTH
),
437 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF
, nouveau_gem_ioctl_pushbuf
, DRM_AUTH
),
438 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP
, nouveau_gem_ioctl_cpu_prep
, DRM_AUTH
),
439 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI
, nouveau_gem_ioctl_cpu_fini
, DRM_AUTH
),
440 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO
, nouveau_gem_ioctl_info
, DRM_AUTH
),
443 int nouveau_max_ioctl
= DRM_ARRAY_SIZE(nouveau_ioctls
);