2 * Copyright 2009 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "nouveau_drv.h"
28 #include "nouveau_i2c.h"
29 #include "nouveau_connector.h"
30 #include "nouveau_encoder.h"
33 auxch_rd(struct drm_encoder
*encoder
, int address
, uint8_t *buf
, int size
)
35 struct drm_device
*dev
= encoder
->dev
;
36 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
37 struct nouveau_i2c_chan
*auxch
;
40 auxch
= nouveau_i2c_find(dev
, nv_encoder
->dcb
->i2c_index
);
44 ret
= nouveau_dp_auxch(auxch
, 9, address
, buf
, size
);
52 auxch_wr(struct drm_encoder
*encoder
, int address
, uint8_t *buf
, int size
)
54 struct drm_device
*dev
= encoder
->dev
;
55 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
56 struct nouveau_i2c_chan
*auxch
;
59 auxch
= nouveau_i2c_find(dev
, nv_encoder
->dcb
->i2c_index
);
63 ret
= nouveau_dp_auxch(auxch
, 8, address
, buf
, size
);
68 nouveau_dp_lane_count_set(struct drm_encoder
*encoder
, uint8_t cmd
)
70 struct drm_device
*dev
= encoder
->dev
;
71 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
73 int or = nv_encoder
->or, link
= !(nv_encoder
->dcb
->sorconf
.link
& 1);
75 tmp
= nv_rd32(dev
, NV50_SOR_DP_CTRL(or, link
));
76 tmp
&= ~(NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED
|
77 NV50_SOR_DP_CTRL_LANE_MASK
);
78 tmp
|= ((1 << (cmd
& DP_LANE_COUNT_MASK
)) - 1) << 16;
79 if (cmd
& DP_LANE_COUNT_ENHANCED_FRAME_EN
)
80 tmp
|= NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED
;
81 nv_wr32(dev
, NV50_SOR_DP_CTRL(or, link
), tmp
);
83 return auxch_wr(encoder
, DP_LANE_COUNT_SET
, &cmd
, 1);
87 nouveau_dp_link_bw_set(struct drm_encoder
*encoder
, uint8_t cmd
)
89 struct drm_device
*dev
= encoder
->dev
;
90 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
92 int reg
= 0x614300 + (nv_encoder
->or * 0x800);
94 tmp
= nv_rd32(dev
, reg
);
96 if (cmd
== DP_LINK_BW_2_7
)
98 nv_wr32(dev
, reg
, tmp
);
100 return auxch_wr(encoder
, DP_LINK_BW_SET
, &cmd
, 1);
104 nouveau_dp_link_train_set(struct drm_encoder
*encoder
, int pattern
)
106 struct drm_device
*dev
= encoder
->dev
;
107 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
110 int or = nv_encoder
->or, link
= !(nv_encoder
->dcb
->sorconf
.link
& 1);
113 tmp
= nv_rd32(dev
, NV50_SOR_DP_CTRL(or, link
));
114 tmp
&= ~NV50_SOR_DP_CTRL_TRAINING_PATTERN
;
115 tmp
|= (pattern
<< 24);
116 nv_wr32(dev
, NV50_SOR_DP_CTRL(or, link
), tmp
);
118 ret
= auxch_rd(encoder
, DP_TRAINING_PATTERN_SET
, &cmd
, 1);
121 cmd
&= ~DP_TRAINING_PATTERN_MASK
;
122 cmd
|= (pattern
& DP_TRAINING_PATTERN_MASK
);
123 return auxch_wr(encoder
, DP_TRAINING_PATTERN_SET
, &cmd
, 1);
127 nouveau_dp_max_voltage_swing(struct drm_encoder
*encoder
)
129 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
130 struct drm_device
*dev
= encoder
->dev
;
131 struct bit_displayport_encoder_table_entry
*dpse
;
132 struct bit_displayport_encoder_table
*dpe
;
133 int i
, dpe_headerlen
, max_vs
= 0;
135 dpe
= nouveau_bios_dp_table(dev
, nv_encoder
->dcb
, &dpe_headerlen
);
138 dpse
= (void *)((char *)dpe
+ dpe_headerlen
);
140 for (i
= 0; i
< dpe_headerlen
; i
++, dpse
++) {
141 if (dpse
->vs_level
> max_vs
)
142 max_vs
= dpse
->vs_level
;
149 nouveau_dp_max_pre_emphasis(struct drm_encoder
*encoder
, int vs
)
151 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
152 struct drm_device
*dev
= encoder
->dev
;
153 struct bit_displayport_encoder_table_entry
*dpse
;
154 struct bit_displayport_encoder_table
*dpe
;
155 int i
, dpe_headerlen
, max_pre
= 0;
157 dpe
= nouveau_bios_dp_table(dev
, nv_encoder
->dcb
, &dpe_headerlen
);
160 dpse
= (void *)((char *)dpe
+ dpe_headerlen
);
162 for (i
= 0; i
< dpe_headerlen
; i
++, dpse
++) {
163 if (dpse
->vs_level
!= vs
)
166 if (dpse
->pre_level
> max_pre
)
167 max_pre
= dpse
->pre_level
;
174 nouveau_dp_link_train_adjust(struct drm_encoder
*encoder
, uint8_t *config
)
176 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
177 struct drm_device
*dev
= encoder
->dev
;
178 struct bit_displayport_encoder_table_entry
*dpse
;
179 struct bit_displayport_encoder_table
*dpe
;
180 int ret
, i
, dpe_headerlen
, vs
= 0, pre
= 0;
183 dpe
= nouveau_bios_dp_table(dev
, nv_encoder
->dcb
, &dpe_headerlen
);
186 dpse
= (void *)((char *)dpe
+ dpe_headerlen
);
188 ret
= auxch_rd(encoder
, DP_ADJUST_REQUEST_LANE0_1
, request
, 2);
192 NV_DEBUG_KMS(dev
, "\t\tadjust 0x%02x 0x%02x\n", request
[0], request
[1]);
194 /* Keep all lanes at the same level.. */
195 for (i
= 0; i
< nv_encoder
->dp
.link_nr
; i
++) {
196 int lane_req
= (request
[i
>> 1] >> ((i
& 1) << 2)) & 0xf;
197 int lane_vs
= lane_req
& 3;
198 int lane_pre
= (lane_req
>> 2) & 3;
206 if (vs
>= nouveau_dp_max_voltage_swing(encoder
)) {
207 vs
= nouveau_dp_max_voltage_swing(encoder
);
211 if (pre
>= nouveau_dp_max_pre_emphasis(encoder
, vs
& 3)) {
212 pre
= nouveau_dp_max_pre_emphasis(encoder
, vs
& 3);
216 /* Update the configuration for all lanes.. */
217 for (i
= 0; i
< nv_encoder
->dp
.link_nr
; i
++)
218 config
[i
] = (pre
<< 3) | vs
;
224 nouveau_dp_link_train_commit(struct drm_encoder
*encoder
, uint8_t *config
)
226 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
227 struct drm_device
*dev
= encoder
->dev
;
228 struct bit_displayport_encoder_table_entry
*dpse
;
229 struct bit_displayport_encoder_table
*dpe
;
230 int or = nv_encoder
->or, link
= !(nv_encoder
->dcb
->sorconf
.link
& 1);
231 int dpe_headerlen
, ret
, i
;
233 NV_DEBUG_KMS(dev
, "\t\tconfig 0x%02x 0x%02x 0x%02x 0x%02x\n",
234 config
[0], config
[1], config
[2], config
[3]);
236 dpe
= nouveau_bios_dp_table(dev
, nv_encoder
->dcb
, &dpe_headerlen
);
239 dpse
= (void *)((char *)dpe
+ dpe_headerlen
);
241 for (i
= 0; i
< dpe
->record_nr
; i
++, dpse
++) {
242 if (dpse
->vs_level
== (config
[0] & 3) &&
243 dpse
->pre_level
== ((config
[0] >> 3) & 3))
246 BUG_ON(i
== dpe
->record_nr
);
248 for (i
= 0; i
< nv_encoder
->dp
.link_nr
; i
++) {
249 const int shift
[4] = { 16, 8, 0, 24 };
250 uint32_t mask
= 0xff << shift
[i
];
251 uint32_t reg0
, reg1
, reg2
;
253 reg0
= nv_rd32(dev
, NV50_SOR_DP_UNK118(or, link
)) & ~mask
;
254 reg0
|= (dpse
->reg0
<< shift
[i
]);
255 reg1
= nv_rd32(dev
, NV50_SOR_DP_UNK120(or, link
)) & ~mask
;
256 reg1
|= (dpse
->reg1
<< shift
[i
]);
257 reg2
= nv_rd32(dev
, NV50_SOR_DP_UNK130(or, link
)) & 0xffff00ff;
258 reg2
|= (dpse
->reg2
<< 8);
259 nv_wr32(dev
, NV50_SOR_DP_UNK118(or, link
), reg0
);
260 nv_wr32(dev
, NV50_SOR_DP_UNK120(or, link
), reg1
);
261 nv_wr32(dev
, NV50_SOR_DP_UNK130(or, link
), reg2
);
264 ret
= auxch_wr(encoder
, DP_TRAINING_LANE0_SET
, config
, 4);
272 nouveau_dp_link_train(struct drm_encoder
*encoder
)
274 struct drm_device
*dev
= encoder
->dev
;
275 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
276 struct nouveau_gpio_engine
*pgpio
= &dev_priv
->engine
.gpio
;
277 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
278 struct nouveau_connector
*nv_connector
;
279 struct bit_displayport_encoder_table
*dpe
;
281 uint8_t config
[4], status
[3];
282 bool cr_done
, cr_max_vs
, eq_done
;
283 int ret
= 0, i
, tries
, voltage
;
285 NV_DEBUG_KMS(dev
, "link training!!\n");
287 nv_connector
= nouveau_encoder_connector_get(nv_encoder
);
291 dpe
= nouveau_bios_dp_table(dev
, nv_encoder
->dcb
, &dpe_headerlen
);
293 NV_ERROR(dev
, "SOR-%d: no DP encoder table!\n", nv_encoder
->or);
297 /* disable hotplug detect, this flips around on some panels during
300 pgpio
->irq_enable(dev
, nv_connector
->dcb
->gpio_tag
, false);
303 NV_DEBUG_KMS(dev
, "SOR-%d: running DP script 0\n", nv_encoder
->or);
304 nouveau_bios_run_init_table(dev
, le16_to_cpu(dpe
->script0
),
309 cr_done
= eq_done
= false;
311 /* set link configuration */
312 NV_DEBUG_KMS(dev
, "\tbegin train: bw %d, lanes %d\n",
313 nv_encoder
->dp
.link_bw
, nv_encoder
->dp
.link_nr
);
315 ret
= nouveau_dp_link_bw_set(encoder
, nv_encoder
->dp
.link_bw
);
319 config
[0] = nv_encoder
->dp
.link_nr
;
320 if (nv_encoder
->dp
.dpcd_version
>= 0x11)
321 config
[0] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
323 ret
= nouveau_dp_lane_count_set(encoder
, config
[0]);
328 NV_DEBUG_KMS(dev
, "\tbegin cr\n");
329 ret
= nouveau_dp_link_train_set(encoder
, DP_TRAINING_PATTERN_1
);
335 memset(config
, 0x00, sizeof(config
));
337 if (!nouveau_dp_link_train_commit(encoder
, config
))
342 ret
= auxch_rd(encoder
, DP_LANE0_1_STATUS
, status
, 2);
345 NV_DEBUG_KMS(dev
, "\t\tstatus: 0x%02x 0x%02x\n",
346 status
[0], status
[1]);
350 for (i
= 0; i
< nv_encoder
->dp
.link_nr
; i
++) {
351 int lane
= (status
[i
>> 1] >> ((i
& 1) * 4)) & 0xf;
353 if (!(lane
& DP_LANE_CR_DONE
)) {
355 if (config
[i
] & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
)
361 if ((config
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) != voltage
) {
362 voltage
= config
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
366 if (cr_done
|| cr_max_vs
|| (++tries
== 5))
369 if (!nouveau_dp_link_train_adjust(encoder
, config
))
376 /* channel equalisation */
377 NV_DEBUG_KMS(dev
, "\tbegin eq\n");
378 ret
= nouveau_dp_link_train_set(encoder
, DP_TRAINING_PATTERN_2
);
382 for (tries
= 0; tries
<= 5; tries
++) {
385 ret
= auxch_rd(encoder
, DP_LANE0_1_STATUS
, status
, 3);
388 NV_DEBUG_KMS(dev
, "\t\tstatus: 0x%02x 0x%02x\n",
389 status
[0], status
[1]);
392 if (!(status
[2] & DP_INTERLANE_ALIGN_DONE
))
395 for (i
= 0; eq_done
&& i
< nv_encoder
->dp
.link_nr
; i
++) {
396 int lane
= (status
[i
>> 1] >> ((i
& 1) * 4)) & 0xf;
398 if (!(lane
& DP_LANE_CR_DONE
)) {
403 if (!(lane
& DP_LANE_CHANNEL_EQ_DONE
) ||
404 !(lane
& DP_LANE_SYMBOL_LOCKED
)) {
410 if (eq_done
|| !cr_done
)
413 if (!nouveau_dp_link_train_adjust(encoder
, config
) ||
414 !nouveau_dp_link_train_commit(encoder
, config
))
419 /* end link training */
420 ret
= nouveau_dp_link_train_set(encoder
, DP_TRAINING_PATTERN_DISABLE
);
424 /* retry at a lower setting, if possible */
425 if (!ret
&& !(eq_done
&& cr_done
)) {
426 NV_DEBUG_KMS(dev
, "\twe failed\n");
427 if (nv_encoder
->dp
.link_bw
!= DP_LINK_BW_1_62
) {
428 NV_DEBUG_KMS(dev
, "retry link training at low rate\n");
429 nv_encoder
->dp
.link_bw
= DP_LINK_BW_1_62
;
435 NV_DEBUG_KMS(dev
, "SOR-%d: running DP script 1\n", nv_encoder
->or);
436 nouveau_bios_run_init_table(dev
, le16_to_cpu(dpe
->script1
),
440 /* re-enable hotplug detect */
441 pgpio
->irq_enable(dev
, nv_connector
->dcb
->gpio_tag
, true);
447 nouveau_dp_detect(struct drm_encoder
*encoder
)
449 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
450 struct drm_device
*dev
= encoder
->dev
;
454 ret
= auxch_rd(encoder
, 0x0000, dpcd
, 4);
458 NV_DEBUG_KMS(dev
, "encoder: link_bw %d, link_nr %d\n"
459 "display: link_bw %d, link_nr %d version 0x%02x\n",
460 nv_encoder
->dcb
->dpconf
.link_bw
,
461 nv_encoder
->dcb
->dpconf
.link_nr
,
462 dpcd
[1], dpcd
[2] & 0x0f, dpcd
[0]);
464 nv_encoder
->dp
.dpcd_version
= dpcd
[0];
466 nv_encoder
->dp
.link_bw
= dpcd
[1];
467 if (nv_encoder
->dp
.link_bw
!= DP_LINK_BW_1_62
&&
468 !nv_encoder
->dcb
->dpconf
.link_bw
)
469 nv_encoder
->dp
.link_bw
= DP_LINK_BW_1_62
;
471 nv_encoder
->dp
.link_nr
= dpcd
[2] & 0xf;
472 if (nv_encoder
->dp
.link_nr
> nv_encoder
->dcb
->dpconf
.link_nr
)
473 nv_encoder
->dp
.link_nr
= nv_encoder
->dcb
->dpconf
.link_nr
;
479 nouveau_dp_auxch(struct nouveau_i2c_chan
*auxch
, int cmd
, int addr
,
480 uint8_t *data
, int data_nr
)
482 struct drm_device
*dev
= auxch
->dev
;
483 uint32_t tmp
, ctrl
, stat
= 0, data32
[4] = {};
484 int ret
= 0, i
, index
= auxch
->rd
;
486 NV_DEBUG_KMS(dev
, "ch %d cmd %d addr 0x%x len %d\n", index
, cmd
, addr
, data_nr
);
488 tmp
= nv_rd32(dev
, NV50_AUXCH_CTRL(auxch
->rd
));
489 nv_wr32(dev
, NV50_AUXCH_CTRL(auxch
->rd
), tmp
| 0x00100000);
490 tmp
= nv_rd32(dev
, NV50_AUXCH_CTRL(auxch
->rd
));
491 if (!(tmp
& 0x01000000)) {
492 NV_ERROR(dev
, "expected bit 24 == 1, got 0x%08x\n", tmp
);
497 for (i
= 0; i
< 3; i
++) {
498 tmp
= nv_rd32(dev
, NV50_AUXCH_STAT(auxch
->rd
));
499 if (tmp
& NV50_AUXCH_STAT_STATE_READY
)
510 memcpy(data32
, data
, data_nr
);
511 for (i
= 0; i
< 4; i
++) {
512 NV_DEBUG_KMS(dev
, "wr %d: 0x%08x\n", i
, data32
[i
]);
513 nv_wr32(dev
, NV50_AUXCH_DATA_OUT(index
, i
), data32
[i
]);
517 nv_wr32(dev
, NV50_AUXCH_ADDR(index
), addr
);
518 ctrl
= nv_rd32(dev
, NV50_AUXCH_CTRL(index
));
519 ctrl
&= ~(NV50_AUXCH_CTRL_CMD
| NV50_AUXCH_CTRL_LEN
);
520 ctrl
|= (cmd
<< NV50_AUXCH_CTRL_CMD_SHIFT
);
521 ctrl
|= ((data_nr
- 1) << NV50_AUXCH_CTRL_LEN_SHIFT
);
523 for (i
= 0; i
< 16; i
++) {
524 nv_wr32(dev
, NV50_AUXCH_CTRL(index
), ctrl
| 0x80000000);
525 nv_wr32(dev
, NV50_AUXCH_CTRL(index
), ctrl
);
526 nv_wr32(dev
, NV50_AUXCH_CTRL(index
), ctrl
| 0x00010000);
527 if (!nv_wait(NV50_AUXCH_CTRL(index
), 0x00010000, 0x00000000)) {
528 NV_ERROR(dev
, "expected bit 16 == 0, got 0x%08x\n",
529 nv_rd32(dev
, NV50_AUXCH_CTRL(index
)));
536 stat
= nv_rd32(dev
, NV50_AUXCH_STAT(index
));
537 if ((stat
& NV50_AUXCH_STAT_REPLY_AUX
) !=
538 NV50_AUXCH_STAT_REPLY_AUX_DEFER
)
543 NV_ERROR(dev
, "auxch DEFER too many times, bailing\n");
549 if ((stat
& NV50_AUXCH_STAT_COUNT
) != data_nr
) {
554 for (i
= 0; i
< 4; i
++) {
555 data32
[i
] = nv_rd32(dev
, NV50_AUXCH_DATA_IN(index
, i
));
556 NV_DEBUG_KMS(dev
, "rd %d: 0x%08x\n", i
, data32
[i
]);
558 memcpy(data
, data32
, data_nr
);
562 tmp
= nv_rd32(dev
, NV50_AUXCH_CTRL(auxch
->rd
));
563 nv_wr32(dev
, NV50_AUXCH_CTRL(auxch
->rd
), tmp
& ~0x00100000);
564 tmp
= nv_rd32(dev
, NV50_AUXCH_CTRL(auxch
->rd
));
565 if (tmp
& 0x01000000) {
566 NV_ERROR(dev
, "expected bit 24 == 0, got 0x%08x\n", tmp
);
572 return ret
? ret
: (stat
& NV50_AUXCH_STAT_REPLY
);
576 nouveau_dp_i2c_xfer(struct i2c_adapter
*adap
, struct i2c_msg
*msgs
, int num
)
578 struct nouveau_i2c_chan
*auxch
= (struct nouveau_i2c_chan
*)adap
;
579 struct drm_device
*dev
= auxch
->dev
;
580 struct i2c_msg
*msg
= msgs
;
584 u8 remaining
= msg
->len
;
588 u8 cnt
= (remaining
> 16) ? 16 : remaining
;
591 if (msg
->flags
& I2C_M_RD
)
596 if (mcnt
|| remaining
> 16)
599 ret
= nouveau_dp_auxch(auxch
, cmd
, msg
->addr
, ptr
, cnt
);
603 switch (ret
& NV50_AUXCH_STAT_REPLY_I2C
) {
604 case NV50_AUXCH_STAT_REPLY_I2C_ACK
:
606 case NV50_AUXCH_STAT_REPLY_I2C_NACK
:
608 case NV50_AUXCH_STAT_REPLY_I2C_DEFER
:
612 NV_ERROR(dev
, "bad auxch reply: 0x%08x\n", ret
);
627 nouveau_dp_i2c_func(struct i2c_adapter
*adap
)
629 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
632 const struct i2c_algorithm nouveau_dp_i2c_algo
= {
633 .master_xfer
= nouveau_dp_i2c_xfer
,
634 .functionality
= nouveau_dp_i2c_func