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drm/nouveau: Rework tile region handling.
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
1 /*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
27
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
34
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
38
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
41
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
47
48 struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50 };
51
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
57 struct nouveau_grctx;
58
59 #define MAX_NUM_DCB_ENTRIES 16
60
61 #define NOUVEAU_MAX_CHANNEL_NR 128
62 #define NOUVEAU_MAX_TILE_NR 15
63
64 #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65 #define NV50_VM_BLOCK (512*1024*1024ULL)
66 #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
68 struct nouveau_tile_reg {
69 bool used;
70 uint32_t addr;
71 uint32_t limit;
72 uint32_t pitch;
73 struct nouveau_fence *fence;
74 };
75
76 struct nouveau_bo {
77 struct ttm_buffer_object bo;
78 struct ttm_placement placement;
79 u32 placements[3];
80 u32 busy_placements[3];
81 struct ttm_bo_kmap_obj kmap;
82 struct list_head head;
83
84 /* protected by ttm_bo_reserve() */
85 struct drm_file *reserved_by;
86 struct list_head entry;
87 int pbbo_index;
88 bool validate_mapped;
89
90 struct nouveau_channel *channel;
91
92 bool mappable;
93 bool no_vm;
94
95 uint32_t tile_mode;
96 uint32_t tile_flags;
97 struct nouveau_tile_reg *tile;
98
99 struct drm_gem_object *gem;
100 int pin_refcnt;
101 };
102
103 #define nouveau_bo_tile_layout(nvbo) \
104 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
105
106 static inline struct nouveau_bo *
107 nouveau_bo(struct ttm_buffer_object *bo)
108 {
109 return container_of(bo, struct nouveau_bo, bo);
110 }
111
112 static inline struct nouveau_bo *
113 nouveau_gem_object(struct drm_gem_object *gem)
114 {
115 return gem ? gem->driver_private : NULL;
116 }
117
118 /* TODO: submit equivalent to TTM generic API upstream? */
119 static inline void __iomem *
120 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
121 {
122 bool is_iomem;
123 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
124 &nvbo->kmap, &is_iomem);
125 WARN_ON_ONCE(ioptr && !is_iomem);
126 return ioptr;
127 }
128
129 enum nouveau_flags {
130 NV_NFORCE = 0x10000000,
131 NV_NFORCE2 = 0x20000000
132 };
133
134 #define NVOBJ_ENGINE_SW 0
135 #define NVOBJ_ENGINE_GR 1
136 #define NVOBJ_ENGINE_PPP 2
137 #define NVOBJ_ENGINE_COPY 3
138 #define NVOBJ_ENGINE_VP 4
139 #define NVOBJ_ENGINE_CRYPT 5
140 #define NVOBJ_ENGINE_BSP 6
141 #define NVOBJ_ENGINE_DISPLAY 0xcafe0001
142 #define NVOBJ_ENGINE_INT 0xdeadbeef
143
144 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
145 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
146 struct nouveau_gpuobj {
147 struct drm_device *dev;
148 struct kref refcount;
149 struct list_head list;
150
151 struct drm_mm_node *im_pramin;
152 struct nouveau_bo *im_backing;
153 uint32_t *im_backing_suspend;
154 int im_bound;
155
156 uint32_t flags;
157
158 u32 size;
159 u32 pinst;
160 u32 cinst;
161 u64 vinst;
162
163 uint32_t engine;
164 uint32_t class;
165
166 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
167 void *priv;
168 };
169
170 struct nouveau_page_flip_state {
171 struct list_head head;
172 struct drm_pending_vblank_event *event;
173 int crtc, bpp, pitch, x, y;
174 uint64_t offset;
175 };
176
177 enum nouveau_channel_mutex_class {
178 NOUVEAU_UCHANNEL_MUTEX,
179 NOUVEAU_KCHANNEL_MUTEX
180 };
181
182 struct nouveau_channel {
183 struct drm_device *dev;
184 int id;
185
186 /* references to the channel data structure */
187 struct kref ref;
188 /* users of the hardware channel resources, the hardware
189 * context will be kicked off when it reaches zero. */
190 atomic_t users;
191 struct mutex mutex;
192
193 /* owner of this fifo */
194 struct drm_file *file_priv;
195 /* mapping of the fifo itself */
196 struct drm_local_map *map;
197
198 /* mapping of the regs controling the fifo */
199 void __iomem *user;
200 uint32_t user_get;
201 uint32_t user_put;
202
203 /* Fencing */
204 struct {
205 /* lock protects the pending list only */
206 spinlock_t lock;
207 struct list_head pending;
208 uint32_t sequence;
209 uint32_t sequence_ack;
210 atomic_t last_sequence_irq;
211 } fence;
212
213 /* DMA push buffer */
214 struct nouveau_gpuobj *pushbuf;
215 struct nouveau_bo *pushbuf_bo;
216 uint32_t pushbuf_base;
217
218 /* Notifier memory */
219 struct nouveau_bo *notifier_bo;
220 struct drm_mm notifier_heap;
221
222 /* PFIFO context */
223 struct nouveau_gpuobj *ramfc;
224 struct nouveau_gpuobj *cache;
225
226 /* PGRAPH context */
227 /* XXX may be merge 2 pointers as private data ??? */
228 struct nouveau_gpuobj *ramin_grctx;
229 struct nouveau_gpuobj *crypt_ctx;
230 void *pgraph_ctx;
231
232 /* NV50 VM */
233 struct nouveau_gpuobj *vm_pd;
234 struct nouveau_gpuobj *vm_gart_pt;
235 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
236
237 /* Objects */
238 struct nouveau_gpuobj *ramin; /* Private instmem */
239 struct drm_mm ramin_heap; /* Private PRAMIN heap */
240 struct nouveau_ramht *ramht; /* Hash table */
241
242 /* GPU object info for stuff used in-kernel (mm_enabled) */
243 uint32_t m2mf_ntfy;
244 uint32_t vram_handle;
245 uint32_t gart_handle;
246 bool accel_done;
247
248 /* Push buffer state (only for drm's channel on !mm_enabled) */
249 struct {
250 int max;
251 int free;
252 int cur;
253 int put;
254 /* access via pushbuf_bo */
255
256 int ib_base;
257 int ib_max;
258 int ib_free;
259 int ib_put;
260 } dma;
261
262 uint32_t sw_subchannel[8];
263
264 struct {
265 struct nouveau_gpuobj *vblsem;
266 uint32_t vblsem_head;
267 uint32_t vblsem_offset;
268 uint32_t vblsem_rval;
269 struct list_head vbl_wait;
270 struct list_head flip;
271 } nvsw;
272
273 struct {
274 bool active;
275 char name[32];
276 struct drm_info_list info;
277 } debugfs;
278 };
279
280 struct nouveau_instmem_engine {
281 void *priv;
282
283 int (*init)(struct drm_device *dev);
284 void (*takedown)(struct drm_device *dev);
285 int (*suspend)(struct drm_device *dev);
286 void (*resume)(struct drm_device *dev);
287
288 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
289 u32 *size, u32 align);
290 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
291 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
292 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
293 void (*flush)(struct drm_device *);
294 };
295
296 struct nouveau_mc_engine {
297 int (*init)(struct drm_device *dev);
298 void (*takedown)(struct drm_device *dev);
299 };
300
301 struct nouveau_timer_engine {
302 int (*init)(struct drm_device *dev);
303 void (*takedown)(struct drm_device *dev);
304 uint64_t (*read)(struct drm_device *dev);
305 };
306
307 struct nouveau_fb_engine {
308 int num_tiles;
309
310 int (*init)(struct drm_device *dev);
311 void (*takedown)(struct drm_device *dev);
312
313 void (*init_tile_region)(struct drm_device *dev, int i,
314 uint32_t addr, uint32_t size,
315 uint32_t pitch, uint32_t flags);
316 void (*set_tile_region)(struct drm_device *dev, int i);
317 void (*free_tile_region)(struct drm_device *dev, int i);
318 };
319
320 struct nouveau_fifo_engine {
321 int channels;
322
323 struct nouveau_gpuobj *playlist[2];
324 int cur_playlist;
325
326 int (*init)(struct drm_device *);
327 void (*takedown)(struct drm_device *);
328
329 void (*disable)(struct drm_device *);
330 void (*enable)(struct drm_device *);
331 bool (*reassign)(struct drm_device *, bool enable);
332 bool (*cache_pull)(struct drm_device *dev, bool enable);
333
334 int (*channel_id)(struct drm_device *);
335
336 int (*create_context)(struct nouveau_channel *);
337 void (*destroy_context)(struct nouveau_channel *);
338 int (*load_context)(struct nouveau_channel *);
339 int (*unload_context)(struct drm_device *);
340 void (*tlb_flush)(struct drm_device *dev);
341 };
342
343 struct nouveau_pgraph_engine {
344 bool accel_blocked;
345 bool registered;
346 int grctx_size;
347
348 /* NV2x/NV3x context table (0x400780) */
349 struct nouveau_gpuobj *ctx_table;
350
351 int (*init)(struct drm_device *);
352 void (*takedown)(struct drm_device *);
353
354 void (*fifo_access)(struct drm_device *, bool);
355
356 struct nouveau_channel *(*channel)(struct drm_device *);
357 int (*create_context)(struct nouveau_channel *);
358 void (*destroy_context)(struct nouveau_channel *);
359 int (*load_context)(struct nouveau_channel *);
360 int (*unload_context)(struct drm_device *);
361 void (*tlb_flush)(struct drm_device *dev);
362
363 void (*set_tile_region)(struct drm_device *dev, int i);
364 };
365
366 struct nouveau_display_engine {
367 int (*early_init)(struct drm_device *);
368 void (*late_takedown)(struct drm_device *);
369 int (*create)(struct drm_device *);
370 int (*init)(struct drm_device *);
371 void (*destroy)(struct drm_device *);
372 };
373
374 struct nouveau_gpio_engine {
375 int (*init)(struct drm_device *);
376 void (*takedown)(struct drm_device *);
377
378 int (*get)(struct drm_device *, enum dcb_gpio_tag);
379 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
380
381 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
382 };
383
384 struct nouveau_pm_voltage_level {
385 u8 voltage;
386 u8 vid;
387 };
388
389 struct nouveau_pm_voltage {
390 bool supported;
391 u8 vid_mask;
392
393 struct nouveau_pm_voltage_level *level;
394 int nr_level;
395 };
396
397 #define NOUVEAU_PM_MAX_LEVEL 8
398 struct nouveau_pm_level {
399 struct device_attribute dev_attr;
400 char name[32];
401 int id;
402
403 u32 core;
404 u32 memory;
405 u32 shader;
406 u32 unk05;
407
408 u8 voltage;
409 u8 fanspeed;
410
411 u16 memscript;
412 };
413
414 struct nouveau_pm_temp_sensor_constants {
415 u16 offset_constant;
416 s16 offset_mult;
417 u16 offset_div;
418 u16 slope_mult;
419 u16 slope_div;
420 };
421
422 struct nouveau_pm_threshold_temp {
423 s16 critical;
424 s16 down_clock;
425 s16 fan_boost;
426 };
427
428 struct nouveau_pm_memtiming {
429 u32 reg_100220;
430 u32 reg_100224;
431 u32 reg_100228;
432 u32 reg_10022c;
433 u32 reg_100230;
434 u32 reg_100234;
435 u32 reg_100238;
436 u32 reg_10023c;
437 };
438
439 struct nouveau_pm_memtimings {
440 bool supported;
441 struct nouveau_pm_memtiming *timing;
442 int nr_timing;
443 };
444
445 struct nouveau_pm_engine {
446 struct nouveau_pm_voltage voltage;
447 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
448 int nr_perflvl;
449 struct nouveau_pm_memtimings memtimings;
450 struct nouveau_pm_temp_sensor_constants sensor_constants;
451 struct nouveau_pm_threshold_temp threshold_temp;
452
453 struct nouveau_pm_level boot;
454 struct nouveau_pm_level *cur;
455
456 struct device *hwmon;
457 struct notifier_block acpi_nb;
458
459 int (*clock_get)(struct drm_device *, u32 id);
460 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
461 u32 id, int khz);
462 void (*clock_set)(struct drm_device *, void *);
463 int (*voltage_get)(struct drm_device *);
464 int (*voltage_set)(struct drm_device *, int voltage);
465 int (*fanspeed_get)(struct drm_device *);
466 int (*fanspeed_set)(struct drm_device *, int fanspeed);
467 int (*temp_get)(struct drm_device *);
468 };
469
470 struct nouveau_crypt_engine {
471 bool registered;
472
473 int (*init)(struct drm_device *);
474 void (*takedown)(struct drm_device *);
475 int (*create_context)(struct nouveau_channel *);
476 void (*destroy_context)(struct nouveau_channel *);
477 void (*tlb_flush)(struct drm_device *dev);
478 };
479
480 struct nouveau_engine {
481 struct nouveau_instmem_engine instmem;
482 struct nouveau_mc_engine mc;
483 struct nouveau_timer_engine timer;
484 struct nouveau_fb_engine fb;
485 struct nouveau_pgraph_engine graph;
486 struct nouveau_fifo_engine fifo;
487 struct nouveau_display_engine display;
488 struct nouveau_gpio_engine gpio;
489 struct nouveau_pm_engine pm;
490 struct nouveau_crypt_engine crypt;
491 };
492
493 struct nouveau_pll_vals {
494 union {
495 struct {
496 #ifdef __BIG_ENDIAN
497 uint8_t N1, M1, N2, M2;
498 #else
499 uint8_t M1, N1, M2, N2;
500 #endif
501 };
502 struct {
503 uint16_t NM1, NM2;
504 } __attribute__((packed));
505 };
506 int log2P;
507
508 int refclk;
509 };
510
511 enum nv04_fp_display_regs {
512 FP_DISPLAY_END,
513 FP_TOTAL,
514 FP_CRTC,
515 FP_SYNC_START,
516 FP_SYNC_END,
517 FP_VALID_START,
518 FP_VALID_END
519 };
520
521 struct nv04_crtc_reg {
522 unsigned char MiscOutReg;
523 uint8_t CRTC[0xa0];
524 uint8_t CR58[0x10];
525 uint8_t Sequencer[5];
526 uint8_t Graphics[9];
527 uint8_t Attribute[21];
528 unsigned char DAC[768];
529
530 /* PCRTC regs */
531 uint32_t fb_start;
532 uint32_t crtc_cfg;
533 uint32_t cursor_cfg;
534 uint32_t gpio_ext;
535 uint32_t crtc_830;
536 uint32_t crtc_834;
537 uint32_t crtc_850;
538 uint32_t crtc_eng_ctrl;
539
540 /* PRAMDAC regs */
541 uint32_t nv10_cursync;
542 struct nouveau_pll_vals pllvals;
543 uint32_t ramdac_gen_ctrl;
544 uint32_t ramdac_630;
545 uint32_t ramdac_634;
546 uint32_t tv_setup;
547 uint32_t tv_vtotal;
548 uint32_t tv_vskew;
549 uint32_t tv_vsync_delay;
550 uint32_t tv_htotal;
551 uint32_t tv_hskew;
552 uint32_t tv_hsync_delay;
553 uint32_t tv_hsync_delay2;
554 uint32_t fp_horiz_regs[7];
555 uint32_t fp_vert_regs[7];
556 uint32_t dither;
557 uint32_t fp_control;
558 uint32_t dither_regs[6];
559 uint32_t fp_debug_0;
560 uint32_t fp_debug_1;
561 uint32_t fp_debug_2;
562 uint32_t fp_margin_color;
563 uint32_t ramdac_8c0;
564 uint32_t ramdac_a20;
565 uint32_t ramdac_a24;
566 uint32_t ramdac_a34;
567 uint32_t ctv_regs[38];
568 };
569
570 struct nv04_output_reg {
571 uint32_t output;
572 int head;
573 };
574
575 struct nv04_mode_state {
576 struct nv04_crtc_reg crtc_reg[2];
577 uint32_t pllsel;
578 uint32_t sel_clk;
579 };
580
581 enum nouveau_card_type {
582 NV_04 = 0x00,
583 NV_10 = 0x10,
584 NV_20 = 0x20,
585 NV_30 = 0x30,
586 NV_40 = 0x40,
587 NV_50 = 0x50,
588 NV_C0 = 0xc0,
589 };
590
591 struct drm_nouveau_private {
592 struct drm_device *dev;
593
594 /* the card type, takes NV_* as values */
595 enum nouveau_card_type card_type;
596 /* exact chipset, derived from NV_PMC_BOOT_0 */
597 int chipset;
598 int flags;
599
600 void __iomem *mmio;
601
602 spinlock_t ramin_lock;
603 void __iomem *ramin;
604 u32 ramin_size;
605 u32 ramin_base;
606 bool ramin_available;
607 struct drm_mm ramin_heap;
608 struct list_head gpuobj_list;
609 struct list_head classes;
610
611 struct nouveau_bo *vga_ram;
612
613 /* interrupt handling */
614 bool msi_enabled;
615 struct workqueue_struct *wq;
616 struct work_struct irq_work;
617 struct work_struct hpd_work;
618
619 struct {
620 spinlock_t lock;
621 uint32_t hpd0_bits;
622 uint32_t hpd1_bits;
623 } hpd_state;
624
625 struct list_head vbl_waiting;
626
627 struct {
628 struct drm_global_reference mem_global_ref;
629 struct ttm_bo_global_ref bo_global_ref;
630 struct ttm_bo_device bdev;
631 atomic_t validate_sequence;
632 } ttm;
633
634 struct {
635 spinlock_t lock;
636 struct drm_mm heap;
637 struct nouveau_bo *bo;
638 } fence;
639
640 struct {
641 spinlock_t lock;
642 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
643 } channels;
644
645 struct nouveau_engine engine;
646 struct nouveau_channel *channel;
647
648 /* For PFIFO and PGRAPH. */
649 spinlock_t context_switch_lock;
650
651 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
652 struct nouveau_ramht *ramht;
653 struct nouveau_gpuobj *ramfc;
654 struct nouveau_gpuobj *ramro;
655
656 uint32_t ramin_rsvd_vram;
657
658 struct {
659 enum {
660 NOUVEAU_GART_NONE = 0,
661 NOUVEAU_GART_AGP,
662 NOUVEAU_GART_SGDMA
663 } type;
664 uint64_t aper_base;
665 uint64_t aper_size;
666 uint64_t aper_free;
667
668 struct nouveau_gpuobj *sg_ctxdma;
669 struct page *sg_dummy_page;
670 dma_addr_t sg_dummy_bus;
671 } gart_info;
672
673 /* nv10-nv40 tiling regions */
674 struct {
675 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
676 spinlock_t lock;
677 } tile;
678
679 /* VRAM/fb configuration */
680 uint64_t vram_size;
681 uint64_t vram_sys_base;
682 u32 vram_rblock_size;
683
684 uint64_t fb_phys;
685 uint64_t fb_available_size;
686 uint64_t fb_mappable_pages;
687 uint64_t fb_aper_free;
688 int fb_mtrr;
689
690 /* G8x/G9x virtual address space */
691 uint64_t vm_gart_base;
692 uint64_t vm_gart_size;
693 uint64_t vm_vram_base;
694 uint64_t vm_vram_size;
695 uint64_t vm_end;
696 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
697 int vm_vram_pt_nr;
698
699 struct nvbios vbios;
700
701 struct nv04_mode_state mode_reg;
702 struct nv04_mode_state saved_reg;
703 uint32_t saved_vga_font[4][16384];
704 uint32_t crtc_owner;
705 uint32_t dac_users[4];
706
707 struct nouveau_suspend_resume {
708 uint32_t *ramin_copy;
709 } susres;
710
711 struct backlight_device *backlight;
712
713 struct nouveau_channel *evo;
714 u32 evo_alloc;
715 struct {
716 struct dcb_entry *dcb;
717 u16 script;
718 u32 pclk;
719 } evo_irq;
720
721 struct {
722 struct dentry *channel_root;
723 } debugfs;
724
725 struct nouveau_fbdev *nfbdev;
726 struct apertures_struct *apertures;
727 };
728
729 static inline struct drm_nouveau_private *
730 nouveau_private(struct drm_device *dev)
731 {
732 return dev->dev_private;
733 }
734
735 static inline struct drm_nouveau_private *
736 nouveau_bdev(struct ttm_bo_device *bd)
737 {
738 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
739 }
740
741 static inline int
742 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
743 {
744 struct nouveau_bo *prev;
745
746 if (!pnvbo)
747 return -EINVAL;
748 prev = *pnvbo;
749
750 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
751 if (prev) {
752 struct ttm_buffer_object *bo = &prev->bo;
753
754 ttm_bo_unref(&bo);
755 }
756
757 return 0;
758 }
759
760 /* nouveau_drv.c */
761 extern int nouveau_agpmode;
762 extern int nouveau_duallink;
763 extern int nouveau_uscript_lvds;
764 extern int nouveau_uscript_tmds;
765 extern int nouveau_vram_pushbuf;
766 extern int nouveau_vram_notify;
767 extern int nouveau_fbpercrtc;
768 extern int nouveau_tv_disable;
769 extern char *nouveau_tv_norm;
770 extern int nouveau_reg_debug;
771 extern char *nouveau_vbios;
772 extern int nouveau_ignorelid;
773 extern int nouveau_nofbaccel;
774 extern int nouveau_noaccel;
775 extern int nouveau_force_post;
776 extern int nouveau_override_conntype;
777 extern char *nouveau_perflvl;
778 extern int nouveau_perflvl_wr;
779 extern int nouveau_msi;
780
781 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
782 extern int nouveau_pci_resume(struct pci_dev *pdev);
783
784 /* nouveau_state.c */
785 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
786 extern int nouveau_load(struct drm_device *, unsigned long flags);
787 extern int nouveau_firstopen(struct drm_device *);
788 extern void nouveau_lastclose(struct drm_device *);
789 extern int nouveau_unload(struct drm_device *);
790 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
791 struct drm_file *);
792 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
793 struct drm_file *);
794 extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
795 uint32_t reg, uint32_t mask, uint32_t val);
796 extern bool nouveau_wait_for_idle(struct drm_device *);
797 extern int nouveau_card_init(struct drm_device *);
798
799 /* nouveau_mem.c */
800 extern int nouveau_mem_vram_init(struct drm_device *);
801 extern void nouveau_mem_vram_fini(struct drm_device *);
802 extern int nouveau_mem_gart_init(struct drm_device *);
803 extern void nouveau_mem_gart_fini(struct drm_device *);
804 extern int nouveau_mem_init_agp(struct drm_device *);
805 extern int nouveau_mem_reset_agp(struct drm_device *);
806 extern void nouveau_mem_close(struct drm_device *);
807 extern struct nouveau_tile_reg *nv10_mem_set_tiling(
808 struct drm_device *dev, uint32_t addr, uint32_t size,
809 uint32_t pitch, uint32_t flags);
810 extern void nv10_mem_put_tile_region(struct drm_device *dev,
811 struct nouveau_tile_reg *tile,
812 struct nouveau_fence *fence);
813 extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
814 uint32_t size, uint32_t flags,
815 uint64_t phys);
816 extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
817 uint32_t size);
818
819 /* nouveau_notifier.c */
820 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
821 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
822 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
823 int cout, uint32_t *offset);
824 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
825 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
826 struct drm_file *);
827 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
828 struct drm_file *);
829
830 /* nouveau_channel.c */
831 extern struct drm_ioctl_desc nouveau_ioctls[];
832 extern int nouveau_max_ioctl;
833 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
834 extern int nouveau_channel_alloc(struct drm_device *dev,
835 struct nouveau_channel **chan,
836 struct drm_file *file_priv,
837 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
838 extern struct nouveau_channel *
839 nouveau_channel_get_unlocked(struct nouveau_channel *);
840 extern struct nouveau_channel *
841 nouveau_channel_get(struct drm_device *, struct drm_file *, int id);
842 extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
843 extern void nouveau_channel_put(struct nouveau_channel **);
844 extern void nouveau_channel_ref(struct nouveau_channel *chan,
845 struct nouveau_channel **pchan);
846
847 /* nouveau_object.c */
848 #define NVOBJ_CLASS(d,c,e) do { \
849 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
850 if (ret) \
851 return ret; \
852 } while(0)
853
854 #define NVOBJ_MTHD(d,c,m,e) do { \
855 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
856 if (ret) \
857 return ret; \
858 } while(0)
859
860 extern int nouveau_gpuobj_early_init(struct drm_device *);
861 extern int nouveau_gpuobj_init(struct drm_device *);
862 extern void nouveau_gpuobj_takedown(struct drm_device *);
863 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
864 extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
865 extern void nouveau_gpuobj_resume(struct drm_device *dev);
866 extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
867 extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
868 int (*exec)(struct nouveau_channel *,
869 u32 class, u32 mthd, u32 data));
870 extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
871 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
872 uint32_t vram_h, uint32_t tt_h);
873 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
874 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
875 uint32_t size, int align, uint32_t flags,
876 struct nouveau_gpuobj **);
877 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
878 struct nouveau_gpuobj **);
879 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
880 u32 size, u32 flags,
881 struct nouveau_gpuobj **);
882 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
883 uint64_t offset, uint64_t size, int access,
884 int target, struct nouveau_gpuobj **);
885 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
886 uint64_t offset, uint64_t size,
887 int access, struct nouveau_gpuobj **,
888 uint32_t *o_ret);
889 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
890 struct nouveau_gpuobj **);
891 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
892 struct drm_file *);
893 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
894 struct drm_file *);
895
896 /* nouveau_irq.c */
897 extern int nouveau_irq_init(struct drm_device *);
898 extern void nouveau_irq_fini(struct drm_device *);
899 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
900 extern void nouveau_irq_preinstall(struct drm_device *);
901 extern int nouveau_irq_postinstall(struct drm_device *);
902 extern void nouveau_irq_uninstall(struct drm_device *);
903
904 /* nouveau_sgdma.c */
905 extern int nouveau_sgdma_init(struct drm_device *);
906 extern void nouveau_sgdma_takedown(struct drm_device *);
907 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
908 uint32_t *page);
909 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
910
911 /* nouveau_debugfs.c */
912 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
913 extern int nouveau_debugfs_init(struct drm_minor *);
914 extern void nouveau_debugfs_takedown(struct drm_minor *);
915 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
916 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
917 #else
918 static inline int
919 nouveau_debugfs_init(struct drm_minor *minor)
920 {
921 return 0;
922 }
923
924 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
925 {
926 }
927
928 static inline int
929 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
930 {
931 return 0;
932 }
933
934 static inline void
935 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
936 {
937 }
938 #endif
939
940 /* nouveau_dma.c */
941 extern void nouveau_dma_pre_init(struct nouveau_channel *);
942 extern int nouveau_dma_init(struct nouveau_channel *);
943 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
944
945 /* nouveau_acpi.c */
946 #define ROM_BIOS_PAGE 4096
947 #if defined(CONFIG_ACPI)
948 void nouveau_register_dsm_handler(void);
949 void nouveau_unregister_dsm_handler(void);
950 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
951 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
952 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
953 #else
954 static inline void nouveau_register_dsm_handler(void) {}
955 static inline void nouveau_unregister_dsm_handler(void) {}
956 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
957 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
958 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
959 #endif
960
961 /* nouveau_backlight.c */
962 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
963 extern int nouveau_backlight_init(struct drm_device *);
964 extern void nouveau_backlight_exit(struct drm_device *);
965 #else
966 static inline int nouveau_backlight_init(struct drm_device *dev)
967 {
968 return 0;
969 }
970
971 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
972 #endif
973
974 /* nouveau_bios.c */
975 extern int nouveau_bios_init(struct drm_device *);
976 extern void nouveau_bios_takedown(struct drm_device *dev);
977 extern int nouveau_run_vbios_init(struct drm_device *);
978 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
979 struct dcb_entry *);
980 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
981 enum dcb_gpio_tag);
982 extern struct dcb_connector_table_entry *
983 nouveau_bios_connector_entry(struct drm_device *, int index);
984 extern u32 get_pll_register(struct drm_device *, enum pll_types);
985 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
986 struct pll_lims *);
987 extern int nouveau_bios_run_display_table(struct drm_device *,
988 struct dcb_entry *,
989 uint32_t script, int pxclk);
990 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
991 int *length);
992 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
993 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
994 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
995 bool *dl, bool *if_is_24bit);
996 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
997 int head, int pxclk);
998 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
999 enum LVDS_script, int pxclk);
1000
1001 /* nouveau_ttm.c */
1002 int nouveau_ttm_global_init(struct drm_nouveau_private *);
1003 void nouveau_ttm_global_release(struct drm_nouveau_private *);
1004 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
1005
1006 /* nouveau_dp.c */
1007 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
1008 uint8_t *data, int data_nr);
1009 bool nouveau_dp_detect(struct drm_encoder *);
1010 bool nouveau_dp_link_train(struct drm_encoder *);
1011
1012 /* nv04_fb.c */
1013 extern int nv04_fb_init(struct drm_device *);
1014 extern void nv04_fb_takedown(struct drm_device *);
1015
1016 /* nv10_fb.c */
1017 extern int nv10_fb_init(struct drm_device *);
1018 extern void nv10_fb_takedown(struct drm_device *);
1019 extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
1020 uint32_t addr, uint32_t size,
1021 uint32_t pitch, uint32_t flags);
1022 extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
1023 extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
1024
1025 /* nv30_fb.c */
1026 extern int nv30_fb_init(struct drm_device *);
1027 extern void nv30_fb_takedown(struct drm_device *);
1028 extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
1029 uint32_t addr, uint32_t size,
1030 uint32_t pitch, uint32_t flags);
1031 extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
1032
1033 /* nv40_fb.c */
1034 extern int nv40_fb_init(struct drm_device *);
1035 extern void nv40_fb_takedown(struct drm_device *);
1036 extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
1037
1038 /* nv50_fb.c */
1039 extern int nv50_fb_init(struct drm_device *);
1040 extern void nv50_fb_takedown(struct drm_device *);
1041 extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
1042
1043 /* nvc0_fb.c */
1044 extern int nvc0_fb_init(struct drm_device *);
1045 extern void nvc0_fb_takedown(struct drm_device *);
1046
1047 /* nv04_fifo.c */
1048 extern int nv04_fifo_init(struct drm_device *);
1049 extern void nv04_fifo_disable(struct drm_device *);
1050 extern void nv04_fifo_enable(struct drm_device *);
1051 extern bool nv04_fifo_reassign(struct drm_device *, bool);
1052 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
1053 extern int nv04_fifo_channel_id(struct drm_device *);
1054 extern int nv04_fifo_create_context(struct nouveau_channel *);
1055 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1056 extern int nv04_fifo_load_context(struct nouveau_channel *);
1057 extern int nv04_fifo_unload_context(struct drm_device *);
1058
1059 /* nv10_fifo.c */
1060 extern int nv10_fifo_init(struct drm_device *);
1061 extern int nv10_fifo_channel_id(struct drm_device *);
1062 extern int nv10_fifo_create_context(struct nouveau_channel *);
1063 extern int nv10_fifo_load_context(struct nouveau_channel *);
1064 extern int nv10_fifo_unload_context(struct drm_device *);
1065
1066 /* nv40_fifo.c */
1067 extern int nv40_fifo_init(struct drm_device *);
1068 extern int nv40_fifo_create_context(struct nouveau_channel *);
1069 extern int nv40_fifo_load_context(struct nouveau_channel *);
1070 extern int nv40_fifo_unload_context(struct drm_device *);
1071
1072 /* nv50_fifo.c */
1073 extern int nv50_fifo_init(struct drm_device *);
1074 extern void nv50_fifo_takedown(struct drm_device *);
1075 extern int nv50_fifo_channel_id(struct drm_device *);
1076 extern int nv50_fifo_create_context(struct nouveau_channel *);
1077 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1078 extern int nv50_fifo_load_context(struct nouveau_channel *);
1079 extern int nv50_fifo_unload_context(struct drm_device *);
1080 extern void nv50_fifo_tlb_flush(struct drm_device *dev);
1081
1082 /* nvc0_fifo.c */
1083 extern int nvc0_fifo_init(struct drm_device *);
1084 extern void nvc0_fifo_takedown(struct drm_device *);
1085 extern void nvc0_fifo_disable(struct drm_device *);
1086 extern void nvc0_fifo_enable(struct drm_device *);
1087 extern bool nvc0_fifo_reassign(struct drm_device *, bool);
1088 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1089 extern int nvc0_fifo_channel_id(struct drm_device *);
1090 extern int nvc0_fifo_create_context(struct nouveau_channel *);
1091 extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1092 extern int nvc0_fifo_load_context(struct nouveau_channel *);
1093 extern int nvc0_fifo_unload_context(struct drm_device *);
1094
1095 /* nv04_graph.c */
1096 extern int nv04_graph_init(struct drm_device *);
1097 extern void nv04_graph_takedown(struct drm_device *);
1098 extern void nv04_graph_fifo_access(struct drm_device *, bool);
1099 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1100 extern int nv04_graph_create_context(struct nouveau_channel *);
1101 extern void nv04_graph_destroy_context(struct nouveau_channel *);
1102 extern int nv04_graph_load_context(struct nouveau_channel *);
1103 extern int nv04_graph_unload_context(struct drm_device *);
1104 extern void nv04_graph_context_switch(struct drm_device *);
1105 extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1106 u32 class, u32 mthd, u32 data);
1107
1108 /* nv10_graph.c */
1109 extern int nv10_graph_init(struct drm_device *);
1110 extern void nv10_graph_takedown(struct drm_device *);
1111 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1112 extern int nv10_graph_create_context(struct nouveau_channel *);
1113 extern void nv10_graph_destroy_context(struct nouveau_channel *);
1114 extern int nv10_graph_load_context(struct nouveau_channel *);
1115 extern int nv10_graph_unload_context(struct drm_device *);
1116 extern void nv10_graph_context_switch(struct drm_device *);
1117 extern void nv10_graph_set_tile_region(struct drm_device *dev, int i);
1118
1119 /* nv20_graph.c */
1120 extern int nv20_graph_create_context(struct nouveau_channel *);
1121 extern void nv20_graph_destroy_context(struct nouveau_channel *);
1122 extern int nv20_graph_load_context(struct nouveau_channel *);
1123 extern int nv20_graph_unload_context(struct drm_device *);
1124 extern int nv20_graph_init(struct drm_device *);
1125 extern void nv20_graph_takedown(struct drm_device *);
1126 extern int nv30_graph_init(struct drm_device *);
1127 extern void nv20_graph_set_tile_region(struct drm_device *dev, int i);
1128
1129 /* nv40_graph.c */
1130 extern int nv40_graph_init(struct drm_device *);
1131 extern void nv40_graph_takedown(struct drm_device *);
1132 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1133 extern int nv40_graph_create_context(struct nouveau_channel *);
1134 extern void nv40_graph_destroy_context(struct nouveau_channel *);
1135 extern int nv40_graph_load_context(struct nouveau_channel *);
1136 extern int nv40_graph_unload_context(struct drm_device *);
1137 extern void nv40_grctx_init(struct nouveau_grctx *);
1138 extern void nv40_graph_set_tile_region(struct drm_device *dev, int i);
1139
1140 /* nv50_graph.c */
1141 extern int nv50_graph_init(struct drm_device *);
1142 extern void nv50_graph_takedown(struct drm_device *);
1143 extern void nv50_graph_fifo_access(struct drm_device *, bool);
1144 extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1145 extern int nv50_graph_create_context(struct nouveau_channel *);
1146 extern void nv50_graph_destroy_context(struct nouveau_channel *);
1147 extern int nv50_graph_load_context(struct nouveau_channel *);
1148 extern int nv50_graph_unload_context(struct drm_device *);
1149 extern void nv50_graph_context_switch(struct drm_device *);
1150 extern int nv50_grctx_init(struct nouveau_grctx *);
1151 extern void nv50_graph_tlb_flush(struct drm_device *dev);
1152 extern void nv86_graph_tlb_flush(struct drm_device *dev);
1153
1154 /* nvc0_graph.c */
1155 extern int nvc0_graph_init(struct drm_device *);
1156 extern void nvc0_graph_takedown(struct drm_device *);
1157 extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1158 extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1159 extern int nvc0_graph_create_context(struct nouveau_channel *);
1160 extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1161 extern int nvc0_graph_load_context(struct nouveau_channel *);
1162 extern int nvc0_graph_unload_context(struct drm_device *);
1163
1164 /* nv84_crypt.c */
1165 extern int nv84_crypt_init(struct drm_device *dev);
1166 extern void nv84_crypt_fini(struct drm_device *dev);
1167 extern int nv84_crypt_create_context(struct nouveau_channel *);
1168 extern void nv84_crypt_destroy_context(struct nouveau_channel *);
1169 extern void nv84_crypt_tlb_flush(struct drm_device *dev);
1170
1171 /* nv04_instmem.c */
1172 extern int nv04_instmem_init(struct drm_device *);
1173 extern void nv04_instmem_takedown(struct drm_device *);
1174 extern int nv04_instmem_suspend(struct drm_device *);
1175 extern void nv04_instmem_resume(struct drm_device *);
1176 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1177 u32 *size, u32 align);
1178 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1179 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1180 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1181 extern void nv04_instmem_flush(struct drm_device *);
1182
1183 /* nv50_instmem.c */
1184 extern int nv50_instmem_init(struct drm_device *);
1185 extern void nv50_instmem_takedown(struct drm_device *);
1186 extern int nv50_instmem_suspend(struct drm_device *);
1187 extern void nv50_instmem_resume(struct drm_device *);
1188 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1189 u32 *size, u32 align);
1190 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1191 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1192 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1193 extern void nv50_instmem_flush(struct drm_device *);
1194 extern void nv84_instmem_flush(struct drm_device *);
1195 extern void nv50_vm_flush(struct drm_device *, int engine);
1196
1197 /* nvc0_instmem.c */
1198 extern int nvc0_instmem_init(struct drm_device *);
1199 extern void nvc0_instmem_takedown(struct drm_device *);
1200 extern int nvc0_instmem_suspend(struct drm_device *);
1201 extern void nvc0_instmem_resume(struct drm_device *);
1202 extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1203 u32 *size, u32 align);
1204 extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1205 extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1206 extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1207 extern void nvc0_instmem_flush(struct drm_device *);
1208
1209 /* nv04_mc.c */
1210 extern int nv04_mc_init(struct drm_device *);
1211 extern void nv04_mc_takedown(struct drm_device *);
1212
1213 /* nv40_mc.c */
1214 extern int nv40_mc_init(struct drm_device *);
1215 extern void nv40_mc_takedown(struct drm_device *);
1216
1217 /* nv50_mc.c */
1218 extern int nv50_mc_init(struct drm_device *);
1219 extern void nv50_mc_takedown(struct drm_device *);
1220
1221 /* nv04_timer.c */
1222 extern int nv04_timer_init(struct drm_device *);
1223 extern uint64_t nv04_timer_read(struct drm_device *);
1224 extern void nv04_timer_takedown(struct drm_device *);
1225
1226 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1227 unsigned long arg);
1228
1229 /* nv04_dac.c */
1230 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1231 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1232 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1233 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1234 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1235
1236 /* nv04_dfp.c */
1237 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1238 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1239 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1240 int head, bool dl);
1241 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1242 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1243
1244 /* nv04_tv.c */
1245 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1246 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1247
1248 /* nv17_tv.c */
1249 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1250
1251 /* nv04_display.c */
1252 extern int nv04_display_early_init(struct drm_device *);
1253 extern void nv04_display_late_takedown(struct drm_device *);
1254 extern int nv04_display_create(struct drm_device *);
1255 extern int nv04_display_init(struct drm_device *);
1256 extern void nv04_display_destroy(struct drm_device *);
1257
1258 /* nv04_crtc.c */
1259 extern int nv04_crtc_create(struct drm_device *, int index);
1260
1261 /* nouveau_bo.c */
1262 extern struct ttm_bo_driver nouveau_bo_driver;
1263 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1264 int size, int align, uint32_t flags,
1265 uint32_t tile_mode, uint32_t tile_flags,
1266 bool no_vm, bool mappable, struct nouveau_bo **);
1267 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1268 extern int nouveau_bo_unpin(struct nouveau_bo *);
1269 extern int nouveau_bo_map(struct nouveau_bo *);
1270 extern void nouveau_bo_unmap(struct nouveau_bo *);
1271 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1272 uint32_t busy);
1273 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1274 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1275 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1276 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1277 extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
1278
1279 /* nouveau_fence.c */
1280 struct nouveau_fence;
1281 extern int nouveau_fence_init(struct drm_device *);
1282 extern void nouveau_fence_fini(struct drm_device *);
1283 extern int nouveau_fence_channel_init(struct nouveau_channel *);
1284 extern void nouveau_fence_channel_fini(struct nouveau_channel *);
1285 extern void nouveau_fence_update(struct nouveau_channel *);
1286 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1287 bool emit);
1288 extern int nouveau_fence_emit(struct nouveau_fence *);
1289 extern void nouveau_fence_work(struct nouveau_fence *fence,
1290 void (*work)(void *priv, bool signalled),
1291 void *priv);
1292 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1293
1294 extern bool __nouveau_fence_signalled(void *obj, void *arg);
1295 extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1296 extern int __nouveau_fence_flush(void *obj, void *arg);
1297 extern void __nouveau_fence_unref(void **obj);
1298 extern void *__nouveau_fence_ref(void *obj);
1299
1300 static inline bool nouveau_fence_signalled(struct nouveau_fence *obj)
1301 {
1302 return __nouveau_fence_signalled(obj, NULL);
1303 }
1304 static inline int
1305 nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr)
1306 {
1307 return __nouveau_fence_wait(obj, NULL, lazy, intr);
1308 }
1309 extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
1310 static inline int nouveau_fence_flush(struct nouveau_fence *obj)
1311 {
1312 return __nouveau_fence_flush(obj, NULL);
1313 }
1314 static inline void nouveau_fence_unref(struct nouveau_fence **obj)
1315 {
1316 __nouveau_fence_unref((void **)obj);
1317 }
1318 static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj)
1319 {
1320 return __nouveau_fence_ref(obj);
1321 }
1322
1323 /* nouveau_gem.c */
1324 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1325 int size, int align, uint32_t flags,
1326 uint32_t tile_mode, uint32_t tile_flags,
1327 bool no_vm, bool mappable, struct nouveau_bo **);
1328 extern int nouveau_gem_object_new(struct drm_gem_object *);
1329 extern void nouveau_gem_object_del(struct drm_gem_object *);
1330 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1331 struct drm_file *);
1332 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1333 struct drm_file *);
1334 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1335 struct drm_file *);
1336 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1337 struct drm_file *);
1338 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1339 struct drm_file *);
1340
1341 /* nouveau_display.c */
1342 int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1343 void nouveau_vblank_disable(struct drm_device *dev, int crtc);
1344 int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1345 struct drm_pending_vblank_event *event);
1346 int nouveau_finish_page_flip(struct nouveau_channel *,
1347 struct nouveau_page_flip_state *);
1348
1349 /* nv10_gpio.c */
1350 int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1351 int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1352
1353 /* nv50_gpio.c */
1354 int nv50_gpio_init(struct drm_device *dev);
1355 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1356 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1357 void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
1358
1359 /* nv50_calc. */
1360 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1361 int *N1, int *M1, int *N2, int *M2, int *P);
1362 int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1363 int clk, int *N, int *fN, int *M, int *P);
1364
1365 #ifndef ioread32_native
1366 #ifdef __BIG_ENDIAN
1367 #define ioread16_native ioread16be
1368 #define iowrite16_native iowrite16be
1369 #define ioread32_native ioread32be
1370 #define iowrite32_native iowrite32be
1371 #else /* def __BIG_ENDIAN */
1372 #define ioread16_native ioread16
1373 #define iowrite16_native iowrite16
1374 #define ioread32_native ioread32
1375 #define iowrite32_native iowrite32
1376 #endif /* def __BIG_ENDIAN else */
1377 #endif /* !ioread32_native */
1378
1379 /* channel control reg access */
1380 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1381 {
1382 return ioread32_native(chan->user + reg);
1383 }
1384
1385 static inline void nvchan_wr32(struct nouveau_channel *chan,
1386 unsigned reg, u32 val)
1387 {
1388 iowrite32_native(val, chan->user + reg);
1389 }
1390
1391 /* register access */
1392 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1393 {
1394 struct drm_nouveau_private *dev_priv = dev->dev_private;
1395 return ioread32_native(dev_priv->mmio + reg);
1396 }
1397
1398 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1399 {
1400 struct drm_nouveau_private *dev_priv = dev->dev_private;
1401 iowrite32_native(val, dev_priv->mmio + reg);
1402 }
1403
1404 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1405 {
1406 u32 tmp = nv_rd32(dev, reg);
1407 nv_wr32(dev, reg, (tmp & ~mask) | val);
1408 return tmp;
1409 }
1410
1411 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1412 {
1413 struct drm_nouveau_private *dev_priv = dev->dev_private;
1414 return ioread8(dev_priv->mmio + reg);
1415 }
1416
1417 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1418 {
1419 struct drm_nouveau_private *dev_priv = dev->dev_private;
1420 iowrite8(val, dev_priv->mmio + reg);
1421 }
1422
1423 #define nv_wait(dev, reg, mask, val) \
1424 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1425
1426 /* PRAMIN access */
1427 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1428 {
1429 struct drm_nouveau_private *dev_priv = dev->dev_private;
1430 return ioread32_native(dev_priv->ramin + offset);
1431 }
1432
1433 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1434 {
1435 struct drm_nouveau_private *dev_priv = dev->dev_private;
1436 iowrite32_native(val, dev_priv->ramin + offset);
1437 }
1438
1439 /* object access */
1440 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1441 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1442
1443 /*
1444 * Logging
1445 * Argument d is (struct drm_device *).
1446 */
1447 #define NV_PRINTK(level, d, fmt, arg...) \
1448 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1449 pci_name(d->pdev), ##arg)
1450 #ifndef NV_DEBUG_NOTRACE
1451 #define NV_DEBUG(d, fmt, arg...) do { \
1452 if (drm_debug & DRM_UT_DRIVER) { \
1453 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1454 __LINE__, ##arg); \
1455 } \
1456 } while (0)
1457 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1458 if (drm_debug & DRM_UT_KMS) { \
1459 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1460 __LINE__, ##arg); \
1461 } \
1462 } while (0)
1463 #else
1464 #define NV_DEBUG(d, fmt, arg...) do { \
1465 if (drm_debug & DRM_UT_DRIVER) \
1466 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1467 } while (0)
1468 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1469 if (drm_debug & DRM_UT_KMS) \
1470 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1471 } while (0)
1472 #endif
1473 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1474 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1475 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1476 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1477 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1478
1479 /* nouveau_reg_debug bitmask */
1480 enum {
1481 NOUVEAU_REG_DEBUG_MC = 0x1,
1482 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1483 NOUVEAU_REG_DEBUG_FB = 0x4,
1484 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1485 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1486 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1487 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1488 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1489 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1490 NOUVEAU_REG_DEBUG_EVO = 0x200,
1491 };
1492
1493 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1494 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1495 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1496 } while (0)
1497
1498 static inline bool
1499 nv_two_heads(struct drm_device *dev)
1500 {
1501 struct drm_nouveau_private *dev_priv = dev->dev_private;
1502 const int impl = dev->pci_device & 0x0ff0;
1503
1504 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1505 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1506 return true;
1507
1508 return false;
1509 }
1510
1511 static inline bool
1512 nv_gf4_disp_arch(struct drm_device *dev)
1513 {
1514 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1515 }
1516
1517 static inline bool
1518 nv_two_reg_pll(struct drm_device *dev)
1519 {
1520 struct drm_nouveau_private *dev_priv = dev->dev_private;
1521 const int impl = dev->pci_device & 0x0ff0;
1522
1523 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1524 return true;
1525 return false;
1526 }
1527
1528 static inline bool
1529 nv_match_device(struct drm_device *dev, unsigned device,
1530 unsigned sub_vendor, unsigned sub_device)
1531 {
1532 return dev->pdev->device == device &&
1533 dev->pdev->subsystem_vendor == sub_vendor &&
1534 dev->pdev->subsystem_device == sub_device;
1535 }
1536
1537 #define NV_SW 0x0000506e
1538 #define NV_SW_DMA_SEMAPHORE 0x00000060
1539 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1540 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1541 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1542 #define NV_SW_YIELD 0x00000080
1543 #define NV_SW_DMA_VBLSEM 0x0000018c
1544 #define NV_SW_VBLSEM_OFFSET 0x00000400
1545 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1546 #define NV_SW_VBLSEM_RELEASE 0x00000408
1547 #define NV_SW_PAGE_FLIP 0x00000500
1548
1549 #endif /* __NOUVEAU_DRV_H__ */
Linux kernel - Deliverables
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