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Merge branch 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
1 /*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
27
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
34
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
38
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
41
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
47
48 struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50 };
51
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
57 #include "nouveau_util.h"
58
59 struct nouveau_grctx;
60 struct nouveau_vram;
61 #include "nouveau_vm.h"
62
63 #define MAX_NUM_DCB_ENTRIES 16
64
65 #define NOUVEAU_MAX_CHANNEL_NR 128
66 #define NOUVEAU_MAX_TILE_NR 15
67
68 struct nouveau_vram {
69 struct drm_device *dev;
70
71 struct nouveau_vma bar_vma;
72 u8 page_shift;
73
74 struct list_head regions;
75 u32 memtype;
76 u64 offset;
77 u64 size;
78 };
79
80 struct nouveau_tile_reg {
81 bool used;
82 uint32_t addr;
83 uint32_t limit;
84 uint32_t pitch;
85 uint32_t zcomp;
86 struct drm_mm_node *tag_mem;
87 struct nouveau_fence *fence;
88 };
89
90 struct nouveau_bo {
91 struct ttm_buffer_object bo;
92 struct ttm_placement placement;
93 u32 placements[3];
94 u32 busy_placements[3];
95 struct ttm_bo_kmap_obj kmap;
96 struct list_head head;
97
98 /* protected by ttm_bo_reserve() */
99 struct drm_file *reserved_by;
100 struct list_head entry;
101 int pbbo_index;
102 bool validate_mapped;
103
104 struct nouveau_channel *channel;
105
106 struct nouveau_vma vma;
107 bool mappable;
108 bool no_vm;
109
110 uint32_t tile_mode;
111 uint32_t tile_flags;
112 struct nouveau_tile_reg *tile;
113
114 struct drm_gem_object *gem;
115 int pin_refcnt;
116 };
117
118 #define nouveau_bo_tile_layout(nvbo) \
119 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
120
121 static inline struct nouveau_bo *
122 nouveau_bo(struct ttm_buffer_object *bo)
123 {
124 return container_of(bo, struct nouveau_bo, bo);
125 }
126
127 static inline struct nouveau_bo *
128 nouveau_gem_object(struct drm_gem_object *gem)
129 {
130 return gem ? gem->driver_private : NULL;
131 }
132
133 /* TODO: submit equivalent to TTM generic API upstream? */
134 static inline void __iomem *
135 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
136 {
137 bool is_iomem;
138 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
139 &nvbo->kmap, &is_iomem);
140 WARN_ON_ONCE(ioptr && !is_iomem);
141 return ioptr;
142 }
143
144 enum nouveau_flags {
145 NV_NFORCE = 0x10000000,
146 NV_NFORCE2 = 0x20000000
147 };
148
149 #define NVOBJ_ENGINE_SW 0
150 #define NVOBJ_ENGINE_GR 1
151 #define NVOBJ_ENGINE_PPP 2
152 #define NVOBJ_ENGINE_COPY 3
153 #define NVOBJ_ENGINE_VP 4
154 #define NVOBJ_ENGINE_CRYPT 5
155 #define NVOBJ_ENGINE_BSP 6
156 #define NVOBJ_ENGINE_DISPLAY 0xcafe0001
157 #define NVOBJ_ENGINE_INT 0xdeadbeef
158
159 #define NVOBJ_FLAG_DONT_MAP (1 << 0)
160 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
161 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
162 #define NVOBJ_FLAG_VM (1 << 3)
163 #define NVOBJ_FLAG_VM_USER (1 << 4)
164
165 #define NVOBJ_CINST_GLOBAL 0xdeadbeef
166
167 struct nouveau_gpuobj {
168 struct drm_device *dev;
169 struct kref refcount;
170 struct list_head list;
171
172 void *node;
173 u32 *suspend;
174
175 uint32_t flags;
176
177 u32 size;
178 u32 pinst;
179 u32 cinst;
180 u64 vinst;
181
182 uint32_t engine;
183 uint32_t class;
184
185 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
186 void *priv;
187 };
188
189 struct nouveau_page_flip_state {
190 struct list_head head;
191 struct drm_pending_vblank_event *event;
192 int crtc, bpp, pitch, x, y;
193 uint64_t offset;
194 };
195
196 enum nouveau_channel_mutex_class {
197 NOUVEAU_UCHANNEL_MUTEX,
198 NOUVEAU_KCHANNEL_MUTEX
199 };
200
201 struct nouveau_channel {
202 struct drm_device *dev;
203 int id;
204
205 /* references to the channel data structure */
206 struct kref ref;
207 /* users of the hardware channel resources, the hardware
208 * context will be kicked off when it reaches zero. */
209 atomic_t users;
210 struct mutex mutex;
211
212 /* owner of this fifo */
213 struct drm_file *file_priv;
214 /* mapping of the fifo itself */
215 struct drm_local_map *map;
216
217 /* mapping of the regs controling the fifo */
218 void __iomem *user;
219 uint32_t user_get;
220 uint32_t user_put;
221
222 /* Fencing */
223 struct {
224 /* lock protects the pending list only */
225 spinlock_t lock;
226 struct list_head pending;
227 uint32_t sequence;
228 uint32_t sequence_ack;
229 atomic_t last_sequence_irq;
230 } fence;
231
232 /* DMA push buffer */
233 struct nouveau_gpuobj *pushbuf;
234 struct nouveau_bo *pushbuf_bo;
235 uint32_t pushbuf_base;
236
237 /* Notifier memory */
238 struct nouveau_bo *notifier_bo;
239 struct drm_mm notifier_heap;
240
241 /* PFIFO context */
242 struct nouveau_gpuobj *ramfc;
243 struct nouveau_gpuobj *cache;
244 void *fifo_priv;
245
246 /* PGRAPH context */
247 /* XXX may be merge 2 pointers as private data ??? */
248 struct nouveau_gpuobj *ramin_grctx;
249 struct nouveau_gpuobj *crypt_ctx;
250 void *pgraph_ctx;
251
252 /* NV50 VM */
253 struct nouveau_vm *vm;
254 struct nouveau_gpuobj *vm_pd;
255
256 /* Objects */
257 struct nouveau_gpuobj *ramin; /* Private instmem */
258 struct drm_mm ramin_heap; /* Private PRAMIN heap */
259 struct nouveau_ramht *ramht; /* Hash table */
260
261 /* GPU object info for stuff used in-kernel (mm_enabled) */
262 uint32_t m2mf_ntfy;
263 uint32_t vram_handle;
264 uint32_t gart_handle;
265 bool accel_done;
266
267 /* Push buffer state (only for drm's channel on !mm_enabled) */
268 struct {
269 int max;
270 int free;
271 int cur;
272 int put;
273 /* access via pushbuf_bo */
274
275 int ib_base;
276 int ib_max;
277 int ib_free;
278 int ib_put;
279 } dma;
280
281 uint32_t sw_subchannel[8];
282
283 struct {
284 struct nouveau_gpuobj *vblsem;
285 uint32_t vblsem_head;
286 uint32_t vblsem_offset;
287 uint32_t vblsem_rval;
288 struct list_head vbl_wait;
289 struct list_head flip;
290 } nvsw;
291
292 struct {
293 bool active;
294 char name[32];
295 struct drm_info_list info;
296 } debugfs;
297 };
298
299 struct nouveau_instmem_engine {
300 void *priv;
301
302 int (*init)(struct drm_device *dev);
303 void (*takedown)(struct drm_device *dev);
304 int (*suspend)(struct drm_device *dev);
305 void (*resume)(struct drm_device *dev);
306
307 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align);
308 void (*put)(struct nouveau_gpuobj *);
309 int (*map)(struct nouveau_gpuobj *);
310 void (*unmap)(struct nouveau_gpuobj *);
311
312 void (*flush)(struct drm_device *);
313 };
314
315 struct nouveau_mc_engine {
316 int (*init)(struct drm_device *dev);
317 void (*takedown)(struct drm_device *dev);
318 };
319
320 struct nouveau_timer_engine {
321 int (*init)(struct drm_device *dev);
322 void (*takedown)(struct drm_device *dev);
323 uint64_t (*read)(struct drm_device *dev);
324 };
325
326 struct nouveau_fb_engine {
327 int num_tiles;
328 struct drm_mm tag_heap;
329 void *priv;
330
331 int (*init)(struct drm_device *dev);
332 void (*takedown)(struct drm_device *dev);
333
334 void (*init_tile_region)(struct drm_device *dev, int i,
335 uint32_t addr, uint32_t size,
336 uint32_t pitch, uint32_t flags);
337 void (*set_tile_region)(struct drm_device *dev, int i);
338 void (*free_tile_region)(struct drm_device *dev, int i);
339 };
340
341 struct nouveau_fifo_engine {
342 void *priv;
343 int channels;
344
345 struct nouveau_gpuobj *playlist[2];
346 int cur_playlist;
347
348 int (*init)(struct drm_device *);
349 void (*takedown)(struct drm_device *);
350
351 void (*disable)(struct drm_device *);
352 void (*enable)(struct drm_device *);
353 bool (*reassign)(struct drm_device *, bool enable);
354 bool (*cache_pull)(struct drm_device *dev, bool enable);
355
356 int (*channel_id)(struct drm_device *);
357
358 int (*create_context)(struct nouveau_channel *);
359 void (*destroy_context)(struct nouveau_channel *);
360 int (*load_context)(struct nouveau_channel *);
361 int (*unload_context)(struct drm_device *);
362 void (*tlb_flush)(struct drm_device *dev);
363 };
364
365 struct nouveau_pgraph_engine {
366 bool accel_blocked;
367 bool registered;
368 int grctx_size;
369 void *priv;
370
371 /* NV2x/NV3x context table (0x400780) */
372 struct nouveau_gpuobj *ctx_table;
373
374 int (*init)(struct drm_device *);
375 void (*takedown)(struct drm_device *);
376
377 void (*fifo_access)(struct drm_device *, bool);
378
379 struct nouveau_channel *(*channel)(struct drm_device *);
380 int (*create_context)(struct nouveau_channel *);
381 void (*destroy_context)(struct nouveau_channel *);
382 int (*load_context)(struct nouveau_channel *);
383 int (*unload_context)(struct drm_device *);
384 void (*tlb_flush)(struct drm_device *dev);
385
386 void (*set_tile_region)(struct drm_device *dev, int i);
387 };
388
389 struct nouveau_display_engine {
390 int (*early_init)(struct drm_device *);
391 void (*late_takedown)(struct drm_device *);
392 int (*create)(struct drm_device *);
393 int (*init)(struct drm_device *);
394 void (*destroy)(struct drm_device *);
395 };
396
397 struct nouveau_gpio_engine {
398 void *priv;
399
400 int (*init)(struct drm_device *);
401 void (*takedown)(struct drm_device *);
402
403 int (*get)(struct drm_device *, enum dcb_gpio_tag);
404 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
405
406 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag,
407 void (*)(void *, int), void *);
408 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag,
409 void (*)(void *, int), void *);
410 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
411 };
412
413 struct nouveau_pm_voltage_level {
414 u8 voltage;
415 u8 vid;
416 };
417
418 struct nouveau_pm_voltage {
419 bool supported;
420 u8 vid_mask;
421
422 struct nouveau_pm_voltage_level *level;
423 int nr_level;
424 };
425
426 #define NOUVEAU_PM_MAX_LEVEL 8
427 struct nouveau_pm_level {
428 struct device_attribute dev_attr;
429 char name[32];
430 int id;
431
432 u32 core;
433 u32 memory;
434 u32 shader;
435 u32 unk05;
436
437 u8 voltage;
438 u8 fanspeed;
439
440 u16 memscript;
441 };
442
443 struct nouveau_pm_temp_sensor_constants {
444 u16 offset_constant;
445 s16 offset_mult;
446 u16 offset_div;
447 u16 slope_mult;
448 u16 slope_div;
449 };
450
451 struct nouveau_pm_threshold_temp {
452 s16 critical;
453 s16 down_clock;
454 s16 fan_boost;
455 };
456
457 struct nouveau_pm_memtiming {
458 u32 reg_100220;
459 u32 reg_100224;
460 u32 reg_100228;
461 u32 reg_10022c;
462 u32 reg_100230;
463 u32 reg_100234;
464 u32 reg_100238;
465 u32 reg_10023c;
466 };
467
468 struct nouveau_pm_memtimings {
469 bool supported;
470 struct nouveau_pm_memtiming *timing;
471 int nr_timing;
472 };
473
474 struct nouveau_pm_engine {
475 struct nouveau_pm_voltage voltage;
476 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
477 int nr_perflvl;
478 struct nouveau_pm_memtimings memtimings;
479 struct nouveau_pm_temp_sensor_constants sensor_constants;
480 struct nouveau_pm_threshold_temp threshold_temp;
481
482 struct nouveau_pm_level boot;
483 struct nouveau_pm_level *cur;
484
485 struct device *hwmon;
486 struct notifier_block acpi_nb;
487
488 int (*clock_get)(struct drm_device *, u32 id);
489 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
490 u32 id, int khz);
491 void (*clock_set)(struct drm_device *, void *);
492 int (*voltage_get)(struct drm_device *);
493 int (*voltage_set)(struct drm_device *, int voltage);
494 int (*fanspeed_get)(struct drm_device *);
495 int (*fanspeed_set)(struct drm_device *, int fanspeed);
496 int (*temp_get)(struct drm_device *);
497 };
498
499 struct nouveau_crypt_engine {
500 bool registered;
501
502 int (*init)(struct drm_device *);
503 void (*takedown)(struct drm_device *);
504 int (*create_context)(struct nouveau_channel *);
505 void (*destroy_context)(struct nouveau_channel *);
506 void (*tlb_flush)(struct drm_device *dev);
507 };
508
509 struct nouveau_vram_engine {
510 int (*init)(struct drm_device *);
511 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc,
512 u32 type, struct nouveau_vram **);
513 void (*put)(struct drm_device *, struct nouveau_vram **);
514
515 bool (*flags_valid)(struct drm_device *, u32 tile_flags);
516 };
517
518 struct nouveau_engine {
519 struct nouveau_instmem_engine instmem;
520 struct nouveau_mc_engine mc;
521 struct nouveau_timer_engine timer;
522 struct nouveau_fb_engine fb;
523 struct nouveau_pgraph_engine graph;
524 struct nouveau_fifo_engine fifo;
525 struct nouveau_display_engine display;
526 struct nouveau_gpio_engine gpio;
527 struct nouveau_pm_engine pm;
528 struct nouveau_crypt_engine crypt;
529 struct nouveau_vram_engine vram;
530 };
531
532 struct nouveau_pll_vals {
533 union {
534 struct {
535 #ifdef __BIG_ENDIAN
536 uint8_t N1, M1, N2, M2;
537 #else
538 uint8_t M1, N1, M2, N2;
539 #endif
540 };
541 struct {
542 uint16_t NM1, NM2;
543 } __attribute__((packed));
544 };
545 int log2P;
546
547 int refclk;
548 };
549
550 enum nv04_fp_display_regs {
551 FP_DISPLAY_END,
552 FP_TOTAL,
553 FP_CRTC,
554 FP_SYNC_START,
555 FP_SYNC_END,
556 FP_VALID_START,
557 FP_VALID_END
558 };
559
560 struct nv04_crtc_reg {
561 unsigned char MiscOutReg;
562 uint8_t CRTC[0xa0];
563 uint8_t CR58[0x10];
564 uint8_t Sequencer[5];
565 uint8_t Graphics[9];
566 uint8_t Attribute[21];
567 unsigned char DAC[768];
568
569 /* PCRTC regs */
570 uint32_t fb_start;
571 uint32_t crtc_cfg;
572 uint32_t cursor_cfg;
573 uint32_t gpio_ext;
574 uint32_t crtc_830;
575 uint32_t crtc_834;
576 uint32_t crtc_850;
577 uint32_t crtc_eng_ctrl;
578
579 /* PRAMDAC regs */
580 uint32_t nv10_cursync;
581 struct nouveau_pll_vals pllvals;
582 uint32_t ramdac_gen_ctrl;
583 uint32_t ramdac_630;
584 uint32_t ramdac_634;
585 uint32_t tv_setup;
586 uint32_t tv_vtotal;
587 uint32_t tv_vskew;
588 uint32_t tv_vsync_delay;
589 uint32_t tv_htotal;
590 uint32_t tv_hskew;
591 uint32_t tv_hsync_delay;
592 uint32_t tv_hsync_delay2;
593 uint32_t fp_horiz_regs[7];
594 uint32_t fp_vert_regs[7];
595 uint32_t dither;
596 uint32_t fp_control;
597 uint32_t dither_regs[6];
598 uint32_t fp_debug_0;
599 uint32_t fp_debug_1;
600 uint32_t fp_debug_2;
601 uint32_t fp_margin_color;
602 uint32_t ramdac_8c0;
603 uint32_t ramdac_a20;
604 uint32_t ramdac_a24;
605 uint32_t ramdac_a34;
606 uint32_t ctv_regs[38];
607 };
608
609 struct nv04_output_reg {
610 uint32_t output;
611 int head;
612 };
613
614 struct nv04_mode_state {
615 struct nv04_crtc_reg crtc_reg[2];
616 uint32_t pllsel;
617 uint32_t sel_clk;
618 };
619
620 enum nouveau_card_type {
621 NV_04 = 0x00,
622 NV_10 = 0x10,
623 NV_20 = 0x20,
624 NV_30 = 0x30,
625 NV_40 = 0x40,
626 NV_50 = 0x50,
627 NV_C0 = 0xc0,
628 };
629
630 struct drm_nouveau_private {
631 struct drm_device *dev;
632
633 /* the card type, takes NV_* as values */
634 enum nouveau_card_type card_type;
635 /* exact chipset, derived from NV_PMC_BOOT_0 */
636 int chipset;
637 int flags;
638
639 void __iomem *mmio;
640
641 spinlock_t ramin_lock;
642 void __iomem *ramin;
643 u32 ramin_size;
644 u32 ramin_base;
645 bool ramin_available;
646 struct drm_mm ramin_heap;
647 struct list_head gpuobj_list;
648 struct list_head classes;
649
650 struct nouveau_bo *vga_ram;
651
652 /* interrupt handling */
653 void (*irq_handler[32])(struct drm_device *);
654 bool msi_enabled;
655 struct workqueue_struct *wq;
656 struct work_struct irq_work;
657
658 struct list_head vbl_waiting;
659
660 struct {
661 struct drm_global_reference mem_global_ref;
662 struct ttm_bo_global_ref bo_global_ref;
663 struct ttm_bo_device bdev;
664 atomic_t validate_sequence;
665 } ttm;
666
667 struct {
668 spinlock_t lock;
669 struct drm_mm heap;
670 struct nouveau_bo *bo;
671 } fence;
672
673 struct {
674 spinlock_t lock;
675 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
676 } channels;
677
678 struct nouveau_engine engine;
679 struct nouveau_channel *channel;
680
681 /* For PFIFO and PGRAPH. */
682 spinlock_t context_switch_lock;
683
684 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
685 struct nouveau_ramht *ramht;
686 struct nouveau_gpuobj *ramfc;
687 struct nouveau_gpuobj *ramro;
688
689 uint32_t ramin_rsvd_vram;
690
691 struct {
692 enum {
693 NOUVEAU_GART_NONE = 0,
694 NOUVEAU_GART_AGP,
695 NOUVEAU_GART_SGDMA
696 } type;
697 uint64_t aper_base;
698 uint64_t aper_size;
699 uint64_t aper_free;
700
701 struct nouveau_gpuobj *sg_ctxdma;
702 struct nouveau_vma vma;
703 } gart_info;
704
705 /* nv10-nv40 tiling regions */
706 struct {
707 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
708 spinlock_t lock;
709 } tile;
710
711 /* VRAM/fb configuration */
712 uint64_t vram_size;
713 uint64_t vram_sys_base;
714 u32 vram_rblock_size;
715
716 uint64_t fb_phys;
717 uint64_t fb_available_size;
718 uint64_t fb_mappable_pages;
719 uint64_t fb_aper_free;
720 int fb_mtrr;
721
722 /* BAR control (NV50-) */
723 struct nouveau_vm *bar1_vm;
724 struct nouveau_vm *bar3_vm;
725
726 /* G8x/G9x virtual address space */
727 struct nouveau_vm *chan_vm;
728
729 struct nvbios vbios;
730
731 struct nv04_mode_state mode_reg;
732 struct nv04_mode_state saved_reg;
733 uint32_t saved_vga_font[4][16384];
734 uint32_t crtc_owner;
735 uint32_t dac_users[4];
736
737 struct nouveau_suspend_resume {
738 uint32_t *ramin_copy;
739 } susres;
740
741 struct backlight_device *backlight;
742
743 struct nouveau_channel *evo;
744 u32 evo_alloc;
745 struct {
746 struct dcb_entry *dcb;
747 u16 script;
748 u32 pclk;
749 } evo_irq;
750
751 struct {
752 struct dentry *channel_root;
753 } debugfs;
754
755 struct nouveau_fbdev *nfbdev;
756 struct apertures_struct *apertures;
757
758 bool powered_down;
759 };
760
761 static inline struct drm_nouveau_private *
762 nouveau_private(struct drm_device *dev)
763 {
764 return dev->dev_private;
765 }
766
767 static inline struct drm_nouveau_private *
768 nouveau_bdev(struct ttm_bo_device *bd)
769 {
770 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
771 }
772
773 static inline int
774 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
775 {
776 struct nouveau_bo *prev;
777
778 if (!pnvbo)
779 return -EINVAL;
780 prev = *pnvbo;
781
782 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
783 if (prev) {
784 struct ttm_buffer_object *bo = &prev->bo;
785
786 ttm_bo_unref(&bo);
787 }
788
789 return 0;
790 }
791
792 /* nouveau_drv.c */
793 extern int nouveau_agpmode;
794 extern int nouveau_duallink;
795 extern int nouveau_uscript_lvds;
796 extern int nouveau_uscript_tmds;
797 extern int nouveau_vram_pushbuf;
798 extern int nouveau_vram_notify;
799 extern int nouveau_fbpercrtc;
800 extern int nouveau_tv_disable;
801 extern char *nouveau_tv_norm;
802 extern int nouveau_reg_debug;
803 extern char *nouveau_vbios;
804 extern int nouveau_ignorelid;
805 extern int nouveau_nofbaccel;
806 extern int nouveau_noaccel;
807 extern int nouveau_force_post;
808 extern int nouveau_override_conntype;
809 extern char *nouveau_perflvl;
810 extern int nouveau_perflvl_wr;
811 extern int nouveau_msi;
812
813 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
814 extern int nouveau_pci_resume(struct pci_dev *pdev);
815
816 /* nouveau_state.c */
817 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
818 extern int nouveau_load(struct drm_device *, unsigned long flags);
819 extern int nouveau_firstopen(struct drm_device *);
820 extern void nouveau_lastclose(struct drm_device *);
821 extern int nouveau_unload(struct drm_device *);
822 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
823 struct drm_file *);
824 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
825 struct drm_file *);
826 extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout,
827 uint32_t reg, uint32_t mask, uint32_t val);
828 extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout,
829 uint32_t reg, uint32_t mask, uint32_t val);
830 extern bool nouveau_wait_for_idle(struct drm_device *);
831 extern int nouveau_card_init(struct drm_device *);
832
833 /* nouveau_mem.c */
834 extern int nouveau_mem_vram_init(struct drm_device *);
835 extern void nouveau_mem_vram_fini(struct drm_device *);
836 extern int nouveau_mem_gart_init(struct drm_device *);
837 extern void nouveau_mem_gart_fini(struct drm_device *);
838 extern int nouveau_mem_init_agp(struct drm_device *);
839 extern int nouveau_mem_reset_agp(struct drm_device *);
840 extern void nouveau_mem_close(struct drm_device *);
841 extern int nouveau_mem_detect(struct drm_device *);
842 extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
843 extern struct nouveau_tile_reg *nv10_mem_set_tiling(
844 struct drm_device *dev, uint32_t addr, uint32_t size,
845 uint32_t pitch, uint32_t flags);
846 extern void nv10_mem_put_tile_region(struct drm_device *dev,
847 struct nouveau_tile_reg *tile,
848 struct nouveau_fence *fence);
849 extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
850
851 /* nouveau_notifier.c */
852 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
853 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
854 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
855 int cout, uint32_t start, uint32_t end,
856 uint32_t *offset);
857 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
858 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
859 struct drm_file *);
860 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
861 struct drm_file *);
862
863 /* nouveau_channel.c */
864 extern struct drm_ioctl_desc nouveau_ioctls[];
865 extern int nouveau_max_ioctl;
866 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
867 extern int nouveau_channel_alloc(struct drm_device *dev,
868 struct nouveau_channel **chan,
869 struct drm_file *file_priv,
870 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
871 extern struct nouveau_channel *
872 nouveau_channel_get_unlocked(struct nouveau_channel *);
873 extern struct nouveau_channel *
874 nouveau_channel_get(struct drm_device *, struct drm_file *, int id);
875 extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
876 extern void nouveau_channel_put(struct nouveau_channel **);
877 extern void nouveau_channel_ref(struct nouveau_channel *chan,
878 struct nouveau_channel **pchan);
879 extern void nouveau_channel_idle(struct nouveau_channel *chan);
880
881 /* nouveau_object.c */
882 #define NVOBJ_CLASS(d,c,e) do { \
883 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
884 if (ret) \
885 return ret; \
886 } while(0)
887
888 #define NVOBJ_MTHD(d,c,m,e) do { \
889 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
890 if (ret) \
891 return ret; \
892 } while(0)
893
894 extern int nouveau_gpuobj_early_init(struct drm_device *);
895 extern int nouveau_gpuobj_init(struct drm_device *);
896 extern void nouveau_gpuobj_takedown(struct drm_device *);
897 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
898 extern void nouveau_gpuobj_resume(struct drm_device *dev);
899 extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
900 extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
901 int (*exec)(struct nouveau_channel *,
902 u32 class, u32 mthd, u32 data));
903 extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
904 extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
905 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
906 uint32_t vram_h, uint32_t tt_h);
907 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
908 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
909 uint32_t size, int align, uint32_t flags,
910 struct nouveau_gpuobj **);
911 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
912 struct nouveau_gpuobj **);
913 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
914 u32 size, u32 flags,
915 struct nouveau_gpuobj **);
916 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
917 uint64_t offset, uint64_t size, int access,
918 int target, struct nouveau_gpuobj **);
919 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class);
920 extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base,
921 u64 size, int target, int access, u32 type,
922 u32 comp, struct nouveau_gpuobj **pobj);
923 extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset,
924 int class, u64 base, u64 size, int target,
925 int access, u32 type, u32 comp);
926 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
927 struct drm_file *);
928 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
929 struct drm_file *);
930
931 /* nouveau_irq.c */
932 extern int nouveau_irq_init(struct drm_device *);
933 extern void nouveau_irq_fini(struct drm_device *);
934 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
935 extern void nouveau_irq_register(struct drm_device *, int status_bit,
936 void (*)(struct drm_device *));
937 extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
938 extern void nouveau_irq_preinstall(struct drm_device *);
939 extern int nouveau_irq_postinstall(struct drm_device *);
940 extern void nouveau_irq_uninstall(struct drm_device *);
941
942 /* nouveau_sgdma.c */
943 extern int nouveau_sgdma_init(struct drm_device *);
944 extern void nouveau_sgdma_takedown(struct drm_device *);
945 extern uint32_t nouveau_sgdma_get_physical(struct drm_device *,
946 uint32_t offset);
947 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
948
949 /* nouveau_debugfs.c */
950 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
951 extern int nouveau_debugfs_init(struct drm_minor *);
952 extern void nouveau_debugfs_takedown(struct drm_minor *);
953 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
954 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
955 #else
956 static inline int
957 nouveau_debugfs_init(struct drm_minor *minor)
958 {
959 return 0;
960 }
961
962 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
963 {
964 }
965
966 static inline int
967 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
968 {
969 return 0;
970 }
971
972 static inline void
973 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
974 {
975 }
976 #endif
977
978 /* nouveau_dma.c */
979 extern void nouveau_dma_pre_init(struct nouveau_channel *);
980 extern int nouveau_dma_init(struct nouveau_channel *);
981 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
982
983 /* nouveau_acpi.c */
984 #define ROM_BIOS_PAGE 4096
985 #if defined(CONFIG_ACPI)
986 void nouveau_register_dsm_handler(void);
987 void nouveau_unregister_dsm_handler(void);
988 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
989 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
990 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
991 #else
992 static inline void nouveau_register_dsm_handler(void) {}
993 static inline void nouveau_unregister_dsm_handler(void) {}
994 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
995 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
996 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
997 #endif
998
999 /* nouveau_backlight.c */
1000 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1001 extern int nouveau_backlight_init(struct drm_device *);
1002 extern void nouveau_backlight_exit(struct drm_device *);
1003 #else
1004 static inline int nouveau_backlight_init(struct drm_device *dev)
1005 {
1006 return 0;
1007 }
1008
1009 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
1010 #endif
1011
1012 /* nouveau_bios.c */
1013 extern int nouveau_bios_init(struct drm_device *);
1014 extern void nouveau_bios_takedown(struct drm_device *dev);
1015 extern int nouveau_run_vbios_init(struct drm_device *);
1016 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
1017 struct dcb_entry *);
1018 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
1019 enum dcb_gpio_tag);
1020 extern struct dcb_connector_table_entry *
1021 nouveau_bios_connector_entry(struct drm_device *, int index);
1022 extern u32 get_pll_register(struct drm_device *, enum pll_types);
1023 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
1024 struct pll_lims *);
1025 extern int nouveau_bios_run_display_table(struct drm_device *,
1026 struct dcb_entry *,
1027 uint32_t script, int pxclk);
1028 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
1029 int *length);
1030 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
1031 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
1032 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
1033 bool *dl, bool *if_is_24bit);
1034 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
1035 int head, int pxclk);
1036 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
1037 enum LVDS_script, int pxclk);
1038
1039 /* nouveau_ttm.c */
1040 int nouveau_ttm_global_init(struct drm_nouveau_private *);
1041 void nouveau_ttm_global_release(struct drm_nouveau_private *);
1042 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
1043
1044 /* nouveau_dp.c */
1045 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
1046 uint8_t *data, int data_nr);
1047 bool nouveau_dp_detect(struct drm_encoder *);
1048 bool nouveau_dp_link_train(struct drm_encoder *);
1049
1050 /* nv04_fb.c */
1051 extern int nv04_fb_init(struct drm_device *);
1052 extern void nv04_fb_takedown(struct drm_device *);
1053
1054 /* nv10_fb.c */
1055 extern int nv10_fb_init(struct drm_device *);
1056 extern void nv10_fb_takedown(struct drm_device *);
1057 extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
1058 uint32_t addr, uint32_t size,
1059 uint32_t pitch, uint32_t flags);
1060 extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
1061 extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
1062
1063 /* nv30_fb.c */
1064 extern int nv30_fb_init(struct drm_device *);
1065 extern void nv30_fb_takedown(struct drm_device *);
1066 extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
1067 uint32_t addr, uint32_t size,
1068 uint32_t pitch, uint32_t flags);
1069 extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
1070
1071 /* nv40_fb.c */
1072 extern int nv40_fb_init(struct drm_device *);
1073 extern void nv40_fb_takedown(struct drm_device *);
1074 extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
1075
1076 /* nv50_fb.c */
1077 extern int nv50_fb_init(struct drm_device *);
1078 extern void nv50_fb_takedown(struct drm_device *);
1079 extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
1080
1081 /* nvc0_fb.c */
1082 extern int nvc0_fb_init(struct drm_device *);
1083 extern void nvc0_fb_takedown(struct drm_device *);
1084
1085 /* nv04_fifo.c */
1086 extern int nv04_fifo_init(struct drm_device *);
1087 extern void nv04_fifo_fini(struct drm_device *);
1088 extern void nv04_fifo_disable(struct drm_device *);
1089 extern void nv04_fifo_enable(struct drm_device *);
1090 extern bool nv04_fifo_reassign(struct drm_device *, bool);
1091 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
1092 extern int nv04_fifo_channel_id(struct drm_device *);
1093 extern int nv04_fifo_create_context(struct nouveau_channel *);
1094 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1095 extern int nv04_fifo_load_context(struct nouveau_channel *);
1096 extern int nv04_fifo_unload_context(struct drm_device *);
1097 extern void nv04_fifo_isr(struct drm_device *);
1098
1099 /* nv10_fifo.c */
1100 extern int nv10_fifo_init(struct drm_device *);
1101 extern int nv10_fifo_channel_id(struct drm_device *);
1102 extern int nv10_fifo_create_context(struct nouveau_channel *);
1103 extern int nv10_fifo_load_context(struct nouveau_channel *);
1104 extern int nv10_fifo_unload_context(struct drm_device *);
1105
1106 /* nv40_fifo.c */
1107 extern int nv40_fifo_init(struct drm_device *);
1108 extern int nv40_fifo_create_context(struct nouveau_channel *);
1109 extern int nv40_fifo_load_context(struct nouveau_channel *);
1110 extern int nv40_fifo_unload_context(struct drm_device *);
1111
1112 /* nv50_fifo.c */
1113 extern int nv50_fifo_init(struct drm_device *);
1114 extern void nv50_fifo_takedown(struct drm_device *);
1115 extern int nv50_fifo_channel_id(struct drm_device *);
1116 extern int nv50_fifo_create_context(struct nouveau_channel *);
1117 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1118 extern int nv50_fifo_load_context(struct nouveau_channel *);
1119 extern int nv50_fifo_unload_context(struct drm_device *);
1120 extern void nv50_fifo_tlb_flush(struct drm_device *dev);
1121
1122 /* nvc0_fifo.c */
1123 extern int nvc0_fifo_init(struct drm_device *);
1124 extern void nvc0_fifo_takedown(struct drm_device *);
1125 extern void nvc0_fifo_disable(struct drm_device *);
1126 extern void nvc0_fifo_enable(struct drm_device *);
1127 extern bool nvc0_fifo_reassign(struct drm_device *, bool);
1128 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1129 extern int nvc0_fifo_channel_id(struct drm_device *);
1130 extern int nvc0_fifo_create_context(struct nouveau_channel *);
1131 extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1132 extern int nvc0_fifo_load_context(struct nouveau_channel *);
1133 extern int nvc0_fifo_unload_context(struct drm_device *);
1134
1135 /* nv04_graph.c */
1136 extern int nv04_graph_init(struct drm_device *);
1137 extern void nv04_graph_takedown(struct drm_device *);
1138 extern void nv04_graph_fifo_access(struct drm_device *, bool);
1139 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1140 extern int nv04_graph_create_context(struct nouveau_channel *);
1141 extern void nv04_graph_destroy_context(struct nouveau_channel *);
1142 extern int nv04_graph_load_context(struct nouveau_channel *);
1143 extern int nv04_graph_unload_context(struct drm_device *);
1144 extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1145 u32 class, u32 mthd, u32 data);
1146 extern struct nouveau_bitfield nv04_graph_nsource[];
1147
1148 /* nv10_graph.c */
1149 extern int nv10_graph_init(struct drm_device *);
1150 extern void nv10_graph_takedown(struct drm_device *);
1151 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1152 extern int nv10_graph_create_context(struct nouveau_channel *);
1153 extern void nv10_graph_destroy_context(struct nouveau_channel *);
1154 extern int nv10_graph_load_context(struct nouveau_channel *);
1155 extern int nv10_graph_unload_context(struct drm_device *);
1156 extern void nv10_graph_set_tile_region(struct drm_device *dev, int i);
1157 extern struct nouveau_bitfield nv10_graph_intr[];
1158 extern struct nouveau_bitfield nv10_graph_nstatus[];
1159
1160 /* nv20_graph.c */
1161 extern int nv20_graph_create_context(struct nouveau_channel *);
1162 extern void nv20_graph_destroy_context(struct nouveau_channel *);
1163 extern int nv20_graph_load_context(struct nouveau_channel *);
1164 extern int nv20_graph_unload_context(struct drm_device *);
1165 extern int nv20_graph_init(struct drm_device *);
1166 extern void nv20_graph_takedown(struct drm_device *);
1167 extern int nv30_graph_init(struct drm_device *);
1168 extern void nv20_graph_set_tile_region(struct drm_device *dev, int i);
1169
1170 /* nv40_graph.c */
1171 extern int nv40_graph_init(struct drm_device *);
1172 extern void nv40_graph_takedown(struct drm_device *);
1173 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1174 extern int nv40_graph_create_context(struct nouveau_channel *);
1175 extern void nv40_graph_destroy_context(struct nouveau_channel *);
1176 extern int nv40_graph_load_context(struct nouveau_channel *);
1177 extern int nv40_graph_unload_context(struct drm_device *);
1178 extern void nv40_grctx_init(struct nouveau_grctx *);
1179 extern void nv40_graph_set_tile_region(struct drm_device *dev, int i);
1180
1181 /* nv50_graph.c */
1182 extern int nv50_graph_init(struct drm_device *);
1183 extern void nv50_graph_takedown(struct drm_device *);
1184 extern void nv50_graph_fifo_access(struct drm_device *, bool);
1185 extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1186 extern int nv50_graph_create_context(struct nouveau_channel *);
1187 extern void nv50_graph_destroy_context(struct nouveau_channel *);
1188 extern int nv50_graph_load_context(struct nouveau_channel *);
1189 extern int nv50_graph_unload_context(struct drm_device *);
1190 extern int nv50_grctx_init(struct nouveau_grctx *);
1191 extern void nv50_graph_tlb_flush(struct drm_device *dev);
1192 extern void nv86_graph_tlb_flush(struct drm_device *dev);
1193 extern struct nouveau_enum nv50_data_error_names[];
1194
1195 /* nvc0_graph.c */
1196 extern int nvc0_graph_init(struct drm_device *);
1197 extern void nvc0_graph_takedown(struct drm_device *);
1198 extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1199 extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1200 extern int nvc0_graph_create_context(struct nouveau_channel *);
1201 extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1202 extern int nvc0_graph_load_context(struct nouveau_channel *);
1203 extern int nvc0_graph_unload_context(struct drm_device *);
1204
1205 /* nv84_crypt.c */
1206 extern int nv84_crypt_init(struct drm_device *dev);
1207 extern void nv84_crypt_fini(struct drm_device *dev);
1208 extern int nv84_crypt_create_context(struct nouveau_channel *);
1209 extern void nv84_crypt_destroy_context(struct nouveau_channel *);
1210 extern void nv84_crypt_tlb_flush(struct drm_device *dev);
1211
1212 /* nv04_instmem.c */
1213 extern int nv04_instmem_init(struct drm_device *);
1214 extern void nv04_instmem_takedown(struct drm_device *);
1215 extern int nv04_instmem_suspend(struct drm_device *);
1216 extern void nv04_instmem_resume(struct drm_device *);
1217 extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align);
1218 extern void nv04_instmem_put(struct nouveau_gpuobj *);
1219 extern int nv04_instmem_map(struct nouveau_gpuobj *);
1220 extern void nv04_instmem_unmap(struct nouveau_gpuobj *);
1221 extern void nv04_instmem_flush(struct drm_device *);
1222
1223 /* nv50_instmem.c */
1224 extern int nv50_instmem_init(struct drm_device *);
1225 extern void nv50_instmem_takedown(struct drm_device *);
1226 extern int nv50_instmem_suspend(struct drm_device *);
1227 extern void nv50_instmem_resume(struct drm_device *);
1228 extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align);
1229 extern void nv50_instmem_put(struct nouveau_gpuobj *);
1230 extern int nv50_instmem_map(struct nouveau_gpuobj *);
1231 extern void nv50_instmem_unmap(struct nouveau_gpuobj *);
1232 extern void nv50_instmem_flush(struct drm_device *);
1233 extern void nv84_instmem_flush(struct drm_device *);
1234
1235 /* nvc0_instmem.c */
1236 extern int nvc0_instmem_init(struct drm_device *);
1237 extern void nvc0_instmem_takedown(struct drm_device *);
1238 extern int nvc0_instmem_suspend(struct drm_device *);
1239 extern void nvc0_instmem_resume(struct drm_device *);
1240
1241 /* nv04_mc.c */
1242 extern int nv04_mc_init(struct drm_device *);
1243 extern void nv04_mc_takedown(struct drm_device *);
1244
1245 /* nv40_mc.c */
1246 extern int nv40_mc_init(struct drm_device *);
1247 extern void nv40_mc_takedown(struct drm_device *);
1248
1249 /* nv50_mc.c */
1250 extern int nv50_mc_init(struct drm_device *);
1251 extern void nv50_mc_takedown(struct drm_device *);
1252
1253 /* nv04_timer.c */
1254 extern int nv04_timer_init(struct drm_device *);
1255 extern uint64_t nv04_timer_read(struct drm_device *);
1256 extern void nv04_timer_takedown(struct drm_device *);
1257
1258 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1259 unsigned long arg);
1260
1261 /* nv04_dac.c */
1262 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1263 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1264 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1265 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1266 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1267
1268 /* nv04_dfp.c */
1269 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1270 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1271 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1272 int head, bool dl);
1273 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1274 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1275
1276 /* nv04_tv.c */
1277 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1278 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1279
1280 /* nv17_tv.c */
1281 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1282
1283 /* nv04_display.c */
1284 extern int nv04_display_early_init(struct drm_device *);
1285 extern void nv04_display_late_takedown(struct drm_device *);
1286 extern int nv04_display_create(struct drm_device *);
1287 extern int nv04_display_init(struct drm_device *);
1288 extern void nv04_display_destroy(struct drm_device *);
1289
1290 /* nv04_crtc.c */
1291 extern int nv04_crtc_create(struct drm_device *, int index);
1292
1293 /* nouveau_bo.c */
1294 extern struct ttm_bo_driver nouveau_bo_driver;
1295 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1296 int size, int align, uint32_t flags,
1297 uint32_t tile_mode, uint32_t tile_flags,
1298 bool no_vm, bool mappable, struct nouveau_bo **);
1299 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1300 extern int nouveau_bo_unpin(struct nouveau_bo *);
1301 extern int nouveau_bo_map(struct nouveau_bo *);
1302 extern void nouveau_bo_unmap(struct nouveau_bo *);
1303 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1304 uint32_t busy);
1305 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1306 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1307 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1308 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1309 extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
1310 extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible,
1311 bool no_wait_reserve, bool no_wait_gpu);
1312
1313 /* nouveau_fence.c */
1314 struct nouveau_fence;
1315 extern int nouveau_fence_init(struct drm_device *);
1316 extern void nouveau_fence_fini(struct drm_device *);
1317 extern int nouveau_fence_channel_init(struct nouveau_channel *);
1318 extern void nouveau_fence_channel_fini(struct nouveau_channel *);
1319 extern void nouveau_fence_update(struct nouveau_channel *);
1320 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1321 bool emit);
1322 extern int nouveau_fence_emit(struct nouveau_fence *);
1323 extern void nouveau_fence_work(struct nouveau_fence *fence,
1324 void (*work)(void *priv, bool signalled),
1325 void *priv);
1326 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1327
1328 extern bool __nouveau_fence_signalled(void *obj, void *arg);
1329 extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1330 extern int __nouveau_fence_flush(void *obj, void *arg);
1331 extern void __nouveau_fence_unref(void **obj);
1332 extern void *__nouveau_fence_ref(void *obj);
1333
1334 static inline bool nouveau_fence_signalled(struct nouveau_fence *obj)
1335 {
1336 return __nouveau_fence_signalled(obj, NULL);
1337 }
1338 static inline int
1339 nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr)
1340 {
1341 return __nouveau_fence_wait(obj, NULL, lazy, intr);
1342 }
1343 extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
1344 static inline int nouveau_fence_flush(struct nouveau_fence *obj)
1345 {
1346 return __nouveau_fence_flush(obj, NULL);
1347 }
1348 static inline void nouveau_fence_unref(struct nouveau_fence **obj)
1349 {
1350 __nouveau_fence_unref((void **)obj);
1351 }
1352 static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj)
1353 {
1354 return __nouveau_fence_ref(obj);
1355 }
1356
1357 /* nouveau_gem.c */
1358 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1359 int size, int align, uint32_t flags,
1360 uint32_t tile_mode, uint32_t tile_flags,
1361 bool no_vm, bool mappable, struct nouveau_bo **);
1362 extern int nouveau_gem_object_new(struct drm_gem_object *);
1363 extern void nouveau_gem_object_del(struct drm_gem_object *);
1364 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1365 struct drm_file *);
1366 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1367 struct drm_file *);
1368 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1369 struct drm_file *);
1370 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1371 struct drm_file *);
1372 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1373 struct drm_file *);
1374
1375 /* nouveau_display.c */
1376 int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1377 void nouveau_vblank_disable(struct drm_device *dev, int crtc);
1378 int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1379 struct drm_pending_vblank_event *event);
1380 int nouveau_finish_page_flip(struct nouveau_channel *,
1381 struct nouveau_page_flip_state *);
1382
1383 /* nv10_gpio.c */
1384 int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1385 int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1386
1387 /* nv50_gpio.c */
1388 int nv50_gpio_init(struct drm_device *dev);
1389 void nv50_gpio_fini(struct drm_device *dev);
1390 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1391 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1392 int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag,
1393 void (*)(void *, int), void *);
1394 void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag,
1395 void (*)(void *, int), void *);
1396 bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
1397
1398 /* nv50_calc. */
1399 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1400 int *N1, int *M1, int *N2, int *M2, int *P);
1401 int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1402 int clk, int *N, int *fN, int *M, int *P);
1403
1404 #ifndef ioread32_native
1405 #ifdef __BIG_ENDIAN
1406 #define ioread16_native ioread16be
1407 #define iowrite16_native iowrite16be
1408 #define ioread32_native ioread32be
1409 #define iowrite32_native iowrite32be
1410 #else /* def __BIG_ENDIAN */
1411 #define ioread16_native ioread16
1412 #define iowrite16_native iowrite16
1413 #define ioread32_native ioread32
1414 #define iowrite32_native iowrite32
1415 #endif /* def __BIG_ENDIAN else */
1416 #endif /* !ioread32_native */
1417
1418 /* channel control reg access */
1419 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1420 {
1421 return ioread32_native(chan->user + reg);
1422 }
1423
1424 static inline void nvchan_wr32(struct nouveau_channel *chan,
1425 unsigned reg, u32 val)
1426 {
1427 iowrite32_native(val, chan->user + reg);
1428 }
1429
1430 /* register access */
1431 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1432 {
1433 struct drm_nouveau_private *dev_priv = dev->dev_private;
1434 return ioread32_native(dev_priv->mmio + reg);
1435 }
1436
1437 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1438 {
1439 struct drm_nouveau_private *dev_priv = dev->dev_private;
1440 iowrite32_native(val, dev_priv->mmio + reg);
1441 }
1442
1443 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1444 {
1445 u32 tmp = nv_rd32(dev, reg);
1446 nv_wr32(dev, reg, (tmp & ~mask) | val);
1447 return tmp;
1448 }
1449
1450 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1451 {
1452 struct drm_nouveau_private *dev_priv = dev->dev_private;
1453 return ioread8(dev_priv->mmio + reg);
1454 }
1455
1456 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1457 {
1458 struct drm_nouveau_private *dev_priv = dev->dev_private;
1459 iowrite8(val, dev_priv->mmio + reg);
1460 }
1461
1462 #define nv_wait(dev, reg, mask, val) \
1463 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val))
1464 #define nv_wait_ne(dev, reg, mask, val) \
1465 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val))
1466
1467 /* PRAMIN access */
1468 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1469 {
1470 struct drm_nouveau_private *dev_priv = dev->dev_private;
1471 return ioread32_native(dev_priv->ramin + offset);
1472 }
1473
1474 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1475 {
1476 struct drm_nouveau_private *dev_priv = dev->dev_private;
1477 iowrite32_native(val, dev_priv->ramin + offset);
1478 }
1479
1480 /* object access */
1481 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1482 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1483
1484 /*
1485 * Logging
1486 * Argument d is (struct drm_device *).
1487 */
1488 #define NV_PRINTK(level, d, fmt, arg...) \
1489 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1490 pci_name(d->pdev), ##arg)
1491 #ifndef NV_DEBUG_NOTRACE
1492 #define NV_DEBUG(d, fmt, arg...) do { \
1493 if (drm_debug & DRM_UT_DRIVER) { \
1494 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1495 __LINE__, ##arg); \
1496 } \
1497 } while (0)
1498 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1499 if (drm_debug & DRM_UT_KMS) { \
1500 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1501 __LINE__, ##arg); \
1502 } \
1503 } while (0)
1504 #else
1505 #define NV_DEBUG(d, fmt, arg...) do { \
1506 if (drm_debug & DRM_UT_DRIVER) \
1507 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1508 } while (0)
1509 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1510 if (drm_debug & DRM_UT_KMS) \
1511 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1512 } while (0)
1513 #endif
1514 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1515 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1516 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1517 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1518 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1519
1520 /* nouveau_reg_debug bitmask */
1521 enum {
1522 NOUVEAU_REG_DEBUG_MC = 0x1,
1523 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1524 NOUVEAU_REG_DEBUG_FB = 0x4,
1525 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1526 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1527 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1528 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1529 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1530 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1531 NOUVEAU_REG_DEBUG_EVO = 0x200,
1532 };
1533
1534 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1535 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1536 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1537 } while (0)
1538
1539 static inline bool
1540 nv_two_heads(struct drm_device *dev)
1541 {
1542 struct drm_nouveau_private *dev_priv = dev->dev_private;
1543 const int impl = dev->pci_device & 0x0ff0;
1544
1545 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1546 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1547 return true;
1548
1549 return false;
1550 }
1551
1552 static inline bool
1553 nv_gf4_disp_arch(struct drm_device *dev)
1554 {
1555 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1556 }
1557
1558 static inline bool
1559 nv_two_reg_pll(struct drm_device *dev)
1560 {
1561 struct drm_nouveau_private *dev_priv = dev->dev_private;
1562 const int impl = dev->pci_device & 0x0ff0;
1563
1564 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1565 return true;
1566 return false;
1567 }
1568
1569 static inline bool
1570 nv_match_device(struct drm_device *dev, unsigned device,
1571 unsigned sub_vendor, unsigned sub_device)
1572 {
1573 return dev->pdev->device == device &&
1574 dev->pdev->subsystem_vendor == sub_vendor &&
1575 dev->pdev->subsystem_device == sub_device;
1576 }
1577
1578 /* returns 1 if device is one of the nv4x using the 0x4497 object class,
1579 * helpful to determine a number of other hardware features
1580 */
1581 static inline int
1582 nv44_graph_class(struct drm_device *dev)
1583 {
1584 struct drm_nouveau_private *dev_priv = dev->dev_private;
1585
1586 if ((dev_priv->chipset & 0xf0) == 0x60)
1587 return 1;
1588
1589 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f)));
1590 }
1591
1592 /* memory type/access flags, do not match hardware values */
1593 #define NV_MEM_ACCESS_RO 1
1594 #define NV_MEM_ACCESS_WO 2
1595 #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO)
1596 #define NV_MEM_ACCESS_SYS 4
1597 #define NV_MEM_ACCESS_VM 8
1598
1599 #define NV_MEM_TARGET_VRAM 0
1600 #define NV_MEM_TARGET_PCI 1
1601 #define NV_MEM_TARGET_PCI_NOSNOOP 2
1602 #define NV_MEM_TARGET_VM 3
1603 #define NV_MEM_TARGET_GART 4
1604
1605 #define NV_MEM_TYPE_VM 0x7f
1606 #define NV_MEM_COMP_VM 0x03
1607
1608 /* NV_SW object class */
1609 #define NV_SW 0x0000506e
1610 #define NV_SW_DMA_SEMAPHORE 0x00000060
1611 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1612 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1613 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1614 #define NV_SW_YIELD 0x00000080
1615 #define NV_SW_DMA_VBLSEM 0x0000018c
1616 #define NV_SW_VBLSEM_OFFSET 0x00000400
1617 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1618 #define NV_SW_VBLSEM_RELEASE 0x00000408
1619 #define NV_SW_PAGE_FLIP 0x00000500
1620
1621 #endif /* __NOUVEAU_DRV_H__ */
Linux kernel - Deliverables
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