2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
48 struct nouveau_fpriv
{
49 struct ttm_object_file
*tfile
;
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
59 #define MAX_NUM_DCB_ENTRIES 16
61 #define NOUVEAU_MAX_CHANNEL_NR 128
62 #define NOUVEAU_MAX_TILE_NR 15
64 #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65 #define NV50_VM_BLOCK (512*1024*1024ULL)
66 #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
68 struct nouveau_tile_reg
{
69 struct nouveau_fence
*fence
;
76 struct ttm_buffer_object bo
;
77 struct ttm_placement placement
;
79 u32 busy_placements
[3];
80 struct ttm_bo_kmap_obj kmap
;
81 struct list_head head
;
83 /* protected by ttm_bo_reserve() */
84 struct drm_file
*reserved_by
;
85 struct list_head entry
;
89 struct nouveau_channel
*channel
;
96 struct nouveau_tile_reg
*tile
;
98 struct drm_gem_object
*gem
;
99 struct drm_file
*cpu_filp
;
103 static inline struct nouveau_bo
*
104 nouveau_bo(struct ttm_buffer_object
*bo
)
106 return container_of(bo
, struct nouveau_bo
, bo
);
109 static inline struct nouveau_bo
*
110 nouveau_gem_object(struct drm_gem_object
*gem
)
112 return gem
? gem
->driver_private
: NULL
;
115 /* TODO: submit equivalent to TTM generic API upstream? */
116 static inline void __iomem
*
117 nvbo_kmap_obj_iovirtual(struct nouveau_bo
*nvbo
)
120 void __iomem
*ioptr
= (void __force __iomem
*)ttm_kmap_obj_virtual(
121 &nvbo
->kmap
, &is_iomem
);
122 WARN_ON_ONCE(ioptr
&& !is_iomem
);
127 NV_NFORCE
= 0x10000000,
128 NV_NFORCE2
= 0x20000000
131 #define NVOBJ_ENGINE_SW 0
132 #define NVOBJ_ENGINE_GR 1
133 #define NVOBJ_ENGINE_DISPLAY 2
134 #define NVOBJ_ENGINE_INT 0xdeadbeef
136 #define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
137 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
138 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
139 #define NVOBJ_FLAG_FAKE (1 << 3)
140 struct nouveau_gpuobj
{
141 struct list_head list
;
143 struct nouveau_channel
*im_channel
;
144 struct drm_mm_node
*im_pramin
;
145 struct nouveau_bo
*im_backing
;
146 uint32_t im_backing_start
;
147 uint32_t *im_backing_suspend
;
156 void (*dtor
)(struct drm_device
*, struct nouveau_gpuobj
*);
160 struct nouveau_gpuobj_ref
{
161 struct list_head list
;
163 struct nouveau_gpuobj
*gpuobj
;
166 struct nouveau_channel
*channel
;
170 struct nouveau_channel
{
171 struct drm_device
*dev
;
174 /* owner of this fifo */
175 struct drm_file
*file_priv
;
176 /* mapping of the fifo itself */
177 struct drm_local_map
*map
;
179 /* mapping of the regs controling the fifo */
186 /* lock protects the pending list only */
188 struct list_head pending
;
190 uint32_t sequence_ack
;
191 atomic_t last_sequence_irq
;
194 /* DMA push buffer */
195 struct nouveau_gpuobj_ref
*pushbuf
;
196 struct nouveau_bo
*pushbuf_bo
;
197 uint32_t pushbuf_base
;
199 /* Notifier memory */
200 struct nouveau_bo
*notifier_bo
;
201 struct drm_mm notifier_heap
;
204 struct nouveau_gpuobj_ref
*ramfc
;
205 struct nouveau_gpuobj_ref
*cache
;
208 /* XXX may be merge 2 pointers as private data ??? */
209 struct nouveau_gpuobj_ref
*ramin_grctx
;
213 struct nouveau_gpuobj
*vm_pd
;
214 struct nouveau_gpuobj_ref
*vm_gart_pt
;
215 struct nouveau_gpuobj_ref
*vm_vram_pt
[NV50_VM_VRAM_NR
];
218 struct nouveau_gpuobj_ref
*ramin
; /* Private instmem */
219 struct drm_mm ramin_heap
; /* Private PRAMIN heap */
220 struct nouveau_gpuobj_ref
*ramht
; /* Hash table */
221 struct list_head ramht_refs
; /* Objects referenced by RAMHT */
223 /* GPU object info for stuff used in-kernel (mm_enabled) */
225 uint32_t vram_handle
;
226 uint32_t gart_handle
;
229 /* Push buffer state (only for drm's channel on !mm_enabled) */
235 /* access via pushbuf_bo */
243 uint32_t sw_subchannel
[8];
246 struct nouveau_gpuobj
*vblsem
;
247 uint32_t vblsem_offset
;
248 uint32_t vblsem_rval
;
249 struct list_head vbl_wait
;
255 struct drm_info_list info
;
259 struct nouveau_instmem_engine
{
262 int (*init
)(struct drm_device
*dev
);
263 void (*takedown
)(struct drm_device
*dev
);
264 int (*suspend
)(struct drm_device
*dev
);
265 void (*resume
)(struct drm_device
*dev
);
267 int (*populate
)(struct drm_device
*, struct nouveau_gpuobj
*,
269 void (*clear
)(struct drm_device
*, struct nouveau_gpuobj
*);
270 int (*bind
)(struct drm_device
*, struct nouveau_gpuobj
*);
271 int (*unbind
)(struct drm_device
*, struct nouveau_gpuobj
*);
272 void (*flush
)(struct drm_device
*);
275 struct nouveau_mc_engine
{
276 int (*init
)(struct drm_device
*dev
);
277 void (*takedown
)(struct drm_device
*dev
);
280 struct nouveau_timer_engine
{
281 int (*init
)(struct drm_device
*dev
);
282 void (*takedown
)(struct drm_device
*dev
);
283 uint64_t (*read
)(struct drm_device
*dev
);
286 struct nouveau_fb_engine
{
289 int (*init
)(struct drm_device
*dev
);
290 void (*takedown
)(struct drm_device
*dev
);
292 void (*set_region_tiling
)(struct drm_device
*dev
, int i
, uint32_t addr
,
293 uint32_t size
, uint32_t pitch
);
296 struct nouveau_fifo_engine
{
299 struct nouveau_gpuobj_ref
*playlist
[2];
302 int (*init
)(struct drm_device
*);
303 void (*takedown
)(struct drm_device
*);
305 void (*disable
)(struct drm_device
*);
306 void (*enable
)(struct drm_device
*);
307 bool (*reassign
)(struct drm_device
*, bool enable
);
308 bool (*cache_flush
)(struct drm_device
*dev
);
309 bool (*cache_pull
)(struct drm_device
*dev
, bool enable
);
311 int (*channel_id
)(struct drm_device
*);
313 int (*create_context
)(struct nouveau_channel
*);
314 void (*destroy_context
)(struct nouveau_channel
*);
315 int (*load_context
)(struct nouveau_channel
*);
316 int (*unload_context
)(struct drm_device
*);
319 struct nouveau_pgraph_object_method
{
321 int (*exec
)(struct nouveau_channel
*chan
, int grclass
, int mthd
,
325 struct nouveau_pgraph_object_class
{
328 struct nouveau_pgraph_object_method
*methods
;
331 struct nouveau_pgraph_engine
{
332 struct nouveau_pgraph_object_class
*grclass
;
336 /* NV2x/NV3x context table (0x400780) */
337 struct nouveau_gpuobj_ref
*ctx_table
;
339 int (*init
)(struct drm_device
*);
340 void (*takedown
)(struct drm_device
*);
342 void (*fifo_access
)(struct drm_device
*, bool);
344 struct nouveau_channel
*(*channel
)(struct drm_device
*);
345 int (*create_context
)(struct nouveau_channel
*);
346 void (*destroy_context
)(struct nouveau_channel
*);
347 int (*load_context
)(struct nouveau_channel
*);
348 int (*unload_context
)(struct drm_device
*);
350 void (*set_region_tiling
)(struct drm_device
*dev
, int i
, uint32_t addr
,
351 uint32_t size
, uint32_t pitch
);
354 struct nouveau_display_engine
{
355 int (*early_init
)(struct drm_device
*);
356 void (*late_takedown
)(struct drm_device
*);
357 int (*create
)(struct drm_device
*);
358 int (*init
)(struct drm_device
*);
359 void (*destroy
)(struct drm_device
*);
362 struct nouveau_gpio_engine
{
363 int (*init
)(struct drm_device
*);
364 void (*takedown
)(struct drm_device
*);
366 int (*get
)(struct drm_device
*, enum dcb_gpio_tag
);
367 int (*set
)(struct drm_device
*, enum dcb_gpio_tag
, int state
);
369 void (*irq_enable
)(struct drm_device
*, enum dcb_gpio_tag
, bool on
);
372 struct nouveau_engine
{
373 struct nouveau_instmem_engine instmem
;
374 struct nouveau_mc_engine mc
;
375 struct nouveau_timer_engine timer
;
376 struct nouveau_fb_engine fb
;
377 struct nouveau_pgraph_engine graph
;
378 struct nouveau_fifo_engine fifo
;
379 struct nouveau_display_engine display
;
380 struct nouveau_gpio_engine gpio
;
383 struct nouveau_pll_vals
{
387 uint8_t N1
, M1
, N2
, M2
;
389 uint8_t M1
, N1
, M2
, N2
;
394 } __attribute__((packed
));
401 enum nv04_fp_display_regs
{
411 struct nv04_crtc_reg
{
412 unsigned char MiscOutReg
; /* */
415 uint8_t Sequencer
[5];
417 uint8_t Attribute
[21];
418 unsigned char DAC
[768]; /* Internal Colorlookuptable */
428 uint32_t crtc_eng_ctrl
;
431 uint32_t nv10_cursync
;
432 struct nouveau_pll_vals pllvals
;
433 uint32_t ramdac_gen_ctrl
;
439 uint32_t tv_vsync_delay
;
442 uint32_t tv_hsync_delay
;
443 uint32_t tv_hsync_delay2
;
444 uint32_t fp_horiz_regs
[7];
445 uint32_t fp_vert_regs
[7];
448 uint32_t dither_regs
[6];
452 uint32_t fp_margin_color
;
457 uint32_t ctv_regs
[38];
460 struct nv04_output_reg
{
465 struct nv04_mode_state
{
493 uint32_t cursorConfig
;
502 struct nv04_crtc_reg crtc_reg
[2];
505 enum nouveau_card_type
{
515 struct drm_nouveau_private
{
516 struct drm_device
*dev
;
518 /* the card type, takes NV_* as values */
519 enum nouveau_card_type card_type
;
520 /* exact chipset, derived from NV_PMC_BOOT_0 */
528 struct nouveau_bo
*vga_ram
;
530 struct workqueue_struct
*wq
;
531 struct work_struct irq_work
;
532 struct work_struct hpd_work
;
534 struct list_head vbl_waiting
;
537 struct drm_global_reference mem_global_ref
;
538 struct ttm_bo_global_ref bo_global_ref
;
539 struct ttm_bo_device bdev
;
540 atomic_t validate_sequence
;
543 int fifo_alloc_count
;
544 struct nouveau_channel
*fifos
[NOUVEAU_MAX_CHANNEL_NR
];
546 struct nouveau_engine engine
;
547 struct nouveau_channel
*channel
;
549 /* For PFIFO and PGRAPH. */
550 spinlock_t context_switch_lock
;
552 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
553 struct nouveau_gpuobj
*ramht
;
554 uint32_t ramin_rsvd_vram
;
555 uint32_t ramht_offset
;
558 uint32_t ramfc_offset
;
560 uint32_t ramro_offset
;
565 NOUVEAU_GART_NONE
= 0,
573 struct nouveau_gpuobj
*sg_ctxdma
;
574 struct page
*sg_dummy_page
;
575 dma_addr_t sg_dummy_bus
;
578 /* nv10-nv40 tiling regions */
580 struct nouveau_tile_reg reg
[NOUVEAU_MAX_TILE_NR
];
584 /* VRAM/fb configuration */
586 uint64_t vram_sys_base
;
589 uint64_t fb_available_size
;
590 uint64_t fb_mappable_pages
;
591 uint64_t fb_aper_free
;
594 /* G8x/G9x virtual address space */
595 uint64_t vm_gart_base
;
596 uint64_t vm_gart_size
;
597 uint64_t vm_vram_base
;
598 uint64_t vm_vram_size
;
600 struct nouveau_gpuobj
*vm_vram_pt
[NV50_VM_VRAM_NR
];
603 struct drm_mm ramin_heap
;
605 struct list_head gpuobj_list
;
609 struct nv04_mode_state mode_reg
;
610 struct nv04_mode_state saved_reg
;
611 uint32_t saved_vga_font
[4][16384];
613 uint32_t dac_users
[4];
615 struct nouveau_suspend_resume
{
616 uint32_t *ramin_copy
;
619 struct backlight_device
*backlight
;
621 struct nouveau_channel
*evo
;
623 struct dcb_entry
*dcb
;
629 struct dentry
*channel_root
;
632 struct nouveau_fbdev
*nfbdev
;
633 struct apertures_struct
*apertures
;
636 static inline struct drm_nouveau_private
*
637 nouveau_bdev(struct ttm_bo_device
*bd
)
639 return container_of(bd
, struct drm_nouveau_private
, ttm
.bdev
);
643 nouveau_bo_ref(struct nouveau_bo
*ref
, struct nouveau_bo
**pnvbo
)
645 struct nouveau_bo
*prev
;
651 *pnvbo
= ref
? nouveau_bo(ttm_bo_reference(&ref
->bo
)) : NULL
;
653 struct ttm_buffer_object
*bo
= &prev
->bo
;
661 #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
662 struct drm_nouveau_private *nv = dev->dev_private; \
663 if (!nouveau_channel_owner(dev, (cl), (id))) { \
664 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
665 DRM_CURRENTPID, (id)); \
668 (ch) = nv->fifos[(id)]; \
672 extern int nouveau_noagp
;
673 extern int nouveau_duallink
;
674 extern int nouveau_uscript_lvds
;
675 extern int nouveau_uscript_tmds
;
676 extern int nouveau_vram_pushbuf
;
677 extern int nouveau_vram_notify
;
678 extern int nouveau_fbpercrtc
;
679 extern int nouveau_tv_disable
;
680 extern char *nouveau_tv_norm
;
681 extern int nouveau_reg_debug
;
682 extern char *nouveau_vbios
;
683 extern int nouveau_ignorelid
;
684 extern int nouveau_nofbaccel
;
685 extern int nouveau_noaccel
;
686 extern int nouveau_override_conntype
;
688 extern int nouveau_pci_suspend(struct pci_dev
*pdev
, pm_message_t pm_state
);
689 extern int nouveau_pci_resume(struct pci_dev
*pdev
);
691 /* nouveau_state.c */
692 extern void nouveau_preclose(struct drm_device
*dev
, struct drm_file
*);
693 extern int nouveau_load(struct drm_device
*, unsigned long flags
);
694 extern int nouveau_firstopen(struct drm_device
*);
695 extern void nouveau_lastclose(struct drm_device
*);
696 extern int nouveau_unload(struct drm_device
*);
697 extern int nouveau_ioctl_getparam(struct drm_device
*, void *data
,
699 extern int nouveau_ioctl_setparam(struct drm_device
*, void *data
,
701 extern bool nouveau_wait_until(struct drm_device
*, uint64_t timeout
,
702 uint32_t reg
, uint32_t mask
, uint32_t val
);
703 extern bool nouveau_wait_for_idle(struct drm_device
*);
704 extern int nouveau_card_init(struct drm_device
*);
707 extern int nouveau_mem_detect(struct drm_device
*dev
);
708 extern int nouveau_mem_init(struct drm_device
*);
709 extern int nouveau_mem_init_agp(struct drm_device
*);
710 extern int nouveau_mem_reset_agp(struct drm_device
*);
711 extern void nouveau_mem_close(struct drm_device
*);
712 extern struct nouveau_tile_reg
*nv10_mem_set_tiling(struct drm_device
*dev
,
716 extern void nv10_mem_expire_tiling(struct drm_device
*dev
,
717 struct nouveau_tile_reg
*tile
,
718 struct nouveau_fence
*fence
);
719 extern int nv50_mem_vm_bind_linear(struct drm_device
*, uint64_t virt
,
720 uint32_t size
, uint32_t flags
,
722 extern void nv50_mem_vm_unbind(struct drm_device
*, uint64_t virt
,
725 /* nouveau_notifier.c */
726 extern int nouveau_notifier_init_channel(struct nouveau_channel
*);
727 extern void nouveau_notifier_takedown_channel(struct nouveau_channel
*);
728 extern int nouveau_notifier_alloc(struct nouveau_channel
*, uint32_t handle
,
729 int cout
, uint32_t *offset
);
730 extern int nouveau_notifier_offset(struct nouveau_gpuobj
*, uint32_t *);
731 extern int nouveau_ioctl_notifier_alloc(struct drm_device
*, void *data
,
733 extern int nouveau_ioctl_notifier_free(struct drm_device
*, void *data
,
736 /* nouveau_channel.c */
737 extern struct drm_ioctl_desc nouveau_ioctls
[];
738 extern int nouveau_max_ioctl
;
739 extern void nouveau_channel_cleanup(struct drm_device
*, struct drm_file
*);
740 extern int nouveau_channel_owner(struct drm_device
*, struct drm_file
*,
742 extern int nouveau_channel_alloc(struct drm_device
*dev
,
743 struct nouveau_channel
**chan
,
744 struct drm_file
*file_priv
,
745 uint32_t fb_ctxdma
, uint32_t tt_ctxdma
);
746 extern void nouveau_channel_free(struct nouveau_channel
*);
748 /* nouveau_object.c */
749 extern int nouveau_gpuobj_early_init(struct drm_device
*);
750 extern int nouveau_gpuobj_init(struct drm_device
*);
751 extern void nouveau_gpuobj_takedown(struct drm_device
*);
752 extern void nouveau_gpuobj_late_takedown(struct drm_device
*);
753 extern int nouveau_gpuobj_suspend(struct drm_device
*dev
);
754 extern void nouveau_gpuobj_suspend_cleanup(struct drm_device
*dev
);
755 extern void nouveau_gpuobj_resume(struct drm_device
*dev
);
756 extern int nouveau_gpuobj_channel_init(struct nouveau_channel
*,
757 uint32_t vram_h
, uint32_t tt_h
);
758 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel
*);
759 extern int nouveau_gpuobj_new(struct drm_device
*, struct nouveau_channel
*,
760 uint32_t size
, int align
, uint32_t flags
,
761 struct nouveau_gpuobj
**);
762 extern int nouveau_gpuobj_del(struct drm_device
*, struct nouveau_gpuobj
**);
763 extern int nouveau_gpuobj_ref_add(struct drm_device
*, struct nouveau_channel
*,
764 uint32_t handle
, struct nouveau_gpuobj
*,
765 struct nouveau_gpuobj_ref
**);
766 extern int nouveau_gpuobj_ref_del(struct drm_device
*,
767 struct nouveau_gpuobj_ref
**);
768 extern int nouveau_gpuobj_ref_find(struct nouveau_channel
*, uint32_t handle
,
769 struct nouveau_gpuobj_ref
**ref_ret
);
770 extern int nouveau_gpuobj_new_ref(struct drm_device
*,
771 struct nouveau_channel
*alloc_chan
,
772 struct nouveau_channel
*ref_chan
,
773 uint32_t handle
, uint32_t size
, int align
,
774 uint32_t flags
, struct nouveau_gpuobj_ref
**);
775 extern int nouveau_gpuobj_new_fake(struct drm_device
*,
776 uint32_t p_offset
, uint32_t b_offset
,
777 uint32_t size
, uint32_t flags
,
778 struct nouveau_gpuobj
**,
779 struct nouveau_gpuobj_ref
**);
780 extern int nouveau_gpuobj_dma_new(struct nouveau_channel
*, int class,
781 uint64_t offset
, uint64_t size
, int access
,
782 int target
, struct nouveau_gpuobj
**);
783 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel
*,
784 uint64_t offset
, uint64_t size
,
785 int access
, struct nouveau_gpuobj
**,
787 extern int nouveau_gpuobj_gr_new(struct nouveau_channel
*, int class,
788 struct nouveau_gpuobj
**);
789 extern int nouveau_gpuobj_sw_new(struct nouveau_channel
*, int class,
790 struct nouveau_gpuobj
**);
791 extern int nouveau_ioctl_grobj_alloc(struct drm_device
*, void *data
,
793 extern int nouveau_ioctl_gpuobj_free(struct drm_device
*, void *data
,
797 extern irqreturn_t
nouveau_irq_handler(DRM_IRQ_ARGS
);
798 extern void nouveau_irq_preinstall(struct drm_device
*);
799 extern int nouveau_irq_postinstall(struct drm_device
*);
800 extern void nouveau_irq_uninstall(struct drm_device
*);
802 /* nouveau_sgdma.c */
803 extern int nouveau_sgdma_init(struct drm_device
*);
804 extern void nouveau_sgdma_takedown(struct drm_device
*);
805 extern int nouveau_sgdma_get_page(struct drm_device
*, uint32_t offset
,
807 extern struct ttm_backend
*nouveau_sgdma_init_ttm(struct drm_device
*);
809 /* nouveau_debugfs.c */
810 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
811 extern int nouveau_debugfs_init(struct drm_minor
*);
812 extern void nouveau_debugfs_takedown(struct drm_minor
*);
813 extern int nouveau_debugfs_channel_init(struct nouveau_channel
*);
814 extern void nouveau_debugfs_channel_fini(struct nouveau_channel
*);
817 nouveau_debugfs_init(struct drm_minor
*minor
)
822 static inline void nouveau_debugfs_takedown(struct drm_minor
*minor
)
827 nouveau_debugfs_channel_init(struct nouveau_channel
*chan
)
833 nouveau_debugfs_channel_fini(struct nouveau_channel
*chan
)
839 extern void nouveau_dma_pre_init(struct nouveau_channel
*);
840 extern int nouveau_dma_init(struct nouveau_channel
*);
841 extern int nouveau_dma_wait(struct nouveau_channel
*, int slots
, int size
);
844 #define ROM_BIOS_PAGE 4096
845 #if defined(CONFIG_ACPI)
846 void nouveau_register_dsm_handler(void);
847 void nouveau_unregister_dsm_handler(void);
848 int nouveau_acpi_get_bios_chunk(uint8_t *bios
, int offset
, int len
);
849 bool nouveau_acpi_rom_supported(struct pci_dev
*pdev
);
850 int nouveau_acpi_edid(struct drm_device
*, struct drm_connector
*);
852 static inline void nouveau_register_dsm_handler(void) {}
853 static inline void nouveau_unregister_dsm_handler(void) {}
854 static inline bool nouveau_acpi_rom_supported(struct pci_dev
*pdev
) { return false; }
855 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios
, int offset
, int len
) { return -EINVAL
; }
856 static inline int nouveau_acpi_edid(struct drm_device
*dev
, struct drm_connector
*connector
) { return -EINVAL
; }
859 /* nouveau_backlight.c */
860 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
861 extern int nouveau_backlight_init(struct drm_device
*);
862 extern void nouveau_backlight_exit(struct drm_device
*);
864 static inline int nouveau_backlight_init(struct drm_device
*dev
)
869 static inline void nouveau_backlight_exit(struct drm_device
*dev
) { }
873 extern int nouveau_bios_init(struct drm_device
*);
874 extern void nouveau_bios_takedown(struct drm_device
*dev
);
875 extern int nouveau_run_vbios_init(struct drm_device
*);
876 extern void nouveau_bios_run_init_table(struct drm_device
*, uint16_t table
,
878 extern struct dcb_gpio_entry
*nouveau_bios_gpio_entry(struct drm_device
*,
880 extern struct dcb_connector_table_entry
*
881 nouveau_bios_connector_entry(struct drm_device
*, int index
);
882 extern int get_pll_limits(struct drm_device
*, uint32_t limit_match
,
884 extern int nouveau_bios_run_display_table(struct drm_device
*,
886 uint32_t script
, int pxclk
);
887 extern void *nouveau_bios_dp_table(struct drm_device
*, struct dcb_entry
*,
889 extern bool nouveau_bios_fp_mode(struct drm_device
*, struct drm_display_mode
*);
890 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device
*);
891 extern int nouveau_bios_parse_lvds_table(struct drm_device
*, int pxclk
,
892 bool *dl
, bool *if_is_24bit
);
893 extern int run_tmds_table(struct drm_device
*, struct dcb_entry
*,
894 int head
, int pxclk
);
895 extern int call_lvds_script(struct drm_device
*, struct dcb_entry
*, int head
,
896 enum LVDS_script
, int pxclk
);
899 int nouveau_ttm_global_init(struct drm_nouveau_private
*);
900 void nouveau_ttm_global_release(struct drm_nouveau_private
*);
901 int nouveau_ttm_mmap(struct file
*, struct vm_area_struct
*);
904 int nouveau_dp_auxch(struct nouveau_i2c_chan
*auxch
, int cmd
, int addr
,
905 uint8_t *data
, int data_nr
);
906 bool nouveau_dp_detect(struct drm_encoder
*);
907 bool nouveau_dp_link_train(struct drm_encoder
*);
910 extern int nv04_fb_init(struct drm_device
*);
911 extern void nv04_fb_takedown(struct drm_device
*);
914 extern int nv10_fb_init(struct drm_device
*);
915 extern void nv10_fb_takedown(struct drm_device
*);
916 extern void nv10_fb_set_region_tiling(struct drm_device
*, int, uint32_t,
920 extern int nv30_fb_init(struct drm_device
*);
921 extern void nv30_fb_takedown(struct drm_device
*);
924 extern int nv40_fb_init(struct drm_device
*);
925 extern void nv40_fb_takedown(struct drm_device
*);
926 extern void nv40_fb_set_region_tiling(struct drm_device
*, int, uint32_t,
930 extern int nv50_fb_init(struct drm_device
*);
931 extern void nv50_fb_takedown(struct drm_device
*);
934 extern int nvc0_fb_init(struct drm_device
*);
935 extern void nvc0_fb_takedown(struct drm_device
*);
938 extern int nv04_fifo_init(struct drm_device
*);
939 extern void nv04_fifo_disable(struct drm_device
*);
940 extern void nv04_fifo_enable(struct drm_device
*);
941 extern bool nv04_fifo_reassign(struct drm_device
*, bool);
942 extern bool nv04_fifo_cache_flush(struct drm_device
*);
943 extern bool nv04_fifo_cache_pull(struct drm_device
*, bool);
944 extern int nv04_fifo_channel_id(struct drm_device
*);
945 extern int nv04_fifo_create_context(struct nouveau_channel
*);
946 extern void nv04_fifo_destroy_context(struct nouveau_channel
*);
947 extern int nv04_fifo_load_context(struct nouveau_channel
*);
948 extern int nv04_fifo_unload_context(struct drm_device
*);
951 extern int nv10_fifo_init(struct drm_device
*);
952 extern int nv10_fifo_channel_id(struct drm_device
*);
953 extern int nv10_fifo_create_context(struct nouveau_channel
*);
954 extern void nv10_fifo_destroy_context(struct nouveau_channel
*);
955 extern int nv10_fifo_load_context(struct nouveau_channel
*);
956 extern int nv10_fifo_unload_context(struct drm_device
*);
959 extern int nv40_fifo_init(struct drm_device
*);
960 extern int nv40_fifo_create_context(struct nouveau_channel
*);
961 extern void nv40_fifo_destroy_context(struct nouveau_channel
*);
962 extern int nv40_fifo_load_context(struct nouveau_channel
*);
963 extern int nv40_fifo_unload_context(struct drm_device
*);
966 extern int nv50_fifo_init(struct drm_device
*);
967 extern void nv50_fifo_takedown(struct drm_device
*);
968 extern int nv50_fifo_channel_id(struct drm_device
*);
969 extern int nv50_fifo_create_context(struct nouveau_channel
*);
970 extern void nv50_fifo_destroy_context(struct nouveau_channel
*);
971 extern int nv50_fifo_load_context(struct nouveau_channel
*);
972 extern int nv50_fifo_unload_context(struct drm_device
*);
975 extern int nvc0_fifo_init(struct drm_device
*);
976 extern void nvc0_fifo_takedown(struct drm_device
*);
977 extern void nvc0_fifo_disable(struct drm_device
*);
978 extern void nvc0_fifo_enable(struct drm_device
*);
979 extern bool nvc0_fifo_reassign(struct drm_device
*, bool);
980 extern bool nvc0_fifo_cache_flush(struct drm_device
*);
981 extern bool nvc0_fifo_cache_pull(struct drm_device
*, bool);
982 extern int nvc0_fifo_channel_id(struct drm_device
*);
983 extern int nvc0_fifo_create_context(struct nouveau_channel
*);
984 extern void nvc0_fifo_destroy_context(struct nouveau_channel
*);
985 extern int nvc0_fifo_load_context(struct nouveau_channel
*);
986 extern int nvc0_fifo_unload_context(struct drm_device
*);
989 extern struct nouveau_pgraph_object_class nv04_graph_grclass
[];
990 extern int nv04_graph_init(struct drm_device
*);
991 extern void nv04_graph_takedown(struct drm_device
*);
992 extern void nv04_graph_fifo_access(struct drm_device
*, bool);
993 extern struct nouveau_channel
*nv04_graph_channel(struct drm_device
*);
994 extern int nv04_graph_create_context(struct nouveau_channel
*);
995 extern void nv04_graph_destroy_context(struct nouveau_channel
*);
996 extern int nv04_graph_load_context(struct nouveau_channel
*);
997 extern int nv04_graph_unload_context(struct drm_device
*);
998 extern void nv04_graph_context_switch(struct drm_device
*);
1001 extern struct nouveau_pgraph_object_class nv10_graph_grclass
[];
1002 extern int nv10_graph_init(struct drm_device
*);
1003 extern void nv10_graph_takedown(struct drm_device
*);
1004 extern struct nouveau_channel
*nv10_graph_channel(struct drm_device
*);
1005 extern int nv10_graph_create_context(struct nouveau_channel
*);
1006 extern void nv10_graph_destroy_context(struct nouveau_channel
*);
1007 extern int nv10_graph_load_context(struct nouveau_channel
*);
1008 extern int nv10_graph_unload_context(struct drm_device
*);
1009 extern void nv10_graph_context_switch(struct drm_device
*);
1010 extern void nv10_graph_set_region_tiling(struct drm_device
*, int, uint32_t,
1011 uint32_t, uint32_t);
1014 extern struct nouveau_pgraph_object_class nv20_graph_grclass
[];
1015 extern struct nouveau_pgraph_object_class nv30_graph_grclass
[];
1016 extern int nv20_graph_create_context(struct nouveau_channel
*);
1017 extern void nv20_graph_destroy_context(struct nouveau_channel
*);
1018 extern int nv20_graph_load_context(struct nouveau_channel
*);
1019 extern int nv20_graph_unload_context(struct drm_device
*);
1020 extern int nv20_graph_init(struct drm_device
*);
1021 extern void nv20_graph_takedown(struct drm_device
*);
1022 extern int nv30_graph_init(struct drm_device
*);
1023 extern void nv20_graph_set_region_tiling(struct drm_device
*, int, uint32_t,
1024 uint32_t, uint32_t);
1027 extern struct nouveau_pgraph_object_class nv40_graph_grclass
[];
1028 extern int nv40_graph_init(struct drm_device
*);
1029 extern void nv40_graph_takedown(struct drm_device
*);
1030 extern struct nouveau_channel
*nv40_graph_channel(struct drm_device
*);
1031 extern int nv40_graph_create_context(struct nouveau_channel
*);
1032 extern void nv40_graph_destroy_context(struct nouveau_channel
*);
1033 extern int nv40_graph_load_context(struct nouveau_channel
*);
1034 extern int nv40_graph_unload_context(struct drm_device
*);
1035 extern void nv40_grctx_init(struct nouveau_grctx
*);
1036 extern void nv40_graph_set_region_tiling(struct drm_device
*, int, uint32_t,
1037 uint32_t, uint32_t);
1040 extern struct nouveau_pgraph_object_class nv50_graph_grclass
[];
1041 extern int nv50_graph_init(struct drm_device
*);
1042 extern void nv50_graph_takedown(struct drm_device
*);
1043 extern void nv50_graph_fifo_access(struct drm_device
*, bool);
1044 extern struct nouveau_channel
*nv50_graph_channel(struct drm_device
*);
1045 extern int nv50_graph_create_context(struct nouveau_channel
*);
1046 extern void nv50_graph_destroy_context(struct nouveau_channel
*);
1047 extern int nv50_graph_load_context(struct nouveau_channel
*);
1048 extern int nv50_graph_unload_context(struct drm_device
*);
1049 extern void nv50_graph_context_switch(struct drm_device
*);
1050 extern int nv50_grctx_init(struct nouveau_grctx
*);
1053 extern int nvc0_graph_init(struct drm_device
*);
1054 extern void nvc0_graph_takedown(struct drm_device
*);
1055 extern void nvc0_graph_fifo_access(struct drm_device
*, bool);
1056 extern struct nouveau_channel
*nvc0_graph_channel(struct drm_device
*);
1057 extern int nvc0_graph_create_context(struct nouveau_channel
*);
1058 extern void nvc0_graph_destroy_context(struct nouveau_channel
*);
1059 extern int nvc0_graph_load_context(struct nouveau_channel
*);
1060 extern int nvc0_graph_unload_context(struct drm_device
*);
1062 /* nv04_instmem.c */
1063 extern int nv04_instmem_init(struct drm_device
*);
1064 extern void nv04_instmem_takedown(struct drm_device
*);
1065 extern int nv04_instmem_suspend(struct drm_device
*);
1066 extern void nv04_instmem_resume(struct drm_device
*);
1067 extern int nv04_instmem_populate(struct drm_device
*, struct nouveau_gpuobj
*,
1069 extern void nv04_instmem_clear(struct drm_device
*, struct nouveau_gpuobj
*);
1070 extern int nv04_instmem_bind(struct drm_device
*, struct nouveau_gpuobj
*);
1071 extern int nv04_instmem_unbind(struct drm_device
*, struct nouveau_gpuobj
*);
1072 extern void nv04_instmem_flush(struct drm_device
*);
1074 /* nv50_instmem.c */
1075 extern int nv50_instmem_init(struct drm_device
*);
1076 extern void nv50_instmem_takedown(struct drm_device
*);
1077 extern int nv50_instmem_suspend(struct drm_device
*);
1078 extern void nv50_instmem_resume(struct drm_device
*);
1079 extern int nv50_instmem_populate(struct drm_device
*, struct nouveau_gpuobj
*,
1081 extern void nv50_instmem_clear(struct drm_device
*, struct nouveau_gpuobj
*);
1082 extern int nv50_instmem_bind(struct drm_device
*, struct nouveau_gpuobj
*);
1083 extern int nv50_instmem_unbind(struct drm_device
*, struct nouveau_gpuobj
*);
1084 extern void nv50_instmem_flush(struct drm_device
*);
1085 extern void nv84_instmem_flush(struct drm_device
*);
1086 extern void nv50_vm_flush(struct drm_device
*, int engine
);
1088 /* nvc0_instmem.c */
1089 extern int nvc0_instmem_init(struct drm_device
*);
1090 extern void nvc0_instmem_takedown(struct drm_device
*);
1091 extern int nvc0_instmem_suspend(struct drm_device
*);
1092 extern void nvc0_instmem_resume(struct drm_device
*);
1093 extern int nvc0_instmem_populate(struct drm_device
*, struct nouveau_gpuobj
*,
1095 extern void nvc0_instmem_clear(struct drm_device
*, struct nouveau_gpuobj
*);
1096 extern int nvc0_instmem_bind(struct drm_device
*, struct nouveau_gpuobj
*);
1097 extern int nvc0_instmem_unbind(struct drm_device
*, struct nouveau_gpuobj
*);
1098 extern void nvc0_instmem_flush(struct drm_device
*);
1101 extern int nv04_mc_init(struct drm_device
*);
1102 extern void nv04_mc_takedown(struct drm_device
*);
1105 extern int nv40_mc_init(struct drm_device
*);
1106 extern void nv40_mc_takedown(struct drm_device
*);
1109 extern int nv50_mc_init(struct drm_device
*);
1110 extern void nv50_mc_takedown(struct drm_device
*);
1113 extern int nv04_timer_init(struct drm_device
*);
1114 extern uint64_t nv04_timer_read(struct drm_device
*);
1115 extern void nv04_timer_takedown(struct drm_device
*);
1117 extern long nouveau_compat_ioctl(struct file
*file
, unsigned int cmd
,
1121 extern int nv04_dac_create(struct drm_connector
*, struct dcb_entry
*);
1122 extern uint32_t nv17_dac_sample_load(struct drm_encoder
*encoder
);
1123 extern int nv04_dac_output_offset(struct drm_encoder
*encoder
);
1124 extern void nv04_dac_update_dacclk(struct drm_encoder
*encoder
, bool enable
);
1125 extern bool nv04_dac_in_use(struct drm_encoder
*encoder
);
1128 extern int nv04_dfp_create(struct drm_connector
*, struct dcb_entry
*);
1129 extern int nv04_dfp_get_bound_head(struct drm_device
*dev
, struct dcb_entry
*dcbent
);
1130 extern void nv04_dfp_bind_head(struct drm_device
*dev
, struct dcb_entry
*dcbent
,
1132 extern void nv04_dfp_disable(struct drm_device
*dev
, int head
);
1133 extern void nv04_dfp_update_fp_control(struct drm_encoder
*encoder
, int mode
);
1136 extern int nv04_tv_identify(struct drm_device
*dev
, int i2c_index
);
1137 extern int nv04_tv_create(struct drm_connector
*, struct dcb_entry
*);
1140 extern int nv17_tv_create(struct drm_connector
*, struct dcb_entry
*);
1142 /* nv04_display.c */
1143 extern int nv04_display_early_init(struct drm_device
*);
1144 extern void nv04_display_late_takedown(struct drm_device
*);
1145 extern int nv04_display_create(struct drm_device
*);
1146 extern int nv04_display_init(struct drm_device
*);
1147 extern void nv04_display_destroy(struct drm_device
*);
1150 extern int nv04_crtc_create(struct drm_device
*, int index
);
1153 extern struct ttm_bo_driver nouveau_bo_driver
;
1154 extern int nouveau_bo_new(struct drm_device
*, struct nouveau_channel
*,
1155 int size
, int align
, uint32_t flags
,
1156 uint32_t tile_mode
, uint32_t tile_flags
,
1157 bool no_vm
, bool mappable
, struct nouveau_bo
**);
1158 extern int nouveau_bo_pin(struct nouveau_bo
*, uint32_t flags
);
1159 extern int nouveau_bo_unpin(struct nouveau_bo
*);
1160 extern int nouveau_bo_map(struct nouveau_bo
*);
1161 extern void nouveau_bo_unmap(struct nouveau_bo
*);
1162 extern void nouveau_bo_placement_set(struct nouveau_bo
*, uint32_t type
,
1164 extern u16
nouveau_bo_rd16(struct nouveau_bo
*nvbo
, unsigned index
);
1165 extern void nouveau_bo_wr16(struct nouveau_bo
*nvbo
, unsigned index
, u16 val
);
1166 extern u32
nouveau_bo_rd32(struct nouveau_bo
*nvbo
, unsigned index
);
1167 extern void nouveau_bo_wr32(struct nouveau_bo
*nvbo
, unsigned index
, u32 val
);
1169 /* nouveau_fence.c */
1170 struct nouveau_fence
;
1171 extern int nouveau_fence_init(struct nouveau_channel
*);
1172 extern void nouveau_fence_fini(struct nouveau_channel
*);
1173 extern void nouveau_fence_update(struct nouveau_channel
*);
1174 extern int nouveau_fence_new(struct nouveau_channel
*, struct nouveau_fence
**,
1176 extern int nouveau_fence_emit(struct nouveau_fence
*);
1177 struct nouveau_channel
*nouveau_fence_channel(struct nouveau_fence
*);
1178 extern bool nouveau_fence_signalled(void *obj
, void *arg
);
1179 extern int nouveau_fence_wait(void *obj
, void *arg
, bool lazy
, bool intr
);
1180 extern int nouveau_fence_flush(void *obj
, void *arg
);
1181 extern void nouveau_fence_unref(void **obj
);
1182 extern void *nouveau_fence_ref(void *obj
);
1185 extern int nouveau_gem_new(struct drm_device
*, struct nouveau_channel
*,
1186 int size
, int align
, uint32_t flags
,
1187 uint32_t tile_mode
, uint32_t tile_flags
,
1188 bool no_vm
, bool mappable
, struct nouveau_bo
**);
1189 extern int nouveau_gem_object_new(struct drm_gem_object
*);
1190 extern void nouveau_gem_object_del(struct drm_gem_object
*);
1191 extern int nouveau_gem_ioctl_new(struct drm_device
*, void *,
1193 extern int nouveau_gem_ioctl_pushbuf(struct drm_device
*, void *,
1195 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device
*, void *,
1197 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device
*, void *,
1199 extern int nouveau_gem_ioctl_info(struct drm_device
*, void *,
1203 int nv10_gpio_get(struct drm_device
*dev
, enum dcb_gpio_tag tag
);
1204 int nv10_gpio_set(struct drm_device
*dev
, enum dcb_gpio_tag tag
, int state
);
1207 int nv50_gpio_init(struct drm_device
*dev
);
1208 int nv50_gpio_get(struct drm_device
*dev
, enum dcb_gpio_tag tag
);
1209 int nv50_gpio_set(struct drm_device
*dev
, enum dcb_gpio_tag tag
, int state
);
1210 void nv50_gpio_irq_enable(struct drm_device
*, enum dcb_gpio_tag
, bool on
);
1213 int nv50_calc_pll(struct drm_device
*, struct pll_lims
*, int clk
,
1214 int *N1
, int *M1
, int *N2
, int *M2
, int *P
);
1215 int nv50_calc_pll2(struct drm_device
*, struct pll_lims
*,
1216 int clk
, int *N
, int *fN
, int *M
, int *P
);
1218 #ifndef ioread32_native
1220 #define ioread16_native ioread16be
1221 #define iowrite16_native iowrite16be
1222 #define ioread32_native ioread32be
1223 #define iowrite32_native iowrite32be
1224 #else /* def __BIG_ENDIAN */
1225 #define ioread16_native ioread16
1226 #define iowrite16_native iowrite16
1227 #define ioread32_native ioread32
1228 #define iowrite32_native iowrite32
1229 #endif /* def __BIG_ENDIAN else */
1230 #endif /* !ioread32_native */
1232 /* channel control reg access */
1233 static inline u32
nvchan_rd32(struct nouveau_channel
*chan
, unsigned reg
)
1235 return ioread32_native(chan
->user
+ reg
);
1238 static inline void nvchan_wr32(struct nouveau_channel
*chan
,
1239 unsigned reg
, u32 val
)
1241 iowrite32_native(val
, chan
->user
+ reg
);
1244 /* register access */
1245 static inline u32
nv_rd32(struct drm_device
*dev
, unsigned reg
)
1247 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1248 return ioread32_native(dev_priv
->mmio
+ reg
);
1251 static inline void nv_wr32(struct drm_device
*dev
, unsigned reg
, u32 val
)
1253 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1254 iowrite32_native(val
, dev_priv
->mmio
+ reg
);
1257 static inline void nv_mask(struct drm_device
*dev
, u32 reg
, u32 mask
, u32 val
)
1259 u32 tmp
= nv_rd32(dev
, reg
);
1262 nv_wr32(dev
, reg
, tmp
);
1265 static inline u8
nv_rd08(struct drm_device
*dev
, unsigned reg
)
1267 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1268 return ioread8(dev_priv
->mmio
+ reg
);
1271 static inline void nv_wr08(struct drm_device
*dev
, unsigned reg
, u8 val
)
1273 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1274 iowrite8(val
, dev_priv
->mmio
+ reg
);
1277 #define nv_wait(reg, mask, val) \
1278 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1281 static inline u32
nv_ri32(struct drm_device
*dev
, unsigned offset
)
1283 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1284 return ioread32_native(dev_priv
->ramin
+ offset
);
1287 static inline void nv_wi32(struct drm_device
*dev
, unsigned offset
, u32 val
)
1289 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1290 iowrite32_native(val
, dev_priv
->ramin
+ offset
);
1294 static inline u32
nv_ro32(struct drm_device
*dev
, struct nouveau_gpuobj
*obj
,
1297 return nv_ri32(dev
, obj
->im_pramin
->start
+ index
* 4);
1300 static inline void nv_wo32(struct drm_device
*dev
, struct nouveau_gpuobj
*obj
,
1301 unsigned index
, u32 val
)
1303 nv_wi32(dev
, obj
->im_pramin
->start
+ index
* 4, val
);
1308 * Argument d is (struct drm_device *).
1310 #define NV_PRINTK(level, d, fmt, arg...) \
1311 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1312 pci_name(d->pdev), ##arg)
1313 #ifndef NV_DEBUG_NOTRACE
1314 #define NV_DEBUG(d, fmt, arg...) do { \
1315 if (drm_debug & DRM_UT_DRIVER) { \
1316 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1320 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1321 if (drm_debug & DRM_UT_KMS) { \
1322 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1327 #define NV_DEBUG(d, fmt, arg...) do { \
1328 if (drm_debug & DRM_UT_DRIVER) \
1329 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1331 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1332 if (drm_debug & DRM_UT_KMS) \
1333 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1336 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1337 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1338 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1339 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1340 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1342 /* nouveau_reg_debug bitmask */
1344 NOUVEAU_REG_DEBUG_MC
= 0x1,
1345 NOUVEAU_REG_DEBUG_VIDEO
= 0x2,
1346 NOUVEAU_REG_DEBUG_FB
= 0x4,
1347 NOUVEAU_REG_DEBUG_EXTDEV
= 0x8,
1348 NOUVEAU_REG_DEBUG_CRTC
= 0x10,
1349 NOUVEAU_REG_DEBUG_RAMDAC
= 0x20,
1350 NOUVEAU_REG_DEBUG_VGACRTC
= 0x40,
1351 NOUVEAU_REG_DEBUG_RMVIO
= 0x80,
1352 NOUVEAU_REG_DEBUG_VGAATTR
= 0x100,
1353 NOUVEAU_REG_DEBUG_EVO
= 0x200,
1356 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1357 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1358 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1362 nv_two_heads(struct drm_device
*dev
)
1364 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1365 const int impl
= dev
->pci_device
& 0x0ff0;
1367 if (dev_priv
->card_type
>= NV_10
&& impl
!= 0x0100 &&
1368 impl
!= 0x0150 && impl
!= 0x01a0 && impl
!= 0x0200)
1375 nv_gf4_disp_arch(struct drm_device
*dev
)
1377 return nv_two_heads(dev
) && (dev
->pci_device
& 0x0ff0) != 0x0110;
1381 nv_two_reg_pll(struct drm_device
*dev
)
1383 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1384 const int impl
= dev
->pci_device
& 0x0ff0;
1386 if (impl
== 0x0310 || impl
== 0x0340 || dev_priv
->card_type
>= NV_40
)
1391 #define NV_SW 0x0000506e
1392 #define NV_SW_DMA_SEMAPHORE 0x00000060
1393 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1394 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1395 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1396 #define NV_SW_DMA_VBLSEM 0x0000018c
1397 #define NV_SW_VBLSEM_OFFSET 0x00000400
1398 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1399 #define NV_SW_VBLSEM_RELEASE 0x00000408
1401 #endif /* __NOUVEAU_DRV_H__ */