drivers/gpu/drm/nouveau/nouveau_gpuobj.c

   1 /*
   2  * Copyright (C) 2006 Ben Skeggs.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 /*
  29  * Authors:
  30  *   Ben Skeggs <darktama@iinet.net.au>
  31  */
  32
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "nouveau_drv.h"
  36 #include <nouveau_drm.h>
  37 #include <engine/fifo.h>
  38 #include <core/ramht.h>
  39 #include "nouveau_software.h"
  40
  41 struct nouveau_gpuobj_method {
  42         struct list_head head;
  43         u32 mthd;
  44         int (*exec)(struct nouveau_channel *, u32 class, u32 mthd, u32 data);
  45 };
  46
  47 struct nouveau_gpuobj_class {
  48         struct list_head head;
  49         struct list_head methods;
  50         u32 id;
  51         u32 engine;
  52 };
  53
  54 int
  55 nouveau_gpuobj_class_new(struct drm_device *dev, u32 class, u32 engine)
  56 {
  57         struct drm_nouveau_private *dev_priv = dev->dev_private;
  58         struct nouveau_gpuobj_class *oc;
  59
  60         oc = kzalloc(sizeof(*oc), GFP_KERNEL);
  61         if (!oc)
  62                 return -ENOMEM;
  63
  64         INIT_LIST_HEAD(&oc->methods);
  65         oc->id = class;
  66         oc->engine = engine;
  67         list_add(&oc->head, &dev_priv->classes);
  68         return 0;
  69 }
  70
  71 int
  72 nouveau_gpuobj_mthd_new(struct drm_device *dev, u32 class, u32 mthd,
  73                         int (*exec)(struct nouveau_channel *, u32, u32, u32))
  74 {
  75         struct drm_nouveau_private *dev_priv = dev->dev_private;
  76         struct nouveau_gpuobj_method *om;
  77         struct nouveau_gpuobj_class *oc;
  78
  79         list_for_each_entry(oc, &dev_priv->classes, head) {
  80                 if (oc->id == class)
  81                         goto found;
  82         }
  83
  84         return -EINVAL;
  85
  86 found:
  87         om = kzalloc(sizeof(*om), GFP_KERNEL);
  88         if (!om)
  89                 return -ENOMEM;
  90
  91         om->mthd = mthd;
  92         om->exec = exec;
  93         list_add(&om->head, &oc->methods);
  94         return 0;
  95 }
  96
  97 int
  98 nouveau_gpuobj_mthd_call(struct nouveau_channel *chan,
  99                          u32 class, u32 mthd, u32 data)
 100 {
 101         struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
 102         struct nouveau_gpuobj_method *om;
 103         struct nouveau_gpuobj_class *oc;
 104
 105         list_for_each_entry(oc, &dev_priv->classes, head) {
 106                 if (oc->id != class)
 107                         continue;
 108
 109                 list_for_each_entry(om, &oc->methods, head) {
 110                         if (om->mthd == mthd)
 111                                 return om->exec(chan, class, mthd, data);
 112                 }
 113         }
 114
 115         return -ENOENT;
 116 }
 117
 118 int
 119 nouveau_gpuobj_mthd_call2(struct drm_device *dev, int chid,
 120                           u32 class, u32 mthd, u32 data)
 121 {
 122         struct drm_nouveau_private *dev_priv = dev->dev_private;
 123         struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
 124         struct nouveau_channel *chan = NULL;
 125         unsigned long flags;
 126         int ret = -EINVAL;
 127
 128         spin_lock_irqsave(&dev_priv->channels.lock, flags);
 129         if (chid >= 0 && chid < pfifo->channels)
 130                 chan = dev_priv->channels.ptr[chid];
 131         if (chan)
 132                 ret = nouveau_gpuobj_mthd_call(chan, class, mthd, data);
 133         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
 134         return ret;
 135 }
 136
 137 void
 138 nv50_gpuobj_dma_init(struct nouveau_gpuobj *obj, u32 offset, int class,
 139                      u64 base, u64 size, int target, int access,
 140                      u32 type, u32 comp)
 141 {
 142         struct drm_nouveau_private *dev_priv = obj->dev->dev_private;
 143         u32 flags0;
 144
 145         flags0  = (comp << 29) | (type << 22) | class;
 146         flags0 |= 0x00100000;
 147
 148         switch (access) {
 149         case NV_MEM_ACCESS_RO: flags0 |= 0x00040000; break;
 150         case NV_MEM_ACCESS_RW:
 151         case NV_MEM_ACCESS_WO: flags0 |= 0x00080000; break;
 152         default:
 153                 break;
 154         }
 155
 156         switch (target) {
 157         case NV_MEM_TARGET_VRAM:
 158                 flags0 |= 0x00010000;
 159                 break;
 160         case NV_MEM_TARGET_PCI:
 161                 flags0 |= 0x00020000;
 162                 break;
 163         case NV_MEM_TARGET_PCI_NOSNOOP:
 164                 flags0 |= 0x00030000;
 165                 break;
 166         case NV_MEM_TARGET_GART:
 167                 base += dev_priv->gart_info.aper_base;
 168         default:
 169                 flags0 &= ~0x00100000;
 170                 break;
 171         }
 172
 173         /* convert to base + limit */
 174         size = (base + size) - 1;
 175
 176         nv_wo32(obj, offset + 0x00, flags0);
 177         nv_wo32(obj, offset + 0x04, lower_32_bits(size));
 178         nv_wo32(obj, offset + 0x08, lower_32_bits(base));
 179         nv_wo32(obj, offset + 0x0c, upper_32_bits(size) << 24 |
 180                                     upper_32_bits(base));
 181         nv_wo32(obj, offset + 0x10, 0x00000000);
 182         nv_wo32(obj, offset + 0x14, 0x00000000);
 183
 184         nvimem_flush(obj->dev);
 185 }
 186
 187 int
 188 nv50_gpuobj_dma_new(struct nouveau_channel *chan, int class, u64 base, u64 size,
 189                     int target, int access, u32 type, u32 comp,
 190                     struct nouveau_gpuobj **pobj)
 191 {
 192         struct drm_device *dev = chan->dev;
 193         int ret;
 194
 195         ret = nouveau_gpuobj_new(dev, chan, 24, 16, NVOBJ_FLAG_ZERO_FREE, pobj);
 196         if (ret)
 197                 return ret;
 198
 199         nv50_gpuobj_dma_init(*pobj, 0, class, base, size, target,
 200                              access, type, comp);
 201         return 0;
 202 }
 203
 204 int
 205 nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class, u64 base,
 206                        u64 size, int access, int target,
 207                        struct nouveau_gpuobj **pobj)
 208 {
 209         struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
 210         struct drm_device *dev = chan->dev;
 211         struct nouveau_gpuobj *obj;
 212         u32 flags0, flags2;
 213         int ret;
 214
 215         if (dev_priv->card_type >= NV_50) {
 216                 u32 comp = (target == NV_MEM_TARGET_VM) ? NV_MEM_COMP_VM : 0;
 217                 u32 type = (target == NV_MEM_TARGET_VM) ? NV_MEM_TYPE_VM : 0;
 218
 219                 return nv50_gpuobj_dma_new(chan, class, base, size,
 220                                            target, access, type, comp, pobj);
 221         }
 222
 223         if (target == NV_MEM_TARGET_GART) {
 224                 struct nouveau_gpuobj *gart = dev_priv->gart_info.sg_ctxdma;
 225
 226                 if (dev_priv->gart_info.type == NOUVEAU_GART_PDMA) {
 227                         if (base == 0) {
 228                                 nouveau_gpuobj_ref(gart, pobj);
 229                                 return 0;
 230                         }
 231
 232                         base   = nouveau_sgdma_get_physical(dev, base);
 233                         target = NV_MEM_TARGET_PCI;
 234                 } else {
 235                         base += dev_priv->gart_info.aper_base;
 236                         if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
 237                                 target = NV_MEM_TARGET_PCI_NOSNOOP;
 238                         else
 239                                 target = NV_MEM_TARGET_PCI;
 240                 }
 241         }
 242
 243         flags0  = class;
 244         flags0 |= 0x00003000; /* PT present, PT linear */
 245         flags2  = 0;
 246
 247         switch (target) {
 248         case NV_MEM_TARGET_PCI:
 249                 flags0 |= 0x00020000;
 250                 break;
 251         case NV_MEM_TARGET_PCI_NOSNOOP:
 252                 flags0 |= 0x00030000;
 253                 break;
 254         default:
 255                 break;
 256         }
 257
 258         switch (access) {
 259         case NV_MEM_ACCESS_RO:
 260                 flags0 |= 0x00004000;
 261                 break;
 262         case NV_MEM_ACCESS_WO:
 263                 flags0 |= 0x00008000;
 264         default:
 265                 flags2 |= 0x00000002;
 266                 break;
 267         }
 268
 269         flags0 |= (base & 0x00000fff) << 20;
 270         flags2 |= (base & 0xfffff000);
 271
 272         ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
 273         if (ret)
 274                 return ret;
 275
 276         nv_wo32(obj, 0x00, flags0);
 277         nv_wo32(obj, 0x04, size - 1);
 278         nv_wo32(obj, 0x08, flags2);
 279         nv_wo32(obj, 0x0c, flags2);
 280
 281         obj->engine = NVOBJ_ENGINE_SW;
 282         obj->class  = class;
 283         *pobj = obj;
 284         return 0;
 285 }
 286
 287 int
 288 nouveau_gpuobj_gr_new(struct nouveau_channel *chan, u32 handle, int class)
 289 {
 290         struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
 291         struct drm_device *dev = chan->dev;
 292         struct nouveau_gpuobj_class *oc;
 293         int ret;
 294
 295         NV_DEBUG(dev, "ch%d class=0x%04x\n", chan->id, class);
 296
 297         list_for_each_entry(oc, &dev_priv->classes, head) {
 298                 struct nouveau_exec_engine *eng = dev_priv->eng[oc->engine];
 299
 300                 if (oc->id != class)
 301                         continue;
 302
 303                 if (!chan->engctx[oc->engine]) {
 304                         ret = eng->context_new(chan, oc->engine);
 305                         if (ret)
 306                                 return ret;
 307                 }
 308
 309                 return eng->object_new(chan, oc->engine, handle, class);
 310         }
 311
 312         return -EINVAL;
 313 }
 314
 315 static int
 316 nv04_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
 317 {
 318         struct drm_device *dev = chan->dev;
 319         int ret;
 320
 321         ret = nouveau_gpuobj_new(dev, NULL, 0x10000, 0x1000,
 322                                  NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
 323         if (ret)
 324                 return ret;
 325
 326         return 0;
 327 }
 328
 329 static int
 330 nv50_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
 331 {
 332         struct drm_device *dev = chan->dev;
 333         int ret;
 334
 335         ret = nouveau_gpuobj_new(dev, NULL, 0x10000, 0x1000,
 336                                  NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
 337         if (ret)
 338                 return ret;
 339
 340         ret = nouveau_gpuobj_new(dev, chan, 0x0200, 0, 0, &chan->ramfc);
 341         if (ret)
 342                 return ret;
 343
 344         ret = nouveau_gpuobj_new(dev, chan, 0x1000, 0, 0, &chan->engptr);
 345         if (ret)
 346                 return ret;
 347
 348         ret = nouveau_gpuobj_new(dev, chan, 0x4000, 0, 0, &chan->vm_pd);
 349         if (ret)
 350                 return ret;
 351
 352         return 0;
 353 }
 354
 355 static int
 356 nv84_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
 357 {
 358         struct drm_device *dev = chan->dev;
 359         int ret;
 360
 361         ret = nouveau_gpuobj_new(dev, NULL, 0x10000, 0x1000,
 362                                  NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
 363         if (ret)
 364                 return ret;
 365
 366         ret = nouveau_gpuobj_new(dev, chan, 0x0200, 0, 0, &chan->engptr);
 367         if (ret)
 368                 return ret;
 369
 370         ret = nouveau_gpuobj_new(dev, chan, 0x4000, 0, 0, &chan->vm_pd);
 371         if (ret)
 372                 return ret;
 373
 374         return 0;
 375 }
 376
 377 static int
 378 nvc0_gpuobj_channel_init(struct nouveau_channel *chan, struct nouveau_vm *vm)
 379 {
 380         struct drm_device *dev = chan->dev;
 381         int ret;
 382
 383         ret = nouveau_gpuobj_new(dev, NULL, 4096, 0x1000, 0, &chan->ramin);
 384         if (ret)
 385                 return ret;
 386
 387         ret = nouveau_gpuobj_new(dev, NULL, 65536, 0x1000, 0, &chan->vm_pd);
 388         if (ret)
 389                 return ret;
 390
 391         nouveau_vm_ref(vm, &chan->vm, chan->vm_pd);
 392
 393         nv_wo32(chan->ramin, 0x0200, lower_32_bits(chan->vm_pd->addr));
 394         nv_wo32(chan->ramin, 0x0204, upper_32_bits(chan->vm_pd->addr));
 395         nv_wo32(chan->ramin, 0x0208, 0xffffffff);
 396         nv_wo32(chan->ramin, 0x020c, 0x000000ff);
 397
 398         return 0;
 399 }
 400
 401 int
 402 nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
 403                             uint32_t vram_h, uint32_t tt_h)
 404 {
 405         struct drm_device *dev = chan->dev;
 406         struct drm_nouveau_private *dev_priv = dev->dev_private;
 407         struct nouveau_fpriv *fpriv = nouveau_fpriv(chan->file_priv);
 408         struct nouveau_vm *vm = fpriv ? fpriv->vm : dev_priv->chan_vm;
 409         struct nouveau_gpuobj *vram = NULL, *tt = NULL;
 410         int ret;
 411
 412         NV_DEBUG(dev, "ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h);
 413         if (dev_priv->card_type >= NV_C0)
 414                 return nvc0_gpuobj_channel_init(chan, vm);
 415
 416         /* Allocate a chunk of memory for per-channel object storage */
 417         if (dev_priv->chipset >= 0x84)
 418                 ret = nv84_gpuobj_channel_init_pramin(chan);
 419         else
 420         if (dev_priv->chipset == 0x50)
 421                 ret = nv50_gpuobj_channel_init_pramin(chan);
 422         else
 423                 ret = nv04_gpuobj_channel_init_pramin(chan);
 424         if (ret) {
 425                 NV_ERROR(dev, "init pramin\n");
 426                 return ret;
 427         }
 428
 429         /* NV50 VM
 430          *  - Allocate per-channel page-directory
 431          *  - Link with shared channel VM
 432          */
 433         if (vm)
 434                 nouveau_vm_ref(vm, &chan->vm, chan->vm_pd);
 435
 436         /* RAMHT */
 437         if (dev_priv->card_type < NV_50) {
 438                 nouveau_ramht_ref(dev_priv->ramht, &chan->ramht, NULL);
 439         } else {
 440                 struct nouveau_gpuobj *ramht = NULL;
 441
 442                 ret = nouveau_gpuobj_new(dev, chan, 0x8000, 16,
 443                                          NVOBJ_FLAG_ZERO_ALLOC, &ramht);
 444                 if (ret)
 445                         return ret;
 446
 447                 ret = nouveau_ramht_new(dev, ramht, &chan->ramht);
 448                 nouveau_gpuobj_ref(NULL, &ramht);
 449                 if (ret)
 450                         return ret;
 451         }
 452
 453         /* VRAM ctxdma */
 454         if (dev_priv->card_type >= NV_50) {
 455                 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
 456                                              0, (1ULL << 40), NV_MEM_ACCESS_RW,
 457                                              NV_MEM_TARGET_VM, &vram);
 458                 if (ret) {
 459                         NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret);
 460                         return ret;
 461                 }
 462         } else {
 463                 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
 464                                              0, dev_priv->fb_available_size,
 465                                              NV_MEM_ACCESS_RW,
 466                                              NV_MEM_TARGET_VRAM, &vram);
 467                 if (ret) {
 468                         NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret);
 469                         return ret;
 470                 }
 471         }
 472
 473         ret = nouveau_ramht_insert(chan, vram_h, vram);
 474         nouveau_gpuobj_ref(NULL, &vram);
 475         if (ret) {
 476                 NV_ERROR(dev, "Error adding VRAM ctxdma to RAMHT: %d\n", ret);
 477                 return ret;
 478         }
 479
 480         /* TT memory ctxdma */
 481         if (dev_priv->card_type >= NV_50) {
 482                 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
 483                                              0, (1ULL << 40), NV_MEM_ACCESS_RW,
 484                                              NV_MEM_TARGET_VM, &tt);
 485         } else {
 486                 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
 487                                              0, dev_priv->gart_info.aper_size,
 488                                              NV_MEM_ACCESS_RW,
 489                                              NV_MEM_TARGET_GART, &tt);
 490         }
 491
 492         if (ret) {
 493                 NV_ERROR(dev, "Error creating TT ctxdma: %d\n", ret);
 494                 return ret;
 495         }
 496
 497         ret = nouveau_ramht_insert(chan, tt_h, tt);
 498         nouveau_gpuobj_ref(NULL, &tt);
 499         if (ret) {
 500                 NV_ERROR(dev, "Error adding TT ctxdma to RAMHT: %d\n", ret);
 501                 return ret;
 502         }
 503
 504         return 0;
 505 }
 506
 507 void
 508 nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan)
 509 {
 510         NV_DEBUG(chan->dev, "ch%d\n", chan->id);
 511
 512         nouveau_vm_ref(NULL, &chan->vm, chan->vm_pd);
 513         nouveau_gpuobj_ref(NULL, &chan->vm_pd);
 514         nouveau_gpuobj_ref(NULL, &chan->ramfc);
 515         nouveau_gpuobj_ref(NULL, &chan->engptr);
 516
 517         nouveau_gpuobj_ref(NULL, &chan->ramin);
 518 }