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drm/nouveau/pm: implement DDR2/DDR3/GDDR3/GDDR5 MR generation and validation
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_mem.c
1 /*
2 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3 * Copyright 2005 Stephane Marchesin
4 *
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 *
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #include "drmP.h"
34 #include "drm.h"
35 #include "drm_sarea.h"
36
37 #include "nouveau_drv.h"
38 #include "nouveau_pm.h"
39 #include "nouveau_mm.h"
40 #include "nouveau_vm.h"
41
42 /*
43 * NV10-NV40 tiling helpers
44 */
45
46 static void
47 nv10_mem_update_tile_region(struct drm_device *dev,
48 struct nouveau_tile_reg *tile, uint32_t addr,
49 uint32_t size, uint32_t pitch, uint32_t flags)
50 {
51 struct drm_nouveau_private *dev_priv = dev->dev_private;
52 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
53 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
54 int i = tile - dev_priv->tile.reg, j;
55 unsigned long save;
56
57 nouveau_fence_unref(&tile->fence);
58
59 if (tile->pitch)
60 pfb->free_tile_region(dev, i);
61
62 if (pitch)
63 pfb->init_tile_region(dev, i, addr, size, pitch, flags);
64
65 spin_lock_irqsave(&dev_priv->context_switch_lock, save);
66 pfifo->reassign(dev, false);
67 pfifo->cache_pull(dev, false);
68
69 nouveau_wait_for_idle(dev);
70
71 pfb->set_tile_region(dev, i);
72 for (j = 0; j < NVOBJ_ENGINE_NR; j++) {
73 if (dev_priv->eng[j] && dev_priv->eng[j]->set_tile_region)
74 dev_priv->eng[j]->set_tile_region(dev, i);
75 }
76
77 pfifo->cache_pull(dev, true);
78 pfifo->reassign(dev, true);
79 spin_unlock_irqrestore(&dev_priv->context_switch_lock, save);
80 }
81
82 static struct nouveau_tile_reg *
83 nv10_mem_get_tile_region(struct drm_device *dev, int i)
84 {
85 struct drm_nouveau_private *dev_priv = dev->dev_private;
86 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
87
88 spin_lock(&dev_priv->tile.lock);
89
90 if (!tile->used &&
91 (!tile->fence || nouveau_fence_signalled(tile->fence)))
92 tile->used = true;
93 else
94 tile = NULL;
95
96 spin_unlock(&dev_priv->tile.lock);
97 return tile;
98 }
99
100 void
101 nv10_mem_put_tile_region(struct drm_device *dev, struct nouveau_tile_reg *tile,
102 struct nouveau_fence *fence)
103 {
104 struct drm_nouveau_private *dev_priv = dev->dev_private;
105
106 if (tile) {
107 spin_lock(&dev_priv->tile.lock);
108 if (fence) {
109 /* Mark it as pending. */
110 tile->fence = fence;
111 nouveau_fence_ref(fence);
112 }
113
114 tile->used = false;
115 spin_unlock(&dev_priv->tile.lock);
116 }
117 }
118
119 struct nouveau_tile_reg *
120 nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
121 uint32_t pitch, uint32_t flags)
122 {
123 struct drm_nouveau_private *dev_priv = dev->dev_private;
124 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
125 struct nouveau_tile_reg *tile, *found = NULL;
126 int i;
127
128 for (i = 0; i < pfb->num_tiles; i++) {
129 tile = nv10_mem_get_tile_region(dev, i);
130
131 if (pitch && !found) {
132 found = tile;
133 continue;
134
135 } else if (tile && tile->pitch) {
136 /* Kill an unused tile region. */
137 nv10_mem_update_tile_region(dev, tile, 0, 0, 0, 0);
138 }
139
140 nv10_mem_put_tile_region(dev, tile, NULL);
141 }
142
143 if (found)
144 nv10_mem_update_tile_region(dev, found, addr, size,
145 pitch, flags);
146 return found;
147 }
148
149 /*
150 * Cleanup everything
151 */
152 void
153 nouveau_mem_vram_fini(struct drm_device *dev)
154 {
155 struct drm_nouveau_private *dev_priv = dev->dev_private;
156
157 ttm_bo_device_release(&dev_priv->ttm.bdev);
158
159 nouveau_ttm_global_release(dev_priv);
160
161 if (dev_priv->fb_mtrr >= 0) {
162 drm_mtrr_del(dev_priv->fb_mtrr,
163 pci_resource_start(dev->pdev, 1),
164 pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
165 dev_priv->fb_mtrr = -1;
166 }
167 }
168
169 void
170 nouveau_mem_gart_fini(struct drm_device *dev)
171 {
172 nouveau_sgdma_takedown(dev);
173
174 if (drm_core_has_AGP(dev) && dev->agp) {
175 struct drm_agp_mem *entry, *tempe;
176
177 /* Remove AGP resources, but leave dev->agp
178 intact until drv_cleanup is called. */
179 list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
180 if (entry->bound)
181 drm_unbind_agp(entry->memory);
182 drm_free_agp(entry->memory, entry->pages);
183 kfree(entry);
184 }
185 INIT_LIST_HEAD(&dev->agp->memory);
186
187 if (dev->agp->acquired)
188 drm_agp_release(dev);
189
190 dev->agp->acquired = 0;
191 dev->agp->enabled = 0;
192 }
193 }
194
195 bool
196 nouveau_mem_flags_valid(struct drm_device *dev, u32 tile_flags)
197 {
198 if (!(tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK))
199 return true;
200
201 return false;
202 }
203
204 #if __OS_HAS_AGP
205 static unsigned long
206 get_agp_mode(struct drm_device *dev, unsigned long mode)
207 {
208 struct drm_nouveau_private *dev_priv = dev->dev_private;
209
210 /*
211 * FW seems to be broken on nv18, it makes the card lock up
212 * randomly.
213 */
214 if (dev_priv->chipset == 0x18)
215 mode &= ~PCI_AGP_COMMAND_FW;
216
217 /*
218 * AGP mode set in the command line.
219 */
220 if (nouveau_agpmode > 0) {
221 bool agpv3 = mode & 0x8;
222 int rate = agpv3 ? nouveau_agpmode / 4 : nouveau_agpmode;
223
224 mode = (mode & ~0x7) | (rate & 0x7);
225 }
226
227 return mode;
228 }
229 #endif
230
231 int
232 nouveau_mem_reset_agp(struct drm_device *dev)
233 {
234 #if __OS_HAS_AGP
235 uint32_t saved_pci_nv_1, pmc_enable;
236 int ret;
237
238 /* First of all, disable fast writes, otherwise if it's
239 * already enabled in the AGP bridge and we disable the card's
240 * AGP controller we might be locking ourselves out of it. */
241 if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) |
242 dev->agp->mode) & PCI_AGP_COMMAND_FW) {
243 struct drm_agp_info info;
244 struct drm_agp_mode mode;
245
246 ret = drm_agp_info(dev, &info);
247 if (ret)
248 return ret;
249
250 mode.mode = get_agp_mode(dev, info.mode) & ~PCI_AGP_COMMAND_FW;
251 ret = drm_agp_enable(dev, mode);
252 if (ret)
253 return ret;
254 }
255
256 saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
257
258 /* clear busmaster bit */
259 nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
260 /* disable AGP */
261 nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);
262
263 /* power cycle pgraph, if enabled */
264 pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
265 if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
266 nv_wr32(dev, NV03_PMC_ENABLE,
267 pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
268 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
269 NV_PMC_ENABLE_PGRAPH);
270 }
271
272 /* and restore (gives effect of resetting AGP) */
273 nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
274 #endif
275
276 return 0;
277 }
278
279 int
280 nouveau_mem_init_agp(struct drm_device *dev)
281 {
282 #if __OS_HAS_AGP
283 struct drm_nouveau_private *dev_priv = dev->dev_private;
284 struct drm_agp_info info;
285 struct drm_agp_mode mode;
286 int ret;
287
288 if (!dev->agp->acquired) {
289 ret = drm_agp_acquire(dev);
290 if (ret) {
291 NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
292 return ret;
293 }
294 }
295
296 nouveau_mem_reset_agp(dev);
297
298 ret = drm_agp_info(dev, &info);
299 if (ret) {
300 NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
301 return ret;
302 }
303
304 /* see agp.h for the AGPSTAT_* modes available */
305 mode.mode = get_agp_mode(dev, info.mode);
306 ret = drm_agp_enable(dev, mode);
307 if (ret) {
308 NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
309 return ret;
310 }
311
312 dev_priv->gart_info.type = NOUVEAU_GART_AGP;
313 dev_priv->gart_info.aper_base = info.aperture_base;
314 dev_priv->gart_info.aper_size = info.aperture_size;
315 #endif
316 return 0;
317 }
318
319 static const struct vram_types {
320 int value;
321 const char *name;
322 } vram_type_map[] = {
323 { NV_MEM_TYPE_STOLEN , "stolen system memory" },
324 { NV_MEM_TYPE_SGRAM , "SGRAM" },
325 { NV_MEM_TYPE_SDRAM , "SDRAM" },
326 { NV_MEM_TYPE_DDR1 , "DDR1" },
327 { NV_MEM_TYPE_DDR2 , "DDR2" },
328 { NV_MEM_TYPE_DDR3 , "DDR3" },
329 { NV_MEM_TYPE_GDDR2 , "GDDR2" },
330 { NV_MEM_TYPE_GDDR3 , "GDDR3" },
331 { NV_MEM_TYPE_GDDR4 , "GDDR4" },
332 { NV_MEM_TYPE_GDDR5 , "GDDR5" },
333 { NV_MEM_TYPE_UNKNOWN, "unknown type" }
334 };
335
336 int
337 nouveau_mem_vram_init(struct drm_device *dev)
338 {
339 struct drm_nouveau_private *dev_priv = dev->dev_private;
340 struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
341 const struct vram_types *vram_type;
342 int ret, dma_bits;
343
344 dma_bits = 32;
345 if (dev_priv->card_type >= NV_50) {
346 if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
347 dma_bits = 40;
348 } else
349 if (0 && pci_is_pcie(dev->pdev) &&
350 dev_priv->chipset > 0x40 &&
351 dev_priv->chipset != 0x45) {
352 if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(39)))
353 dma_bits = 39;
354 }
355
356 ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
357 if (ret)
358 return ret;
359 ret = pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
360 if (ret) {
361 /* Reset to default value. */
362 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(32));
363 }
364
365
366 ret = nouveau_ttm_global_init(dev_priv);
367 if (ret)
368 return ret;
369
370 ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
371 dev_priv->ttm.bo_global_ref.ref.object,
372 &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
373 dma_bits <= 32 ? true : false);
374 if (ret) {
375 NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
376 return ret;
377 }
378
379 vram_type = vram_type_map;
380 while (vram_type->value != NV_MEM_TYPE_UNKNOWN) {
381 if (nouveau_vram_type) {
382 if (!strcasecmp(nouveau_vram_type, vram_type->name))
383 break;
384 dev_priv->vram_type = vram_type->value;
385 } else {
386 if (vram_type->value == dev_priv->vram_type)
387 break;
388 }
389 vram_type++;
390 }
391
392 NV_INFO(dev, "Detected %dMiB VRAM (%s)\n",
393 (int)(dev_priv->vram_size >> 20), vram_type->name);
394 if (dev_priv->vram_sys_base) {
395 NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
396 dev_priv->vram_sys_base);
397 }
398
399 dev_priv->fb_available_size = dev_priv->vram_size;
400 dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
401 if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
402 dev_priv->fb_mappable_pages = pci_resource_len(dev->pdev, 1);
403 dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
404
405 dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
406 dev_priv->fb_aper_free = dev_priv->fb_available_size;
407
408 /* mappable vram */
409 ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
410 dev_priv->fb_available_size >> PAGE_SHIFT);
411 if (ret) {
412 NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
413 return ret;
414 }
415
416 if (dev_priv->card_type < NV_50) {
417 ret = nouveau_bo_new(dev, 256*1024, 0, TTM_PL_FLAG_VRAM,
418 0, 0, &dev_priv->vga_ram);
419 if (ret == 0)
420 ret = nouveau_bo_pin(dev_priv->vga_ram,
421 TTM_PL_FLAG_VRAM);
422
423 if (ret) {
424 NV_WARN(dev, "failed to reserve VGA memory\n");
425 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
426 }
427 }
428
429 dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
430 pci_resource_len(dev->pdev, 1),
431 DRM_MTRR_WC);
432 return 0;
433 }
434
435 int
436 nouveau_mem_gart_init(struct drm_device *dev)
437 {
438 struct drm_nouveau_private *dev_priv = dev->dev_private;
439 struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
440 int ret;
441
442 dev_priv->gart_info.type = NOUVEAU_GART_NONE;
443
444 #if !defined(__powerpc__) && !defined(__ia64__)
445 if (drm_pci_device_is_agp(dev) && dev->agp && nouveau_agpmode) {
446 ret = nouveau_mem_init_agp(dev);
447 if (ret)
448 NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
449 }
450 #endif
451
452 if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
453 ret = nouveau_sgdma_init(dev);
454 if (ret) {
455 NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
456 return ret;
457 }
458 }
459
460 NV_INFO(dev, "%d MiB GART (aperture)\n",
461 (int)(dev_priv->gart_info.aper_size >> 20));
462 dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
463
464 ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
465 dev_priv->gart_info.aper_size >> PAGE_SHIFT);
466 if (ret) {
467 NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
468 return ret;
469 }
470
471 return 0;
472 }
473
474 static void
475 nv40_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
476 struct nouveau_pm_tbl_entry *e,
477 struct nouveau_pm_memtiming *t,
478 struct nouveau_pm_memtiming *boot)
479 {
480
481 t->reg[0] = (e->tRP << 24 | e->tRAS << 16 | e->tRFC << 8 | e->tRC);
482
483 /* XXX: I don't trust the -1's and +1's... they must come
484 * from somewhere! */
485 t->reg[1] = (e->tWR + 2 + (t->tCWL - 1)) << 24 |
486 1 << 16 |
487 (e->tWTR + 2 + (t->tCWL - 1)) << 8 |
488 (e->tCL + 2 - (t->tCWL - 1));
489
490 t->reg[2] = 0x20200000 |
491 ((t->tCWL - 1) << 24 |
492 e->tRRD << 16 |
493 e->tRCDWR << 8 |
494 e->tRCDRD);
495
496 NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x\n", t->id,
497 t->reg[0], t->reg[1], t->reg[2]);
498 }
499
500 static void
501 nv50_mem_timing_entry(struct drm_device *dev, struct bit_entry *P,
502 struct nouveau_pm_tbl_header *hdr,
503 struct nouveau_pm_tbl_entry *e,
504 struct nouveau_pm_memtiming *t,
505 struct nouveau_pm_memtiming *boot)
506 {
507 struct drm_nouveau_private *dev_priv = dev->dev_private;
508 uint8_t unk18 = 1, unk20 = 0, unk21 = 0, tmp7_3;
509
510 switch (min(hdr->entry_len, (u8) 22)) {
511 case 22:
512 unk21 = e->tUNK_21;
513 case 21:
514 unk20 = e->tUNK_20;
515 case 20:
516 if (e->tCWL > 0)
517 t->tCWL = e->tCWL;
518 case 19:
519 unk18 = e->tUNK_18;
520 break;
521 }
522
523 t->reg[0] = (e->tRP << 24 | e->tRAS << 16 | e->tRFC << 8 | e->tRC);
524
525 t->reg[1] = (e->tWR + 2 + (t->tCWL - 1)) << 24 |
526 max(unk18, (u8) 1) << 16 |
527 (e->tWTR + 2 + (t->tCWL - 1)) << 8;
528
529 t->reg[2] = ((t->tCWL - 1) << 24 |
530 e->tRRD << 16 |
531 e->tRCDWR << 8 |
532 e->tRCDRD);
533
534 t->reg[4] = e->tUNK_13 << 8 | e->tUNK_13;
535
536 t->reg[5] = (e->tRFC << 24 | max(e->tRCDRD, e->tRCDWR) << 16 | e->tRP);
537
538 t->reg[8] = boot->reg[8] & 0xffffff00;
539
540 if (P->version == 1) {
541 t->reg[1] |= (e->tCL + 2 - (t->tCWL - 1));
542
543 t->reg[3] = (0x14 + e->tCL) << 24 |
544 0x16 << 16 |
545 (e->tCL - 1) << 8 |
546 (e->tCL - 1);
547
548 t->reg[4] |= boot->reg[4] & 0xffff0000;
549
550 t->reg[6] = (0x33 - t->tCWL) << 16 |
551 t->tCWL << 8 |
552 (0x2e + e->tCL - t->tCWL);
553
554 t->reg[7] = 0x4000202 | (e->tCL - 1) << 16;
555
556 /* XXX: P.version == 1 only has DDR2 and GDDR3? */
557 if (dev_priv->vram_type == NV_MEM_TYPE_DDR2) {
558 t->reg[5] |= (e->tCL + 3) << 8;
559 t->reg[6] |= (t->tCWL - 2) << 8;
560 t->reg[8] |= (e->tCL - 4);
561 } else {
562 t->reg[5] |= (e->tCL + 2) << 8;
563 t->reg[6] |= t->tCWL << 8;
564 t->reg[8] |= (e->tCL - 2);
565 }
566 } else {
567 t->reg[1] |= (5 + e->tCL - (t->tCWL));
568
569 /* XXX: 0xb? 0x30? */
570 t->reg[3] = (0x30 + e->tCL) << 24 |
571 (boot->reg[3] & 0x00ff0000)|
572 (0xb + e->tCL) << 8 |
573 (e->tCL - 1);
574
575 t->reg[4] |= (unk20 << 24 | unk21 << 16);
576
577 /* XXX: +6? */
578 t->reg[5] |= (t->tCWL + 6) << 8;
579
580 t->reg[6] = (0x5a + e->tCL) << 16 |
581 (6 - e->tCL + t->tCWL) << 8 |
582 (0x50 + e->tCL - t->tCWL);
583
584 tmp7_3 = (boot->reg[7] & 0xff000000) >> 24;
585 t->reg[7] = (tmp7_3 << 24) |
586 ((tmp7_3 - 6 + e->tCL) << 16) |
587 0x202;
588 }
589
590 NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", t->id,
591 t->reg[0], t->reg[1], t->reg[2], t->reg[3]);
592 NV_DEBUG(dev, " 230: %08x %08x %08x %08x\n",
593 t->reg[4], t->reg[5], t->reg[6], t->reg[7]);
594 NV_DEBUG(dev, " 240: %08x\n", t->reg[8]);
595 }
596
597 static void
598 nvc0_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
599 struct nouveau_pm_tbl_entry *e,
600 struct nouveau_pm_memtiming *t,
601 struct nouveau_pm_memtiming *boot)
602 {
603 if (e->tCWL > 0)
604 t->tCWL = e->tCWL;
605
606 t->reg[0] = (e->tRP << 24 | (e->tRAS & 0x7f) << 17 |
607 e->tRFC << 8 | e->tRC);
608
609 t->reg[1] = (boot->reg[1] & 0xff000000) |
610 (e->tRCDWR & 0x0f) << 20 |
611 (e->tRCDRD & 0x0f) << 14 |
612 (e->tCWL << 7) |
613 (e->tCL & 0x0f);
614
615 t->reg[2] = (boot->reg[2] & 0xff0000ff) |
616 e->tWR << 16 | e->tWTR << 8;
617
618 t->reg[3] = (e->tUNK_20 & 0xf) << 9 |
619 (e->tUNK_21 & 0xf) << 5 |
620 (e->tUNK_13 & 0x1f);
621
622 t->reg[4] = (boot->reg[4] & 0xfff00fff) |
623 (e->tRRD&0x1f) << 15;
624
625 NV_DEBUG(dev, "Entry %d: 290: %08x %08x %08x %08x\n", t->id,
626 t->reg[0], t->reg[1], t->reg[2], t->reg[3]);
627 NV_DEBUG(dev, " 2a0: %08x\n", t->reg[4]);
628 }
629
630 /**
631 * MR generation methods
632 */
633
634 static bool
635 nouveau_mem_ddr2_mr(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
636 struct nouveau_pm_tbl_entry *e,
637 struct nouveau_pm_memtiming *t,
638 struct nouveau_pm_memtiming *boot)
639 {
640 t->drive_strength = 0;
641 if (hdr->entry_len < 15) {
642 t->odt = boot->odt;
643 } else {
644 t->odt = e->RAM_FT1 & 0x07;
645 }
646
647 if (e->tCL >= NV_MEM_CL_DDR2_MAX) {
648 NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL);
649 return false;
650 }
651
652 if (e->tWR >= NV_MEM_WR_DDR2_MAX) {
653 NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR);
654 return false;
655 }
656
657 if (t->odt > 3) {
658 NV_WARN(dev, "(%u) Invalid odt value, assuming disabled: %x",
659 t->id, t->odt);
660 t->odt = 0;
661 }
662
663 t->mr[0] = (boot->mr[0] & 0x100f) |
664 (e->tCL) << 4 |
665 (e->tWR - 1) << 9;
666 t->mr[1] = (boot->mr[1] & 0x101fbb) |
667 (t->odt & 0x1) << 2 |
668 (t->odt & 0x2) << 5;
669
670 NV_DEBUG(dev, "(%u) MR: %08x", t->id, t->mr[0]);
671 return true;
672 }
673
674 uint8_t nv_mem_wr_lut_ddr3[NV_MEM_WR_DDR3_MAX] = {
675 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
676
677 static bool
678 nouveau_mem_ddr3_mr(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
679 struct nouveau_pm_tbl_entry *e,
680 struct nouveau_pm_memtiming *t,
681 struct nouveau_pm_memtiming *boot)
682 {
683 u8 cl = e->tCL - 4;
684
685 t->drive_strength = 0;
686 if (hdr->entry_len < 15) {
687 t->odt = boot->odt;
688 } else {
689 t->odt = e->RAM_FT1 & 0x07;
690 }
691
692 if (e->tCL >= NV_MEM_CL_DDR3_MAX || e->tCL < 4) {
693 NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL);
694 return false;
695 }
696
697 if (e->tWR >= NV_MEM_WR_DDR3_MAX || e->tWR < 4) {
698 NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR);
699 return false;
700 }
701
702 if (e->tCWL < 5) {
703 NV_WARN(dev, "(%u) Invalid tCWL: %u", t->id, e->tCWL);
704 return false;
705 }
706
707 t->mr[0] = (boot->mr[0] & 0x180b) |
708 /* CAS */
709 (cl & 0x7) << 4 |
710 (cl & 0x8) >> 1 |
711 (nv_mem_wr_lut_ddr3[e->tWR]) << 9;
712 t->mr[1] = (boot->mr[1] & 0x101dbb) |
713 (t->odt & 0x1) << 2 |
714 (t->odt & 0x2) << 5 |
715 (t->odt & 0x4) << 7;
716 t->mr[2] = (boot->mr[2] & 0x20ffb7) | (e->tCWL - 5) << 3;
717
718 NV_DEBUG(dev, "(%u) MR: %08x %08x", t->id, t->mr[0], t->mr[2]);
719 return true;
720 }
721
722 uint8_t nv_mem_cl_lut_gddr3[NV_MEM_CL_GDDR3_MAX] = {
723 0, 0, 0, 0, 4, 5, 6, 7, 0, 1, 2, 3, 8, 9, 10, 11};
724 uint8_t nv_mem_wr_lut_gddr3[NV_MEM_WR_GDDR3_MAX] = {
725 0, 0, 0, 0, 0, 2, 3, 8, 9, 10, 11, 0, 0, 1, 1, 0, 3};
726
727 static bool
728 nouveau_mem_gddr3_mr(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
729 struct nouveau_pm_tbl_entry *e,
730 struct nouveau_pm_memtiming *t,
731 struct nouveau_pm_memtiming *boot)
732 {
733 if (hdr->entry_len < 15) {
734 t->drive_strength = boot->drive_strength;
735 t->odt = boot->odt;
736 } else {
737 t->drive_strength = (e->RAM_FT1 & 0x30) >> 4;
738 t->odt = e->RAM_FT1 & 0x07;
739 }
740
741 if (e->tCL >= NV_MEM_CL_GDDR3_MAX) {
742 NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL);
743 return false;
744 }
745
746 if (e->tWR >= NV_MEM_WR_GDDR3_MAX) {
747 NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR);
748 return false;
749 }
750
751 if (t->odt > 3) {
752 NV_WARN(dev, "(%u) Invalid odt value, assuming autocal: %x",
753 t->id, t->odt);
754 t->odt = 0;
755 }
756
757 t->mr[0] = (boot->mr[0] & 0xe0b) |
758 /* CAS */
759 ((nv_mem_cl_lut_gddr3[e->tCL] & 0x7) << 4) |
760 ((nv_mem_cl_lut_gddr3[e->tCL] & 0x8) >> 2);
761 t->mr[1] = (boot->mr[1] & 0x100f40) | t->drive_strength |
762 (t->odt << 2) |
763 (nv_mem_wr_lut_gddr3[e->tWR] & 0xf) << 4;
764
765 NV_DEBUG(dev, "(%u) MR: %08x %08x", t->id, t->mr[0], t->mr[1]);
766 return true;
767 }
768
769 static bool
770 nouveau_mem_gddr5_mr(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
771 struct nouveau_pm_tbl_entry *e,
772 struct nouveau_pm_memtiming *t,
773 struct nouveau_pm_memtiming *boot)
774 {
775 if (hdr->entry_len < 15) {
776 t->drive_strength = boot->drive_strength;
777 t->odt = boot->odt;
778 } else {
779 t->drive_strength = (e->RAM_FT1 & 0x30) >> 4;
780 t->odt = e->RAM_FT1 & 0x03;
781 }
782
783 if (e->tCL >= NV_MEM_CL_GDDR5_MAX) {
784 NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL);
785 return false;
786 }
787
788 if (e->tWR >= NV_MEM_WR_GDDR5_MAX) {
789 NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR);
790 return false;
791 }
792
793 if (t->odt > 3) {
794 NV_WARN(dev, "(%u) Invalid odt value, assuming autocal: %x",
795 t->id, t->odt);
796 t->odt = 0;
797 }
798
799 t->mr[0] = (boot->mr[0] & 0x007) |
800 ((e->tCL - 5) << 3) |
801 ((e->tWR - 4) << 8);
802 t->mr[1] = (boot->mr[1] & 0x1007f0) |
803 t->drive_strength |
804 (t->odt << 2);
805
806 NV_DEBUG(dev, "(%u) MR: %08x %08x", t->id, t->mr[0], t->mr[1]);
807 return true;
808 }
809
810 static void
811 nouveau_mem_copy_current_timings(struct drm_device *dev,
812 struct nouveau_pm_memtiming *t)
813 {
814 struct drm_nouveau_private *dev_priv = dev->dev_private;
815 u32 timing_base, timing_regs, mr_base;
816 int i;
817
818 if (dev_priv->card_type >= 0xC0) {
819 timing_base = 0x10f290;
820 mr_base = 0x10f300;
821 } else {
822 timing_base = 0x100220;
823 mr_base = 0x1002c0;
824 }
825
826 t->id = -1;
827
828 switch (dev_priv->card_type) {
829 case NV_50:
830 timing_regs = 9;
831 break;
832 case NV_C0:
833 case NV_D0:
834 timing_regs = 5;
835 break;
836 case NV_30:
837 case NV_40:
838 timing_regs = 3;
839 break;
840 default:
841 timing_regs = 0;
842 return;
843 }
844 for(i = 0; i < timing_regs; i++)
845 t->reg[i] = nv_rd32(dev, timing_base + (0x04 * i));
846
847 t->tCWL = 0;
848 if (dev_priv->card_type < NV_C0) {
849 t->tCWL = ((nv_rd32(dev, 0x100228) & 0x0f000000) >> 24) + 1;
850 }
851
852 t->mr[0] = nv_rd32(dev, mr_base);
853 t->mr[1] = nv_rd32(dev, mr_base + 0x04);
854 t->mr[2] = nv_rd32(dev, mr_base + 0x20);
855 t->mr[3] = nv_rd32(dev, mr_base + 0x24);
856
857 t->odt = 0;
858 t->drive_strength = 0;
859
860 switch (dev_priv->vram_type) {
861 case NV_MEM_TYPE_DDR3:
862 t->odt |= (t->mr[1] & 0x200) >> 7;
863 case NV_MEM_TYPE_DDR2:
864 t->odt |= (t->mr[1] & 0x04) >> 2 |
865 (t->mr[1] & 0x40) >> 5;
866 break;
867 case NV_MEM_TYPE_GDDR3:
868 case NV_MEM_TYPE_GDDR5:
869 t->drive_strength = t->mr[1] & 0x03;
870 t->odt = (t->mr[1] & 0x0c) >> 2;
871 break;
872 default:
873 break;
874 }
875 }
876
877 static bool
878 nouveau_mem_compare_timings(struct drm_device *dev,
879 struct nouveau_pm_memtiming *t1,
880 struct nouveau_pm_memtiming *t2)
881 {
882 struct drm_nouveau_private *dev_priv = dev->dev_private;
883
884 switch (dev_priv->card_type) {
885 case 0x50:
886 if (t1->reg[8] != t2->reg[8] ||
887 t1->reg[7] != t2->reg[7] ||
888 t1->reg[6] != t2->reg[6] ||
889 t1->reg[5] != t2->reg[5])
890 return false;
891 case 0xC0:
892 if (t1->reg[4] != t2->reg[4] ||
893 t1->reg[3] != t2->reg[3])
894 return false;
895 case 0x40:
896 if (t1->reg[2] != t2->reg[2] ||
897 t1->reg[1] != t2->reg[1] ||
898 t1->reg[0] != t2->reg[0])
899 return false;
900 break;
901 default:
902 return false;
903 }
904
905 /* RSpliet: may generate many false negatives */
906 switch (dev_priv->vram_type) {
907 case NV_MEM_TYPE_GDDR3:
908 case NV_MEM_TYPE_GDDR5:
909 if (t1->mr[0] == t2->mr[0] ||
910 t1->mr[1] != t2->mr[1])
911 return true;
912 break;
913 case NV_MEM_TYPE_DDR3:
914 if (t1->mr[2] == t2->mr[2])
915 return true;
916 case NV_MEM_TYPE_DDR2:
917 if (t1->mr[0] == t2->mr[0])
918 return true;
919 break;
920 default:
921 return false;
922 }
923
924 return false;
925 }
926
927 /**
928 * Processes the Memory Timing BIOS table, stores generated
929 * register values
930 * @pre init scripts were run, memtiming regs are initialized
931 */
932 void
933 nouveau_mem_timing_init(struct drm_device *dev)
934 {
935 struct drm_nouveau_private *dev_priv = dev->dev_private;
936 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
937 struct nouveau_pm_memtimings *memtimings = &pm->memtimings;
938 struct nvbios *bios = &dev_priv->vbios;
939 struct bit_entry P;
940 struct nouveau_pm_tbl_header *hdr = NULL;
941 bool valid_generation = false;
942 u8 *entry;
943 int i;
944
945 memtimings->nr_timing = 0;
946 memtimings->nr_timing_valid = 0;
947 memtimings->supported = 0;
948
949 if (dev_priv->card_type < NV_40) {
950 NV_ERROR(dev, "Timing entry format unknown for card_type %x. "
951 "please contact nouveau developers",
952 dev_priv->card_type);
953 return;
954 }
955
956 /* Copy the current timings */
957 nouveau_mem_copy_current_timings(dev, &memtimings->boot);
958
959 if (bios->type == NVBIOS_BIT) {
960 if (bit_table(dev, 'P', &P))
961 return;
962
963 if (P.version == 1)
964 hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev,
965 P.data[4]);
966 else if (P.version == 2)
967 hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev,
968 P.data[8]);
969 else
970 NV_WARN(dev, "unknown mem for BIT P %d\n", P.version);
971 } else {
972 NV_DEBUG(dev, "BMP version too old for memory\n");
973 return;
974 }
975
976 if (!hdr) {
977 NV_DEBUG(dev, "memory timing table pointer invalid\n");
978 return;
979 }
980
981 if (hdr->version != 0x10) {
982 NV_WARN(dev, "memory timing table 0x%02x unknown\n",
983 hdr->version);
984 return;
985 }
986
987 /* validate record length */
988 if (hdr->entry_len < 15) {
989 NV_ERROR(dev, "mem timing table length unknown: %d\n",
990 hdr->entry_len);
991 return;
992 }
993
994 /* parse vbios entries into common format */
995 memtimings->timing = kcalloc(hdr->entry_cnt,
996 sizeof(*memtimings->timing), GFP_KERNEL);
997 if (!memtimings->timing)
998 return;
999
1000 entry = (u8 *) hdr + hdr->header_len;
1001 for (i = 0; i < hdr->entry_cnt; i++, entry += hdr->entry_len) {
1002 struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i];
1003 struct nouveau_pm_tbl_entry *entry_struct =
1004 (struct nouveau_pm_tbl_entry *) entry;
1005 if (entry[0] == 0)
1006 continue;
1007 memtimings->nr_timing_valid++;
1008
1009 timing->id = i;
1010 timing->tCWL = memtimings->boot.tCWL;
1011
1012 /* generate the timngs */
1013 if (dev_priv->card_type == NV_40) {
1014 nv40_mem_timing_entry(dev, hdr, entry_struct,
1015 &pm->memtimings.timing[i],
1016 &memtimings->boot);
1017 } else if (dev_priv->card_type == NV_50) {
1018 nv50_mem_timing_entry(dev, &P, hdr, entry_struct,
1019 &pm->memtimings.timing[i],
1020 &memtimings->boot);
1021 } else if (dev_priv->card_type == NV_C0) {
1022 nvc0_mem_timing_entry(dev, hdr, entry_struct,
1023 &pm->memtimings.timing[i],
1024 &memtimings->boot);
1025 }
1026
1027 /* generate the MR/EMR/... */
1028 switch (dev_priv->vram_type) {
1029 case NV_MEM_TYPE_GDDR3:
1030 nouveau_mem_gddr3_mr(dev, hdr, entry_struct, timing,
1031 &memtimings->boot);
1032 break;
1033 case NV_MEM_TYPE_GDDR5:
1034 nouveau_mem_gddr5_mr(dev, hdr, entry_struct, timing,
1035 &memtimings->boot);
1036 break;
1037 case NV_MEM_TYPE_DDR2:
1038 nouveau_mem_ddr2_mr(dev, hdr, entry_struct, timing,
1039 &memtimings->boot);
1040 break;
1041 case NV_MEM_TYPE_DDR3:
1042 nouveau_mem_ddr3_mr(dev, hdr, entry_struct, timing,
1043 &memtimings->boot);
1044 break;
1045 default:
1046 valid_generation = false;
1047 break;
1048 }
1049
1050 /* some kind of validation */
1051 if (nouveau_mem_compare_timings(dev, timing,
1052 &memtimings->boot)) {
1053 NV_DEBUG(dev, "Copy boot timings from entry %d\n",
1054 timing->id);
1055 memtimings->boot = *timing;
1056 valid_generation = true;
1057 }
1058 }
1059
1060 memtimings->nr_timing = hdr->entry_cnt;
1061 memtimings->supported = (P.version == 1) && valid_generation;
1062
1063 /* if there are no timing entries that cannot
1064 * re-generate the current timings
1065 */
1066 if (memtimings->nr_timing_valid > 0 && !valid_generation) {
1067 NV_INFO(dev,
1068 "Memory timings management may not be working."
1069 " please report to nouveau devs\n");
1070 }
1071 }
1072
1073 void
1074 nouveau_mem_timing_fini(struct drm_device *dev)
1075 {
1076 struct drm_nouveau_private *dev_priv = dev->dev_private;
1077 struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings;
1078
1079 kfree(mem->timing);
1080 mem->timing = NULL;
1081 }
1082
1083 int
1084 nouveau_mem_vbios_type(struct drm_device *dev)
1085 {
1086 struct bit_entry M;
1087 u8 ramcfg = (nv_rd32(dev, 0x101000) & 0x0000003c) >> 2;
1088 if (!bit_table(dev, 'M', &M) || M.version != 2 || M.length < 5) {
1089 u8 *table = ROMPTR(dev, M.data[3]);
1090 if (table && table[0] == 0x10 && ramcfg < table[3]) {
1091 u8 *entry = table + table[1] + (ramcfg * table[2]);
1092 switch (entry[0] & 0x0f) {
1093 case 0: return NV_MEM_TYPE_DDR2;
1094 case 1: return NV_MEM_TYPE_DDR3;
1095 case 2: return NV_MEM_TYPE_GDDR3;
1096 case 3: return NV_MEM_TYPE_GDDR5;
1097 default:
1098 break;
1099 }
1100
1101 }
1102 }
1103 return NV_MEM_TYPE_UNKNOWN;
1104 }
1105
1106 static int
1107 nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
1108 {
1109 /* nothing to do */
1110 return 0;
1111 }
1112
1113 static int
1114 nouveau_vram_manager_fini(struct ttm_mem_type_manager *man)
1115 {
1116 /* nothing to do */
1117 return 0;
1118 }
1119
1120 static inline void
1121 nouveau_mem_node_cleanup(struct nouveau_mem *node)
1122 {
1123 if (node->vma[0].node) {
1124 nouveau_vm_unmap(&node->vma[0]);
1125 nouveau_vm_put(&node->vma[0]);
1126 }
1127
1128 if (node->vma[1].node) {
1129 nouveau_vm_unmap(&node->vma[1]);
1130 nouveau_vm_put(&node->vma[1]);
1131 }
1132 }
1133
1134 static void
1135 nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
1136 struct ttm_mem_reg *mem)
1137 {
1138 struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
1139 struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
1140 struct drm_device *dev = dev_priv->dev;
1141
1142 nouveau_mem_node_cleanup(mem->mm_node);
1143 vram->put(dev, (struct nouveau_mem **)&mem->mm_node);
1144 }
1145
1146 static int
1147 nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
1148 struct ttm_buffer_object *bo,
1149 struct ttm_placement *placement,
1150 struct ttm_mem_reg *mem)
1151 {
1152 struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
1153 struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
1154 struct drm_device *dev = dev_priv->dev;
1155 struct nouveau_bo *nvbo = nouveau_bo(bo);
1156 struct nouveau_mem *node;
1157 u32 size_nc = 0;
1158 int ret;
1159
1160 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)
1161 size_nc = 1 << nvbo->page_shift;
1162
1163 ret = vram->get(dev, mem->num_pages << PAGE_SHIFT,
1164 mem->page_alignment << PAGE_SHIFT, size_nc,
1165 (nvbo->tile_flags >> 8) & 0x3ff, &node);
1166 if (ret) {
1167 mem->mm_node = NULL;
1168 return (ret == -ENOSPC) ? 0 : ret;
1169 }
1170
1171 node->page_shift = nvbo->page_shift;
1172
1173 mem->mm_node = node;
1174 mem->start = node->offset >> PAGE_SHIFT;
1175 return 0;
1176 }
1177
1178 void
1179 nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
1180 {
1181 struct nouveau_mm *mm = man->priv;
1182 struct nouveau_mm_node *r;
1183 u32 total = 0, free = 0;
1184
1185 mutex_lock(&mm->mutex);
1186 list_for_each_entry(r, &mm->nodes, nl_entry) {
1187 printk(KERN_DEBUG "%s %d: 0x%010llx 0x%010llx\n",
1188 prefix, r->type, ((u64)r->offset << 12),
1189 (((u64)r->offset + r->length) << 12));
1190
1191 total += r->length;
1192 if (!r->type)
1193 free += r->length;
1194 }
1195 mutex_unlock(&mm->mutex);
1196
1197 printk(KERN_DEBUG "%s total: 0x%010llx free: 0x%010llx\n",
1198 prefix, (u64)total << 12, (u64)free << 12);
1199 printk(KERN_DEBUG "%s block: 0x%08x\n",
1200 prefix, mm->block_size << 12);
1201 }
1202
1203 const struct ttm_mem_type_manager_func nouveau_vram_manager = {
1204 nouveau_vram_manager_init,
1205 nouveau_vram_manager_fini,
1206 nouveau_vram_manager_new,
1207 nouveau_vram_manager_del,
1208 nouveau_vram_manager_debug
1209 };
1210
1211 static int
1212 nouveau_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
1213 {
1214 return 0;
1215 }
1216
1217 static int
1218 nouveau_gart_manager_fini(struct ttm_mem_type_manager *man)
1219 {
1220 return 0;
1221 }
1222
1223 static void
1224 nouveau_gart_manager_del(struct ttm_mem_type_manager *man,
1225 struct ttm_mem_reg *mem)
1226 {
1227 nouveau_mem_node_cleanup(mem->mm_node);
1228 kfree(mem->mm_node);
1229 mem->mm_node = NULL;
1230 }
1231
1232 static int
1233 nouveau_gart_manager_new(struct ttm_mem_type_manager *man,
1234 struct ttm_buffer_object *bo,
1235 struct ttm_placement *placement,
1236 struct ttm_mem_reg *mem)
1237 {
1238 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
1239 struct nouveau_mem *node;
1240
1241 if (unlikely((mem->num_pages << PAGE_SHIFT) >=
1242 dev_priv->gart_info.aper_size))
1243 return -ENOMEM;
1244
1245 node = kzalloc(sizeof(*node), GFP_KERNEL);
1246 if (!node)
1247 return -ENOMEM;
1248 node->page_shift = 12;
1249
1250 mem->mm_node = node;
1251 mem->start = 0;
1252 return 0;
1253 }
1254
1255 void
1256 nouveau_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
1257 {
1258 }
1259
1260 const struct ttm_mem_type_manager_func nouveau_gart_manager = {
1261 nouveau_gart_manager_init,
1262 nouveau_gart_manager_fini,
1263 nouveau_gart_manager_new,
1264 nouveau_gart_manager_del,
1265 nouveau_gart_manager_debug
1266 };
Linux kernel - Deliverables
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