2 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3 * Copyright 2005 Stephane Marchesin
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
29 * Ben Skeggs <bskeggs@redhat.com>
30 * Roy Spliet <r.spliet@student.tudelft.nl>
36 #include "drm_sarea.h"
38 #include "nouveau_drv.h"
39 #include "nouveau_pm.h"
42 nv40_mem_timing_calc(struct drm_device
*dev
, u32 freq
,
43 struct nouveau_pm_tbl_entry
*e
, u8 len
,
44 struct nouveau_pm_memtiming
*boot
,
45 struct nouveau_pm_memtiming
*t
)
47 t
->reg
[0] = (e
->tRP
<< 24 | e
->tRAS
<< 16 | e
->tRFC
<< 8 | e
->tRC
);
49 /* XXX: I don't trust the -1's and +1's... they must come
51 t
->reg
[1] = (e
->tWR
+ 2 + (t
->tCWL
- 1)) << 24 |
53 (e
->tWTR
+ 2 + (t
->tCWL
- 1)) << 8 |
54 (e
->tCL
+ 2 - (t
->tCWL
- 1));
56 t
->reg
[2] = 0x20200000 |
57 ((t
->tCWL
- 1) << 24 |
62 NV_DEBUG(dev
, "Entry %d: 220: %08x %08x %08x\n", t
->id
,
63 t
->reg
[0], t
->reg
[1], t
->reg
[2]);
68 nv50_mem_timing_calc(struct drm_device
*dev
, u32 freq
,
69 struct nouveau_pm_tbl_entry
*e
, u8 len
,
70 struct nouveau_pm_memtiming
*boot
,
71 struct nouveau_pm_memtiming
*t
)
74 uint8_t unk18
= 1, unk20
= 0, unk21
= 0, tmp7_3
;
76 if (bit_table(dev
, 'P', &P
))
79 switch (min(len
, (u8
) 22)) {
92 t
->reg
[0] = (e
->tRP
<< 24 | e
->tRAS
<< 16 | e
->tRFC
<< 8 | e
->tRC
);
94 t
->reg
[1] = (e
->tWR
+ 2 + (t
->tCWL
- 1)) << 24 |
95 max(unk18
, (u8
) 1) << 16 |
96 (e
->tWTR
+ 2 + (t
->tCWL
- 1)) << 8;
98 t
->reg
[2] = ((t
->tCWL
- 1) << 24 |
103 t
->reg
[4] = e
->tUNK_13
<< 8 | e
->tUNK_13
;
105 t
->reg
[5] = (e
->tRFC
<< 24 | max(e
->tRCDRD
, e
->tRCDWR
) << 16 | e
->tRP
);
107 t
->reg
[8] = boot
->reg
[8] & 0xffffff00;
109 if (P
.version
== 1) {
110 t
->reg
[1] |= (e
->tCL
+ 2 - (t
->tCWL
- 1));
112 t
->reg
[3] = (0x14 + e
->tCL
) << 24 |
117 t
->reg
[4] |= boot
->reg
[4] & 0xffff0000;
119 t
->reg
[6] = (0x33 - t
->tCWL
) << 16 |
121 (0x2e + e
->tCL
- t
->tCWL
);
123 t
->reg
[7] = 0x4000202 | (e
->tCL
- 1) << 16;
125 /* XXX: P.version == 1 only has DDR2 and GDDR3? */
126 if (nvfb_vram_type(dev
) == NV_MEM_TYPE_DDR2
) {
127 t
->reg
[5] |= (e
->tCL
+ 3) << 8;
128 t
->reg
[6] |= (t
->tCWL
- 2) << 8;
129 t
->reg
[8] |= (e
->tCL
- 4);
131 t
->reg
[5] |= (e
->tCL
+ 2) << 8;
132 t
->reg
[6] |= t
->tCWL
<< 8;
133 t
->reg
[8] |= (e
->tCL
- 2);
136 t
->reg
[1] |= (5 + e
->tCL
- (t
->tCWL
));
138 /* XXX: 0xb? 0x30? */
139 t
->reg
[3] = (0x30 + e
->tCL
) << 24 |
140 (boot
->reg
[3] & 0x00ff0000)|
141 (0xb + e
->tCL
) << 8 |
144 t
->reg
[4] |= (unk20
<< 24 | unk21
<< 16);
147 t
->reg
[5] |= (t
->tCWL
+ 6) << 8;
149 t
->reg
[6] = (0x5a + e
->tCL
) << 16 |
150 (6 - e
->tCL
+ t
->tCWL
) << 8 |
151 (0x50 + e
->tCL
- t
->tCWL
);
153 tmp7_3
= (boot
->reg
[7] & 0xff000000) >> 24;
154 t
->reg
[7] = (tmp7_3
<< 24) |
155 ((tmp7_3
- 6 + e
->tCL
) << 16) |
159 NV_DEBUG(dev
, "Entry %d: 220: %08x %08x %08x %08x\n", t
->id
,
160 t
->reg
[0], t
->reg
[1], t
->reg
[2], t
->reg
[3]);
161 NV_DEBUG(dev
, " 230: %08x %08x %08x %08x\n",
162 t
->reg
[4], t
->reg
[5], t
->reg
[6], t
->reg
[7]);
163 NV_DEBUG(dev
, " 240: %08x\n", t
->reg
[8]);
168 nvc0_mem_timing_calc(struct drm_device
*dev
, u32 freq
,
169 struct nouveau_pm_tbl_entry
*e
, u8 len
,
170 struct nouveau_pm_memtiming
*boot
,
171 struct nouveau_pm_memtiming
*t
)
176 t
->reg
[0] = (e
->tRP
<< 24 | (e
->tRAS
& 0x7f) << 17 |
177 e
->tRFC
<< 8 | e
->tRC
);
179 t
->reg
[1] = (boot
->reg
[1] & 0xff000000) |
180 (e
->tRCDWR
& 0x0f) << 20 |
181 (e
->tRCDRD
& 0x0f) << 14 |
185 t
->reg
[2] = (boot
->reg
[2] & 0xff0000ff) |
186 e
->tWR
<< 16 | e
->tWTR
<< 8;
188 t
->reg
[3] = (e
->tUNK_20
& 0x1f) << 9 |
189 (e
->tUNK_21
& 0xf) << 5 |
192 t
->reg
[4] = (boot
->reg
[4] & 0xfff00fff) |
193 (e
->tRRD
&0x1f) << 15;
195 NV_DEBUG(dev
, "Entry %d: 290: %08x %08x %08x %08x\n", t
->id
,
196 t
->reg
[0], t
->reg
[1], t
->reg
[2], t
->reg
[3]);
197 NV_DEBUG(dev
, " 2a0: %08x\n", t
->reg
[4]);
202 * MR generation methods
206 nouveau_mem_ddr2_mr(struct drm_device
*dev
, u32 freq
,
207 struct nouveau_pm_tbl_entry
*e
, u8 len
,
208 struct nouveau_pm_memtiming
*boot
,
209 struct nouveau_pm_memtiming
*t
)
211 t
->drive_strength
= 0;
215 t
->odt
= e
->RAM_FT1
& 0x07;
218 if (e
->tCL
>= NV_MEM_CL_DDR2_MAX
) {
219 NV_WARN(dev
, "(%u) Invalid tCL: %u", t
->id
, e
->tCL
);
223 if (e
->tWR
>= NV_MEM_WR_DDR2_MAX
) {
224 NV_WARN(dev
, "(%u) Invalid tWR: %u", t
->id
, e
->tWR
);
229 NV_WARN(dev
, "(%u) Invalid odt value, assuming disabled: %x",
234 t
->mr
[0] = (boot
->mr
[0] & 0x100f) |
237 t
->mr
[1] = (boot
->mr
[1] & 0x101fbb) |
238 (t
->odt
& 0x1) << 2 |
241 NV_DEBUG(dev
, "(%u) MR: %08x", t
->id
, t
->mr
[0]);
245 uint8_t nv_mem_wr_lut_ddr3
[NV_MEM_WR_DDR3_MAX
] = {
246 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
249 nouveau_mem_ddr3_mr(struct drm_device
*dev
, u32 freq
,
250 struct nouveau_pm_tbl_entry
*e
, u8 len
,
251 struct nouveau_pm_memtiming
*boot
,
252 struct nouveau_pm_memtiming
*t
)
256 t
->drive_strength
= 0;
260 t
->odt
= e
->RAM_FT1
& 0x07;
263 if (e
->tCL
>= NV_MEM_CL_DDR3_MAX
|| e
->tCL
< 4) {
264 NV_WARN(dev
, "(%u) Invalid tCL: %u", t
->id
, e
->tCL
);
268 if (e
->tWR
>= NV_MEM_WR_DDR3_MAX
|| e
->tWR
< 4) {
269 NV_WARN(dev
, "(%u) Invalid tWR: %u", t
->id
, e
->tWR
);
274 NV_WARN(dev
, "(%u) Invalid tCWL: %u", t
->id
, e
->tCWL
);
278 t
->mr
[0] = (boot
->mr
[0] & 0x180b) |
282 (nv_mem_wr_lut_ddr3
[e
->tWR
]) << 9;
283 t
->mr
[1] = (boot
->mr
[1] & 0x101dbb) |
284 (t
->odt
& 0x1) << 2 |
285 (t
->odt
& 0x2) << 5 |
287 t
->mr
[2] = (boot
->mr
[2] & 0x20ffb7) | (e
->tCWL
- 5) << 3;
289 NV_DEBUG(dev
, "(%u) MR: %08x %08x", t
->id
, t
->mr
[0], t
->mr
[2]);
293 uint8_t nv_mem_cl_lut_gddr3
[NV_MEM_CL_GDDR3_MAX
] = {
294 0, 0, 0, 0, 4, 5, 6, 7, 0, 1, 2, 3, 8, 9, 10, 11};
295 uint8_t nv_mem_wr_lut_gddr3
[NV_MEM_WR_GDDR3_MAX
] = {
296 0, 0, 0, 0, 0, 2, 3, 8, 9, 10, 11, 0, 0, 1, 1, 0, 3};
299 nouveau_mem_gddr3_mr(struct drm_device
*dev
, u32 freq
,
300 struct nouveau_pm_tbl_entry
*e
, u8 len
,
301 struct nouveau_pm_memtiming
*boot
,
302 struct nouveau_pm_memtiming
*t
)
305 t
->drive_strength
= boot
->drive_strength
;
308 t
->drive_strength
= (e
->RAM_FT1
& 0x30) >> 4;
309 t
->odt
= e
->RAM_FT1
& 0x07;
312 if (e
->tCL
>= NV_MEM_CL_GDDR3_MAX
) {
313 NV_WARN(dev
, "(%u) Invalid tCL: %u", t
->id
, e
->tCL
);
317 if (e
->tWR
>= NV_MEM_WR_GDDR3_MAX
) {
318 NV_WARN(dev
, "(%u) Invalid tWR: %u", t
->id
, e
->tWR
);
323 NV_WARN(dev
, "(%u) Invalid odt value, assuming autocal: %x",
328 t
->mr
[0] = (boot
->mr
[0] & 0xe0b) |
330 ((nv_mem_cl_lut_gddr3
[e
->tCL
] & 0x7) << 4) |
331 ((nv_mem_cl_lut_gddr3
[e
->tCL
] & 0x8) >> 2);
332 t
->mr
[1] = (boot
->mr
[1] & 0x100f40) | t
->drive_strength
|
334 (nv_mem_wr_lut_gddr3
[e
->tWR
] & 0xf) << 4;
335 t
->mr
[2] = boot
->mr
[2];
337 NV_DEBUG(dev
, "(%u) MR: %08x %08x %08x", t
->id
,
338 t
->mr
[0], t
->mr
[1], t
->mr
[2]);
343 nouveau_mem_gddr5_mr(struct drm_device
*dev
, u32 freq
,
344 struct nouveau_pm_tbl_entry
*e
, u8 len
,
345 struct nouveau_pm_memtiming
*boot
,
346 struct nouveau_pm_memtiming
*t
)
349 t
->drive_strength
= boot
->drive_strength
;
352 t
->drive_strength
= (e
->RAM_FT1
& 0x30) >> 4;
353 t
->odt
= e
->RAM_FT1
& 0x03;
356 if (e
->tCL
>= NV_MEM_CL_GDDR5_MAX
) {
357 NV_WARN(dev
, "(%u) Invalid tCL: %u", t
->id
, e
->tCL
);
361 if (e
->tWR
>= NV_MEM_WR_GDDR5_MAX
) {
362 NV_WARN(dev
, "(%u) Invalid tWR: %u", t
->id
, e
->tWR
);
367 NV_WARN(dev
, "(%u) Invalid odt value, assuming autocal: %x",
372 t
->mr
[0] = (boot
->mr
[0] & 0x007) |
373 ((e
->tCL
- 5) << 3) |
375 t
->mr
[1] = (boot
->mr
[1] & 0x1007f0) |
379 NV_DEBUG(dev
, "(%u) MR: %08x %08x", t
->id
, t
->mr
[0], t
->mr
[1]);
384 nouveau_mem_timing_calc(struct drm_device
*dev
, u32 freq
,
385 struct nouveau_pm_memtiming
*t
)
387 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
388 struct nouveau_pm_engine
*pm
= &dev_priv
->engine
.pm
;
389 struct nouveau_pm_memtiming
*boot
= &pm
->boot
.timing
;
390 struct nouveau_pm_tbl_entry
*e
;
391 u8 ver
, len
, *ptr
, *ramcfg
;
394 ptr
= nouveau_perf_timing(dev
, freq
, &ver
, &len
);
395 if (!ptr
|| ptr
[0] == 0x00) {
399 e
= (struct nouveau_pm_tbl_entry
*)ptr
;
401 t
->tCWL
= boot
->tCWL
;
403 switch (dev_priv
->card_type
) {
405 ret
= nv40_mem_timing_calc(dev
, freq
, e
, len
, boot
, t
);
408 ret
= nv50_mem_timing_calc(dev
, freq
, e
, len
, boot
, t
);
412 ret
= nvc0_mem_timing_calc(dev
, freq
, e
, len
, boot
, t
);
419 switch (nvfb_vram_type(dev
) * !ret
) {
420 case NV_MEM_TYPE_GDDR3
:
421 ret
= nouveau_mem_gddr3_mr(dev
, freq
, e
, len
, boot
, t
);
423 case NV_MEM_TYPE_GDDR5
:
424 ret
= nouveau_mem_gddr5_mr(dev
, freq
, e
, len
, boot
, t
);
426 case NV_MEM_TYPE_DDR2
:
427 ret
= nouveau_mem_ddr2_mr(dev
, freq
, e
, len
, boot
, t
);
429 case NV_MEM_TYPE_DDR3
:
430 ret
= nouveau_mem_ddr3_mr(dev
, freq
, e
, len
, boot
, t
);
437 ramcfg
= nouveau_perf_ramcfg(dev
, freq
, &ver
, &len
);
442 dll_off
= !!(ramcfg
[3] & 0x04);
444 dll_off
= !!(ramcfg
[2] & 0x40);
446 switch (nvfb_vram_type(dev
)) {
447 case NV_MEM_TYPE_GDDR3
:
448 t
->mr
[1] &= ~0x00000040;
449 t
->mr
[1] |= 0x00000040 * dll_off
;
452 t
->mr
[1] &= ~0x00000001;
453 t
->mr
[1] |= 0x00000001 * dll_off
;
462 nouveau_mem_timing_read(struct drm_device
*dev
, struct nouveau_pm_memtiming
*t
)
464 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
465 u32 timing_base
, timing_regs
, mr_base
;
468 if (dev_priv
->card_type
>= 0xC0) {
469 timing_base
= 0x10f290;
472 timing_base
= 0x100220;
478 switch (dev_priv
->card_type
) {
494 for(i
= 0; i
< timing_regs
; i
++)
495 t
->reg
[i
] = nv_rd32(dev
, timing_base
+ (0x04 * i
));
498 if (dev_priv
->card_type
< NV_C0
) {
499 t
->tCWL
= ((nv_rd32(dev
, 0x100228) & 0x0f000000) >> 24) + 1;
500 } else if (dev_priv
->card_type
<= NV_D0
) {
501 t
->tCWL
= ((nv_rd32(dev
, 0x10f294) & 0x00000f80) >> 7);
504 t
->mr
[0] = nv_rd32(dev
, mr_base
);
505 t
->mr
[1] = nv_rd32(dev
, mr_base
+ 0x04);
506 t
->mr
[2] = nv_rd32(dev
, mr_base
+ 0x20);
507 t
->mr
[3] = nv_rd32(dev
, mr_base
+ 0x24);
510 t
->drive_strength
= 0;
512 switch (nvfb_vram_type(dev
)) {
513 case NV_MEM_TYPE_DDR3
:
514 t
->odt
|= (t
->mr
[1] & 0x200) >> 7;
515 case NV_MEM_TYPE_DDR2
:
516 t
->odt
|= (t
->mr
[1] & 0x04) >> 2 |
517 (t
->mr
[1] & 0x40) >> 5;
519 case NV_MEM_TYPE_GDDR3
:
520 case NV_MEM_TYPE_GDDR5
:
521 t
->drive_strength
= t
->mr
[1] & 0x03;
522 t
->odt
= (t
->mr
[1] & 0x0c) >> 2;
530 nouveau_mem_exec(struct nouveau_mem_exec_func
*exec
,
531 struct nouveau_pm_level
*perflvl
)
533 struct drm_nouveau_private
*dev_priv
= exec
->dev
->dev_private
;
534 struct nouveau_pm_memtiming
*info
= &perflvl
->timing
;
535 u32 tMRD
= 1000, tCKSRE
= 0, tCKSRX
= 0, tXS
= 0, tDLLK
= 0;
536 u32 mr
[3] = { info
->mr
[0], info
->mr
[1], info
->mr
[2] };
539 switch (nvfb_vram_type(dev_priv
->dev
)) {
540 case NV_MEM_TYPE_DDR2
:
542 mr1_dlloff
= 0x00000001;
544 case NV_MEM_TYPE_DDR3
:
548 mr1_dlloff
= 0x00000001;
550 case NV_MEM_TYPE_GDDR3
:
552 mr1_dlloff
= 0x00000040;
555 NV_ERROR(exec
->dev
, "cannot reclock unsupported memtype\n");
559 /* fetch current MRs */
560 switch (nvfb_vram_type(dev_priv
->dev
)) {
561 case NV_MEM_TYPE_GDDR3
:
562 case NV_MEM_TYPE_DDR3
:
563 mr
[2] = exec
->mrg(exec
, 2);
565 mr
[1] = exec
->mrg(exec
, 1);
566 mr
[0] = exec
->mrg(exec
, 0);
570 /* DLL 'on' -> DLL 'off' mode, disable before entering self-refresh */
571 if (!(mr
[1] & mr1_dlloff
) && (info
->mr
[1] & mr1_dlloff
)) {
572 exec
->precharge(exec
);
573 exec
->mrs (exec
, 1, mr
[1] | mr1_dlloff
);
574 exec
->wait(exec
, tMRD
);
577 /* enter self-refresh mode */
578 exec
->precharge(exec
);
581 exec
->refresh_auto(exec
, false);
582 exec
->refresh_self(exec
, true);
583 exec
->wait(exec
, tCKSRE
);
585 /* modify input clock frequency */
586 exec
->clock_set(exec
);
588 /* exit self-refresh mode */
589 exec
->wait(exec
, tCKSRX
);
590 exec
->precharge(exec
);
591 exec
->refresh_self(exec
, false);
592 exec
->refresh_auto(exec
, true);
593 exec
->wait(exec
, tXS
);
594 exec
->wait(exec
, tXS
);
597 if (mr
[2] != info
->mr
[2]) {
598 exec
->mrs (exec
, 2, info
->mr
[2]);
599 exec
->wait(exec
, tMRD
);
602 if (mr
[1] != info
->mr
[1]) {
603 /* need to keep DLL off until later, at least on GDDR3 */
604 exec
->mrs (exec
, 1, info
->mr
[1] | (mr
[1] & mr1_dlloff
));
605 exec
->wait(exec
, tMRD
);
608 if (mr
[0] != info
->mr
[0]) {
609 exec
->mrs (exec
, 0, info
->mr
[0]);
610 exec
->wait(exec
, tMRD
);
613 /* update PFB timing registers */
614 exec
->timing_set(exec
);
616 /* DLL (enable + ) reset */
617 if (!(info
->mr
[1] & mr1_dlloff
)) {
618 if (mr
[1] & mr1_dlloff
) {
619 exec
->mrs (exec
, 1, info
->mr
[1]);
620 exec
->wait(exec
, tMRD
);
622 exec
->mrs (exec
, 0, info
->mr
[0] | 0x00000100);
623 exec
->wait(exec
, tMRD
);
624 exec
->mrs (exec
, 0, info
->mr
[0] | 0x00000000);
625 exec
->wait(exec
, tMRD
);
626 exec
->wait(exec
, tDLLK
);
627 if (nvfb_vram_type(dev_priv
->dev
) == NV_MEM_TYPE_GDDR3
)
628 exec
->precharge(exec
);
635 nouveau_mem_vbios_type(struct drm_device
*dev
)
638 u8 ramcfg
= (nv_rd32(dev
, 0x101000) & 0x0000003c) >> 2;
639 if (!bit_table(dev
, 'M', &M
) || M
.version
!= 2 || M
.length
< 5) {
640 u8
*table
= ROMPTR(dev
, M
.data
[3]);
641 if (table
&& table
[0] == 0x10 && ramcfg
< table
[3]) {
642 u8
*entry
= table
+ table
[1] + (ramcfg
* table
[2]);
643 switch (entry
[0] & 0x0f) {
644 case 0: return NV_MEM_TYPE_DDR2
;
645 case 1: return NV_MEM_TYPE_DDR3
;
646 case 2: return NV_MEM_TYPE_GDDR3
;
647 case 3: return NV_MEM_TYPE_GDDR5
;
654 return NV_MEM_TYPE_UNKNOWN
;
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