drivers/gpu/drm/nouveau/nouveau_perf.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "drmP.h"
  26
  27 #include "nouveau_drv.h"
  28 #include "nouveau_pm.h"
  29
  30 static void
  31 legacy_perf_init(struct drm_device *dev)
  32 {
  33         struct drm_nouveau_private *dev_priv = dev->dev_private;
  34         struct nvbios *bios = &dev_priv->vbios;
  35         struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
  36         char *perf, *entry, *bmp = &bios->data[bios->offset];
  37         int headerlen, use_straps;
  38
  39         if (bmp[5] < 0x5 || bmp[6] < 0x14) {
  40                 NV_DEBUG(dev, "BMP version too old for perf\n");
  41                 return;
  42         }
  43
  44         perf = ROMPTR(dev, bmp[0x73]);
  45         if (!perf) {
  46                 NV_DEBUG(dev, "No memclock table pointer found.\n");
  47                 return;
  48         }
  49
  50         switch (perf[0]) {
  51         case 0x12:
  52         case 0x14:
  53         case 0x18:
  54                 use_straps = 0;
  55                 headerlen = 1;
  56                 break;
  57         case 0x01:
  58                 use_straps = perf[1] & 1;
  59                 headerlen = (use_straps ? 8 : 2);
  60                 break;
  61         default:
  62                 NV_WARN(dev, "Unknown memclock table version %x.\n", perf[0]);
  63                 return;
  64         }
  65
  66         entry = perf + headerlen;
  67         if (use_straps)
  68                 entry += (nv_rd32(dev, NV_PEXTDEV_BOOT_0) & 0x3c) >> 1;
  69
  70         sprintf(pm->perflvl[0].name, "performance_level_0");
  71         pm->perflvl[0].memory = ROM16(entry[0]) * 20;
  72         pm->nr_perflvl = 1;
  73 }
  74
  75 static struct nouveau_pm_memtiming *
  76 nouveau_perf_timing(struct drm_device *dev, struct bit_entry *P,
  77                     u16 memclk, u8 *entry, u8 recordlen, u8 entries)
  78 {
  79         struct drm_nouveau_private *dev_priv = dev->dev_private;
  80         struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
  81         struct nvbios *bios = &dev_priv->vbios;
  82         u8 ramcfg;
  83         int i;
  84
  85         /* perf v2 has a separate "timing map" table, we have to match
  86          * the target memory clock to a specific entry, *then* use
  87          * ramcfg to select the correct subentry
  88          */
  89         if (P->version == 2) {
  90                 u8 *tmap = ROMPTR(dev, P->data[4]);
  91                 if (!tmap) {
  92                         NV_DEBUG(dev, "no timing map pointer\n");
  93                         return NULL;
  94                 }
  95
  96                 if (tmap[0] != 0x10) {
  97                         NV_WARN(dev, "timing map 0x%02x unknown\n", tmap[0]);
  98                         return NULL;
  99                 }
 100
 101                 entry = tmap + tmap[1];
 102                 recordlen = tmap[2] + (tmap[4] * tmap[3]);
 103                 for (i = 0; i < tmap[5]; i++, entry += recordlen) {
 104                         if (memclk >= ROM16(entry[0]) &&
 105                             memclk <= ROM16(entry[2]))
 106                                 break;
 107                 }
 108
 109                 if (i == tmap[5]) {
 110                         NV_WARN(dev, "no match in timing map table\n");
 111                         return NULL;
 112                 }
 113
 114                 entry += tmap[2];
 115                 recordlen = tmap[3];
 116                 entries   = tmap[4];
 117         }
 118
 119         ramcfg = (nv_rd32(dev, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
 120         if (bios->ram_restrict_tbl_ptr)
 121                 ramcfg = bios->data[bios->ram_restrict_tbl_ptr + ramcfg];
 122
 123         if (ramcfg >= entries) {
 124                 NV_WARN(dev, "ramcfg strap out of bounds!\n");
 125                 return NULL;
 126         }
 127
 128         entry += ramcfg * recordlen;
 129         if (entry[1] >= pm->memtimings.nr_timing) {
 130                 if (entry[1] != 0xff)
 131                         NV_WARN(dev, "timingset %d does not exist\n", entry[1]);
 132                 return NULL;
 133         }
 134
 135         return &pm->memtimings.timing[entry[1]];
 136 }
 137
 138 static void
 139 nouveau_perf_voltage(struct drm_device *dev, struct bit_entry *P,
 140                      struct nouveau_pm_level *perflvl)
 141 {
 142         struct drm_nouveau_private *dev_priv = dev->dev_private;
 143         u8 *vmap;
 144         int id;
 145
 146         id = perflvl->volt_min;
 147         perflvl->volt_min = 0;
 148
 149         /* boards using voltage table version <0x40 store the voltage
 150          * level directly in the perflvl entry as a multiple of 10mV
 151          */
 152         if (dev_priv->engine.pm.voltage.version < 0x40) {
 153                 perflvl->volt_min = id * 10000;
 154                 perflvl->volt_max = perflvl->volt_min;
 155                 return;
 156         }
 157
 158         /* on newer ones, the perflvl stores an index into yet another
 159          * vbios table containing a min/max voltage value for the perflvl
 160          */
 161         if (P->version != 2 || P->length < 34) {
 162                 NV_DEBUG(dev, "where's our volt map table ptr? %d %d\n",
 163                          P->version, P->length);
 164                 return;
 165         }
 166
 167         vmap = ROMPTR(dev, P->data[32]);
 168         if (!vmap) {
 169                 NV_DEBUG(dev, "volt map table pointer invalid\n");
 170                 return;
 171         }
 172
 173         if (id < vmap[3]) {
 174                 vmap += vmap[1] + (vmap[2] * id);
 175                 perflvl->volt_min = ROM32(vmap[0]);
 176                 perflvl->volt_max = ROM32(vmap[4]);
 177         }
 178 }
 179
 180 void
 181 nouveau_perf_init(struct drm_device *dev)
 182 {
 183         struct drm_nouveau_private *dev_priv = dev->dev_private;
 184         struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
 185         struct nvbios *bios = &dev_priv->vbios;
 186         struct bit_entry P;
 187         struct nouveau_pm_memtimings *memtimings = &pm->memtimings;
 188         struct nouveau_pm_tbl_header mt_hdr;
 189         u8 version, headerlen, recordlen, entries;
 190         u8 *perf, *entry;
 191         int vid, i;
 192
 193         if (bios->type == NVBIOS_BIT) {
 194                 if (bit_table(dev, 'P', &P))
 195                         return;
 196
 197                 if (P.version != 1 && P.version != 2) {
 198                         NV_WARN(dev, "unknown perf for BIT P %d\n", P.version);
 199                         return;
 200                 }
 201
 202                 perf = ROMPTR(dev, P.data[0]);
 203                 version   = perf[0];
 204                 headerlen = perf[1];
 205                 if (version < 0x40) {
 206                         recordlen = perf[3] + (perf[4] * perf[5]);
 207                         entries   = perf[2];
 208
 209                         pm->pwm_divisor = ROM16(perf[6]);
 210                 } else {
 211                         recordlen = perf[2] + (perf[3] * perf[4]);
 212                         entries   = perf[5];
 213                 }
 214         } else {
 215                 if (bios->data[bios->offset + 6] < 0x25) {
 216                         legacy_perf_init(dev);
 217                         return;
 218                 }
 219
 220                 perf = ROMPTR(dev, bios->data[bios->offset + 0x94]);
 221                 if (!perf) {
 222                         NV_DEBUG(dev, "perf table pointer invalid\n");
 223                         return;
 224                 }
 225
 226                 version   = perf[1];
 227                 headerlen = perf[0];
 228                 recordlen = perf[3];
 229                 entries   = perf[2];
 230         }
 231
 232         if (entries > NOUVEAU_PM_MAX_LEVEL) {
 233                 NV_DEBUG(dev,
 234                          "perf table has too many entries - buggy vbios?\n");
 235                 entries = NOUVEAU_PM_MAX_LEVEL;
 236         }
 237
 238         entry = perf + headerlen;
 239
 240         /* For version 0x15, initialize memtiming table */
 241         if (version == 0x15) {
 242                 memtimings->timing = kcalloc(entries,
 243                                              sizeof(*memtimings->timing),
 244                                              GFP_KERNEL);
 245                 if (!memtimings->timing) {
 246                         NV_WARN(dev, "Could not allocate memtiming table\n");
 247                         return;
 248                 }
 249
 250                 mt_hdr.entry_cnt = entries;
 251                 mt_hdr.entry_len = 14;
 252                 mt_hdr.version = version;
 253                 mt_hdr.header_len = 4;
 254         }
 255
 256         for (i = 0; i < entries; i++) {
 257                 struct nouveau_pm_level *perflvl = &pm->perflvl[pm->nr_perflvl];
 258
 259                 perflvl->timing = NULL;
 260
 261                 if (entry[0] == 0xff) {
 262                         entry += recordlen;
 263                         continue;
 264                 }
 265
 266                 switch (version) {
 267                 case 0x12:
 268                 case 0x13:
 269                 case 0x15:
 270                         perflvl->fanspeed = entry[55];
 271                         if (recordlen > 56)
 272                                 perflvl->volt_min = entry[56];
 273                         perflvl->core = ROM32(entry[1]) * 10;
 274                         perflvl->memory = ROM32(entry[5]) * 20;
 275                         break;
 276                 case 0x21:
 277                 case 0x23:
 278                 case 0x24:
 279                         perflvl->fanspeed = entry[4];
 280                         perflvl->volt_min = entry[5];
 281                         perflvl->shader = ROM16(entry[6]) * 1000;
 282                         perflvl->core = perflvl->shader;
 283                         perflvl->core += (signed char)entry[8] * 1000;
 284                         if (dev_priv->chipset == 0x49 ||
 285                             dev_priv->chipset == 0x4b)
 286                                 perflvl->memory = ROM16(entry[11]) * 1000;
 287                         else
 288                                 perflvl->memory = ROM16(entry[11]) * 2000;
 289                         break;
 290                 case 0x25:
 291                         perflvl->fanspeed = entry[4];
 292                         perflvl->volt_min = entry[5];
 293                         perflvl->core = ROM16(entry[6]) * 1000;
 294                         perflvl->shader = ROM16(entry[10]) * 1000;
 295                         perflvl->memory = ROM16(entry[12]) * 1000;
 296                         break;
 297                 case 0x30:
 298                         perflvl->memscript = ROM16(entry[2]);
 299                 case 0x35:
 300                         perflvl->fanspeed = entry[6];
 301                         perflvl->volt_min = entry[7];
 302                         perflvl->core = ROM16(entry[8]) * 1000;
 303                         perflvl->shader = ROM16(entry[10]) * 1000;
 304                         perflvl->memory = ROM16(entry[12]) * 1000;
 305                         perflvl->vdec = ROM16(entry[16]) * 1000;
 306                         perflvl->dom6 = ROM16(entry[20]) * 1000;
 307                         break;
 308                 case 0x40:
 309 #define subent(n) ((ROM16(entry[perf[2] + ((n) * perf[3])]) & 0xfff) * 1000)
 310                         perflvl->fanspeed = 0; /*XXX*/
 311                         perflvl->volt_min = entry[2];
 312                         if (dev_priv->card_type == NV_50) {
 313                                 perflvl->core   = subent(0);
 314                                 perflvl->shader = subent(1);
 315                                 perflvl->memory = subent(2);
 316                                 perflvl->vdec   = subent(3);
 317                                 perflvl->unka0  = subent(4);
 318                         } else {
 319                                 perflvl->hub06  = subent(0);
 320                                 perflvl->hub01  = subent(1);
 321                                 perflvl->copy   = subent(2);
 322                                 perflvl->shader = subent(3);
 323                                 perflvl->rop    = subent(4);
 324                                 perflvl->memory = subent(5);
 325                                 perflvl->vdec   = subent(6);
 326                                 perflvl->daemon = subent(10);
 327                                 perflvl->hub07  = subent(11);
 328                                 perflvl->core   = perflvl->shader / 2;
 329                         }
 330                         break;
 331                 }
 332
 333                 /* make sure vid is valid */
 334                 nouveau_perf_voltage(dev, &P, perflvl);
 335                 if (pm->voltage.supported && perflvl->volt_min) {
 336                         vid = nouveau_volt_vid_lookup(dev, perflvl->volt_min);
 337                         if (vid < 0) {
 338                                 NV_DEBUG(dev, "drop perflvl %d, bad vid\n", i);
 339                                 entry += recordlen;
 340                                 continue;
 341                         }
 342                 }
 343
 344                 /* get the corresponding memory timings */
 345                 if (version == 0x15) {
 346                         memtimings->timing[i].id = i;
 347                         nv30_mem_timing_entry(dev, &mt_hdr,
 348                                      (struct nouveau_pm_tbl_entry *) &entry[41],
 349                                      0, &memtimings->timing[i]);
 350                         perflvl->timing = &memtimings->timing[i];
 351                 } else if (version > 0x15) {
 352                         /* last 3 args are for < 0x40, ignored for >= 0x40 */
 353                         perflvl->timing =
 354                                 nouveau_perf_timing(dev, &P,
 355                                                     perflvl->memory / 1000,
 356                                                     entry + perf[3],
 357                                                     perf[5], perf[4]);
 358                 }
 359
 360                 snprintf(perflvl->name, sizeof(perflvl->name),
 361                          "performance_level_%d", i);
 362                 perflvl->id = i;
 363                 pm->nr_perflvl++;
 364
 365                 entry += recordlen;
 366         }
 367 }
 368
 369 void
 370 nouveau_perf_fini(struct drm_device *dev)
 371 {
 372 }