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drm/nv50: regression fix, point NVAA/NVAC at correct PM functions
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_state.c
1 /*
2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26 #include <linux/swab.h>
27 #include <linux/slab.h>
28 #include "drmP.h"
29 #include "drm.h"
30 #include "drm_sarea.h"
31 #include "drm_crtc_helper.h"
32 #include <linux/vgaarb.h>
33 #include <linux/vga_switcheroo.h>
34
35 #include "nouveau_drv.h"
36 #include "nouveau_drm.h"
37 #include "nouveau_fbcon.h"
38 #include "nouveau_ramht.h"
39 #include "nouveau_pm.h"
40 #include "nv50_display.h"
41
42 static void nouveau_stub_takedown(struct drm_device *dev) {}
43 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
44
45 static int nouveau_init_engine_ptrs(struct drm_device *dev)
46 {
47 struct drm_nouveau_private *dev_priv = dev->dev_private;
48 struct nouveau_engine *engine = &dev_priv->engine;
49
50 switch (dev_priv->chipset & 0xf0) {
51 case 0x00:
52 engine->instmem.init = nv04_instmem_init;
53 engine->instmem.takedown = nv04_instmem_takedown;
54 engine->instmem.suspend = nv04_instmem_suspend;
55 engine->instmem.resume = nv04_instmem_resume;
56 engine->instmem.populate = nv04_instmem_populate;
57 engine->instmem.clear = nv04_instmem_clear;
58 engine->instmem.bind = nv04_instmem_bind;
59 engine->instmem.unbind = nv04_instmem_unbind;
60 engine->instmem.flush = nv04_instmem_flush;
61 engine->mc.init = nv04_mc_init;
62 engine->mc.takedown = nv04_mc_takedown;
63 engine->timer.init = nv04_timer_init;
64 engine->timer.read = nv04_timer_read;
65 engine->timer.takedown = nv04_timer_takedown;
66 engine->fb.init = nv04_fb_init;
67 engine->fb.takedown = nv04_fb_takedown;
68 engine->graph.init = nv04_graph_init;
69 engine->graph.takedown = nv04_graph_takedown;
70 engine->graph.fifo_access = nv04_graph_fifo_access;
71 engine->graph.channel = nv04_graph_channel;
72 engine->graph.create_context = nv04_graph_create_context;
73 engine->graph.destroy_context = nv04_graph_destroy_context;
74 engine->graph.load_context = nv04_graph_load_context;
75 engine->graph.unload_context = nv04_graph_unload_context;
76 engine->fifo.channels = 16;
77 engine->fifo.init = nv04_fifo_init;
78 engine->fifo.takedown = nouveau_stub_takedown;
79 engine->fifo.disable = nv04_fifo_disable;
80 engine->fifo.enable = nv04_fifo_enable;
81 engine->fifo.reassign = nv04_fifo_reassign;
82 engine->fifo.cache_pull = nv04_fifo_cache_pull;
83 engine->fifo.channel_id = nv04_fifo_channel_id;
84 engine->fifo.create_context = nv04_fifo_create_context;
85 engine->fifo.destroy_context = nv04_fifo_destroy_context;
86 engine->fifo.load_context = nv04_fifo_load_context;
87 engine->fifo.unload_context = nv04_fifo_unload_context;
88 engine->display.early_init = nv04_display_early_init;
89 engine->display.late_takedown = nv04_display_late_takedown;
90 engine->display.create = nv04_display_create;
91 engine->display.init = nv04_display_init;
92 engine->display.destroy = nv04_display_destroy;
93 engine->gpio.init = nouveau_stub_init;
94 engine->gpio.takedown = nouveau_stub_takedown;
95 engine->gpio.get = NULL;
96 engine->gpio.set = NULL;
97 engine->gpio.irq_enable = NULL;
98 engine->pm.clock_get = nv04_pm_clock_get;
99 engine->pm.clock_pre = nv04_pm_clock_pre;
100 engine->pm.clock_set = nv04_pm_clock_set;
101 engine->crypt.init = nouveau_stub_init;
102 engine->crypt.takedown = nouveau_stub_takedown;
103 break;
104 case 0x10:
105 engine->instmem.init = nv04_instmem_init;
106 engine->instmem.takedown = nv04_instmem_takedown;
107 engine->instmem.suspend = nv04_instmem_suspend;
108 engine->instmem.resume = nv04_instmem_resume;
109 engine->instmem.populate = nv04_instmem_populate;
110 engine->instmem.clear = nv04_instmem_clear;
111 engine->instmem.bind = nv04_instmem_bind;
112 engine->instmem.unbind = nv04_instmem_unbind;
113 engine->instmem.flush = nv04_instmem_flush;
114 engine->mc.init = nv04_mc_init;
115 engine->mc.takedown = nv04_mc_takedown;
116 engine->timer.init = nv04_timer_init;
117 engine->timer.read = nv04_timer_read;
118 engine->timer.takedown = nv04_timer_takedown;
119 engine->fb.init = nv10_fb_init;
120 engine->fb.takedown = nv10_fb_takedown;
121 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
122 engine->graph.init = nv10_graph_init;
123 engine->graph.takedown = nv10_graph_takedown;
124 engine->graph.channel = nv10_graph_channel;
125 engine->graph.create_context = nv10_graph_create_context;
126 engine->graph.destroy_context = nv10_graph_destroy_context;
127 engine->graph.fifo_access = nv04_graph_fifo_access;
128 engine->graph.load_context = nv10_graph_load_context;
129 engine->graph.unload_context = nv10_graph_unload_context;
130 engine->graph.set_region_tiling = nv10_graph_set_region_tiling;
131 engine->fifo.channels = 32;
132 engine->fifo.init = nv10_fifo_init;
133 engine->fifo.takedown = nouveau_stub_takedown;
134 engine->fifo.disable = nv04_fifo_disable;
135 engine->fifo.enable = nv04_fifo_enable;
136 engine->fifo.reassign = nv04_fifo_reassign;
137 engine->fifo.cache_pull = nv04_fifo_cache_pull;
138 engine->fifo.channel_id = nv10_fifo_channel_id;
139 engine->fifo.create_context = nv10_fifo_create_context;
140 engine->fifo.destroy_context = nv04_fifo_destroy_context;
141 engine->fifo.load_context = nv10_fifo_load_context;
142 engine->fifo.unload_context = nv10_fifo_unload_context;
143 engine->display.early_init = nv04_display_early_init;
144 engine->display.late_takedown = nv04_display_late_takedown;
145 engine->display.create = nv04_display_create;
146 engine->display.init = nv04_display_init;
147 engine->display.destroy = nv04_display_destroy;
148 engine->gpio.init = nouveau_stub_init;
149 engine->gpio.takedown = nouveau_stub_takedown;
150 engine->gpio.get = nv10_gpio_get;
151 engine->gpio.set = nv10_gpio_set;
152 engine->gpio.irq_enable = NULL;
153 engine->pm.clock_get = nv04_pm_clock_get;
154 engine->pm.clock_pre = nv04_pm_clock_pre;
155 engine->pm.clock_set = nv04_pm_clock_set;
156 engine->crypt.init = nouveau_stub_init;
157 engine->crypt.takedown = nouveau_stub_takedown;
158 break;
159 case 0x20:
160 engine->instmem.init = nv04_instmem_init;
161 engine->instmem.takedown = nv04_instmem_takedown;
162 engine->instmem.suspend = nv04_instmem_suspend;
163 engine->instmem.resume = nv04_instmem_resume;
164 engine->instmem.populate = nv04_instmem_populate;
165 engine->instmem.clear = nv04_instmem_clear;
166 engine->instmem.bind = nv04_instmem_bind;
167 engine->instmem.unbind = nv04_instmem_unbind;
168 engine->instmem.flush = nv04_instmem_flush;
169 engine->mc.init = nv04_mc_init;
170 engine->mc.takedown = nv04_mc_takedown;
171 engine->timer.init = nv04_timer_init;
172 engine->timer.read = nv04_timer_read;
173 engine->timer.takedown = nv04_timer_takedown;
174 engine->fb.init = nv10_fb_init;
175 engine->fb.takedown = nv10_fb_takedown;
176 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
177 engine->graph.init = nv20_graph_init;
178 engine->graph.takedown = nv20_graph_takedown;
179 engine->graph.channel = nv10_graph_channel;
180 engine->graph.create_context = nv20_graph_create_context;
181 engine->graph.destroy_context = nv20_graph_destroy_context;
182 engine->graph.fifo_access = nv04_graph_fifo_access;
183 engine->graph.load_context = nv20_graph_load_context;
184 engine->graph.unload_context = nv20_graph_unload_context;
185 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
186 engine->fifo.channels = 32;
187 engine->fifo.init = nv10_fifo_init;
188 engine->fifo.takedown = nouveau_stub_takedown;
189 engine->fifo.disable = nv04_fifo_disable;
190 engine->fifo.enable = nv04_fifo_enable;
191 engine->fifo.reassign = nv04_fifo_reassign;
192 engine->fifo.cache_pull = nv04_fifo_cache_pull;
193 engine->fifo.channel_id = nv10_fifo_channel_id;
194 engine->fifo.create_context = nv10_fifo_create_context;
195 engine->fifo.destroy_context = nv04_fifo_destroy_context;
196 engine->fifo.load_context = nv10_fifo_load_context;
197 engine->fifo.unload_context = nv10_fifo_unload_context;
198 engine->display.early_init = nv04_display_early_init;
199 engine->display.late_takedown = nv04_display_late_takedown;
200 engine->display.create = nv04_display_create;
201 engine->display.init = nv04_display_init;
202 engine->display.destroy = nv04_display_destroy;
203 engine->gpio.init = nouveau_stub_init;
204 engine->gpio.takedown = nouveau_stub_takedown;
205 engine->gpio.get = nv10_gpio_get;
206 engine->gpio.set = nv10_gpio_set;
207 engine->gpio.irq_enable = NULL;
208 engine->pm.clock_get = nv04_pm_clock_get;
209 engine->pm.clock_pre = nv04_pm_clock_pre;
210 engine->pm.clock_set = nv04_pm_clock_set;
211 engine->crypt.init = nouveau_stub_init;
212 engine->crypt.takedown = nouveau_stub_takedown;
213 break;
214 case 0x30:
215 engine->instmem.init = nv04_instmem_init;
216 engine->instmem.takedown = nv04_instmem_takedown;
217 engine->instmem.suspend = nv04_instmem_suspend;
218 engine->instmem.resume = nv04_instmem_resume;
219 engine->instmem.populate = nv04_instmem_populate;
220 engine->instmem.clear = nv04_instmem_clear;
221 engine->instmem.bind = nv04_instmem_bind;
222 engine->instmem.unbind = nv04_instmem_unbind;
223 engine->instmem.flush = nv04_instmem_flush;
224 engine->mc.init = nv04_mc_init;
225 engine->mc.takedown = nv04_mc_takedown;
226 engine->timer.init = nv04_timer_init;
227 engine->timer.read = nv04_timer_read;
228 engine->timer.takedown = nv04_timer_takedown;
229 engine->fb.init = nv30_fb_init;
230 engine->fb.takedown = nv30_fb_takedown;
231 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
232 engine->graph.init = nv30_graph_init;
233 engine->graph.takedown = nv20_graph_takedown;
234 engine->graph.fifo_access = nv04_graph_fifo_access;
235 engine->graph.channel = nv10_graph_channel;
236 engine->graph.create_context = nv20_graph_create_context;
237 engine->graph.destroy_context = nv20_graph_destroy_context;
238 engine->graph.load_context = nv20_graph_load_context;
239 engine->graph.unload_context = nv20_graph_unload_context;
240 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
241 engine->fifo.channels = 32;
242 engine->fifo.init = nv10_fifo_init;
243 engine->fifo.takedown = nouveau_stub_takedown;
244 engine->fifo.disable = nv04_fifo_disable;
245 engine->fifo.enable = nv04_fifo_enable;
246 engine->fifo.reassign = nv04_fifo_reassign;
247 engine->fifo.cache_pull = nv04_fifo_cache_pull;
248 engine->fifo.channel_id = nv10_fifo_channel_id;
249 engine->fifo.create_context = nv10_fifo_create_context;
250 engine->fifo.destroy_context = nv04_fifo_destroy_context;
251 engine->fifo.load_context = nv10_fifo_load_context;
252 engine->fifo.unload_context = nv10_fifo_unload_context;
253 engine->display.early_init = nv04_display_early_init;
254 engine->display.late_takedown = nv04_display_late_takedown;
255 engine->display.create = nv04_display_create;
256 engine->display.init = nv04_display_init;
257 engine->display.destroy = nv04_display_destroy;
258 engine->gpio.init = nouveau_stub_init;
259 engine->gpio.takedown = nouveau_stub_takedown;
260 engine->gpio.get = nv10_gpio_get;
261 engine->gpio.set = nv10_gpio_set;
262 engine->gpio.irq_enable = NULL;
263 engine->pm.clock_get = nv04_pm_clock_get;
264 engine->pm.clock_pre = nv04_pm_clock_pre;
265 engine->pm.clock_set = nv04_pm_clock_set;
266 engine->pm.voltage_get = nouveau_voltage_gpio_get;
267 engine->pm.voltage_set = nouveau_voltage_gpio_set;
268 engine->crypt.init = nouveau_stub_init;
269 engine->crypt.takedown = nouveau_stub_takedown;
270 break;
271 case 0x40:
272 case 0x60:
273 engine->instmem.init = nv04_instmem_init;
274 engine->instmem.takedown = nv04_instmem_takedown;
275 engine->instmem.suspend = nv04_instmem_suspend;
276 engine->instmem.resume = nv04_instmem_resume;
277 engine->instmem.populate = nv04_instmem_populate;
278 engine->instmem.clear = nv04_instmem_clear;
279 engine->instmem.bind = nv04_instmem_bind;
280 engine->instmem.unbind = nv04_instmem_unbind;
281 engine->instmem.flush = nv04_instmem_flush;
282 engine->mc.init = nv40_mc_init;
283 engine->mc.takedown = nv40_mc_takedown;
284 engine->timer.init = nv04_timer_init;
285 engine->timer.read = nv04_timer_read;
286 engine->timer.takedown = nv04_timer_takedown;
287 engine->fb.init = nv40_fb_init;
288 engine->fb.takedown = nv40_fb_takedown;
289 engine->fb.set_region_tiling = nv40_fb_set_region_tiling;
290 engine->graph.init = nv40_graph_init;
291 engine->graph.takedown = nv40_graph_takedown;
292 engine->graph.fifo_access = nv04_graph_fifo_access;
293 engine->graph.channel = nv40_graph_channel;
294 engine->graph.create_context = nv40_graph_create_context;
295 engine->graph.destroy_context = nv40_graph_destroy_context;
296 engine->graph.load_context = nv40_graph_load_context;
297 engine->graph.unload_context = nv40_graph_unload_context;
298 engine->graph.set_region_tiling = nv40_graph_set_region_tiling;
299 engine->fifo.channels = 32;
300 engine->fifo.init = nv40_fifo_init;
301 engine->fifo.takedown = nouveau_stub_takedown;
302 engine->fifo.disable = nv04_fifo_disable;
303 engine->fifo.enable = nv04_fifo_enable;
304 engine->fifo.reassign = nv04_fifo_reassign;
305 engine->fifo.cache_pull = nv04_fifo_cache_pull;
306 engine->fifo.channel_id = nv10_fifo_channel_id;
307 engine->fifo.create_context = nv40_fifo_create_context;
308 engine->fifo.destroy_context = nv04_fifo_destroy_context;
309 engine->fifo.load_context = nv40_fifo_load_context;
310 engine->fifo.unload_context = nv40_fifo_unload_context;
311 engine->display.early_init = nv04_display_early_init;
312 engine->display.late_takedown = nv04_display_late_takedown;
313 engine->display.create = nv04_display_create;
314 engine->display.init = nv04_display_init;
315 engine->display.destroy = nv04_display_destroy;
316 engine->gpio.init = nouveau_stub_init;
317 engine->gpio.takedown = nouveau_stub_takedown;
318 engine->gpio.get = nv10_gpio_get;
319 engine->gpio.set = nv10_gpio_set;
320 engine->gpio.irq_enable = NULL;
321 engine->pm.clock_get = nv04_pm_clock_get;
322 engine->pm.clock_pre = nv04_pm_clock_pre;
323 engine->pm.clock_set = nv04_pm_clock_set;
324 engine->pm.voltage_get = nouveau_voltage_gpio_get;
325 engine->pm.voltage_set = nouveau_voltage_gpio_set;
326 engine->pm.temp_get = nv40_temp_get;
327 engine->crypt.init = nouveau_stub_init;
328 engine->crypt.takedown = nouveau_stub_takedown;
329 break;
330 case 0x50:
331 case 0x80: /* gotta love NVIDIA's consistency.. */
332 case 0x90:
333 case 0xA0:
334 engine->instmem.init = nv50_instmem_init;
335 engine->instmem.takedown = nv50_instmem_takedown;
336 engine->instmem.suspend = nv50_instmem_suspend;
337 engine->instmem.resume = nv50_instmem_resume;
338 engine->instmem.populate = nv50_instmem_populate;
339 engine->instmem.clear = nv50_instmem_clear;
340 engine->instmem.bind = nv50_instmem_bind;
341 engine->instmem.unbind = nv50_instmem_unbind;
342 if (dev_priv->chipset == 0x50)
343 engine->instmem.flush = nv50_instmem_flush;
344 else
345 engine->instmem.flush = nv84_instmem_flush;
346 engine->mc.init = nv50_mc_init;
347 engine->mc.takedown = nv50_mc_takedown;
348 engine->timer.init = nv04_timer_init;
349 engine->timer.read = nv04_timer_read;
350 engine->timer.takedown = nv04_timer_takedown;
351 engine->fb.init = nv50_fb_init;
352 engine->fb.takedown = nv50_fb_takedown;
353 engine->graph.init = nv50_graph_init;
354 engine->graph.takedown = nv50_graph_takedown;
355 engine->graph.fifo_access = nv50_graph_fifo_access;
356 engine->graph.channel = nv50_graph_channel;
357 engine->graph.create_context = nv50_graph_create_context;
358 engine->graph.destroy_context = nv50_graph_destroy_context;
359 engine->graph.load_context = nv50_graph_load_context;
360 engine->graph.unload_context = nv50_graph_unload_context;
361 if (dev_priv->chipset != 0x86)
362 engine->graph.tlb_flush = nv50_graph_tlb_flush;
363 else {
364 /* from what i can see nvidia do this on every
365 * pre-NVA3 board except NVAC, but, we've only
366 * ever seen problems on NV86
367 */
368 engine->graph.tlb_flush = nv86_graph_tlb_flush;
369 }
370 engine->fifo.channels = 128;
371 engine->fifo.init = nv50_fifo_init;
372 engine->fifo.takedown = nv50_fifo_takedown;
373 engine->fifo.disable = nv04_fifo_disable;
374 engine->fifo.enable = nv04_fifo_enable;
375 engine->fifo.reassign = nv04_fifo_reassign;
376 engine->fifo.channel_id = nv50_fifo_channel_id;
377 engine->fifo.create_context = nv50_fifo_create_context;
378 engine->fifo.destroy_context = nv50_fifo_destroy_context;
379 engine->fifo.load_context = nv50_fifo_load_context;
380 engine->fifo.unload_context = nv50_fifo_unload_context;
381 engine->fifo.tlb_flush = nv50_fifo_tlb_flush;
382 engine->display.early_init = nv50_display_early_init;
383 engine->display.late_takedown = nv50_display_late_takedown;
384 engine->display.create = nv50_display_create;
385 engine->display.init = nv50_display_init;
386 engine->display.destroy = nv50_display_destroy;
387 engine->gpio.init = nv50_gpio_init;
388 engine->gpio.takedown = nouveau_stub_takedown;
389 engine->gpio.get = nv50_gpio_get;
390 engine->gpio.set = nv50_gpio_set;
391 engine->gpio.irq_enable = nv50_gpio_irq_enable;
392 switch (dev_priv->chipset) {
393 case 0x84:
394 case 0x86:
395 case 0x92:
396 case 0x94:
397 case 0x96:
398 case 0x98:
399 case 0xa0:
400 case 0xaa:
401 case 0xac:
402 case 0x50:
403 engine->pm.clock_get = nv50_pm_clock_get;
404 engine->pm.clock_pre = nv50_pm_clock_pre;
405 engine->pm.clock_set = nv50_pm_clock_set;
406 break;
407 default:
408 engine->pm.clock_get = nva3_pm_clock_get;
409 engine->pm.clock_pre = nva3_pm_clock_pre;
410 engine->pm.clock_set = nva3_pm_clock_set;
411 break;
412 }
413 engine->pm.voltage_get = nouveau_voltage_gpio_get;
414 engine->pm.voltage_set = nouveau_voltage_gpio_set;
415 if (dev_priv->chipset >= 0x84)
416 engine->pm.temp_get = nv84_temp_get;
417 else
418 engine->pm.temp_get = nv40_temp_get;
419 switch (dev_priv->chipset) {
420 case 0x84:
421 case 0x86:
422 case 0x92:
423 case 0x94:
424 case 0x96:
425 case 0xa0:
426 engine->crypt.init = nv84_crypt_init;
427 engine->crypt.takedown = nv84_crypt_fini;
428 engine->crypt.create_context = nv84_crypt_create_context;
429 engine->crypt.destroy_context = nv84_crypt_destroy_context;
430 break;
431 default:
432 engine->crypt.init = nouveau_stub_init;
433 engine->crypt.takedown = nouveau_stub_takedown;
434 break;
435 }
436 break;
437 case 0xC0:
438 engine->instmem.init = nvc0_instmem_init;
439 engine->instmem.takedown = nvc0_instmem_takedown;
440 engine->instmem.suspend = nvc0_instmem_suspend;
441 engine->instmem.resume = nvc0_instmem_resume;
442 engine->instmem.populate = nvc0_instmem_populate;
443 engine->instmem.clear = nvc0_instmem_clear;
444 engine->instmem.bind = nvc0_instmem_bind;
445 engine->instmem.unbind = nvc0_instmem_unbind;
446 engine->instmem.flush = nvc0_instmem_flush;
447 engine->mc.init = nv50_mc_init;
448 engine->mc.takedown = nv50_mc_takedown;
449 engine->timer.init = nv04_timer_init;
450 engine->timer.read = nv04_timer_read;
451 engine->timer.takedown = nv04_timer_takedown;
452 engine->fb.init = nvc0_fb_init;
453 engine->fb.takedown = nvc0_fb_takedown;
454 engine->graph.init = nvc0_graph_init;
455 engine->graph.takedown = nvc0_graph_takedown;
456 engine->graph.fifo_access = nvc0_graph_fifo_access;
457 engine->graph.channel = nvc0_graph_channel;
458 engine->graph.create_context = nvc0_graph_create_context;
459 engine->graph.destroy_context = nvc0_graph_destroy_context;
460 engine->graph.load_context = nvc0_graph_load_context;
461 engine->graph.unload_context = nvc0_graph_unload_context;
462 engine->fifo.channels = 128;
463 engine->fifo.init = nvc0_fifo_init;
464 engine->fifo.takedown = nvc0_fifo_takedown;
465 engine->fifo.disable = nvc0_fifo_disable;
466 engine->fifo.enable = nvc0_fifo_enable;
467 engine->fifo.reassign = nvc0_fifo_reassign;
468 engine->fifo.channel_id = nvc0_fifo_channel_id;
469 engine->fifo.create_context = nvc0_fifo_create_context;
470 engine->fifo.destroy_context = nvc0_fifo_destroy_context;
471 engine->fifo.load_context = nvc0_fifo_load_context;
472 engine->fifo.unload_context = nvc0_fifo_unload_context;
473 engine->display.early_init = nv50_display_early_init;
474 engine->display.late_takedown = nv50_display_late_takedown;
475 engine->display.create = nv50_display_create;
476 engine->display.init = nv50_display_init;
477 engine->display.destroy = nv50_display_destroy;
478 engine->gpio.init = nv50_gpio_init;
479 engine->gpio.takedown = nouveau_stub_takedown;
480 engine->gpio.get = nv50_gpio_get;
481 engine->gpio.set = nv50_gpio_set;
482 engine->gpio.irq_enable = nv50_gpio_irq_enable;
483 engine->crypt.init = nouveau_stub_init;
484 engine->crypt.takedown = nouveau_stub_takedown;
485 break;
486 default:
487 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
488 return 1;
489 }
490
491 return 0;
492 }
493
494 static unsigned int
495 nouveau_vga_set_decode(void *priv, bool state)
496 {
497 struct drm_device *dev = priv;
498 struct drm_nouveau_private *dev_priv = dev->dev_private;
499
500 if (dev_priv->chipset >= 0x40)
501 nv_wr32(dev, 0x88054, state);
502 else
503 nv_wr32(dev, 0x1854, state);
504
505 if (state)
506 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
507 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
508 else
509 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
510 }
511
512 static int
513 nouveau_card_init_channel(struct drm_device *dev)
514 {
515 struct drm_nouveau_private *dev_priv = dev->dev_private;
516 struct nouveau_gpuobj *gpuobj = NULL;
517 int ret;
518
519 ret = nouveau_channel_alloc(dev, &dev_priv->channel,
520 (struct drm_file *)-2, NvDmaFB, NvDmaTT);
521 if (ret)
522 return ret;
523
524 ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
525 0, dev_priv->vram_size,
526 NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
527 &gpuobj);
528 if (ret)
529 goto out_err;
530
531 ret = nouveau_ramht_insert(dev_priv->channel, NvDmaVRAM, gpuobj);
532 nouveau_gpuobj_ref(NULL, &gpuobj);
533 if (ret)
534 goto out_err;
535
536 ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
537 dev_priv->gart_info.aper_size,
538 NV_DMA_ACCESS_RW, &gpuobj, NULL);
539 if (ret)
540 goto out_err;
541
542 ret = nouveau_ramht_insert(dev_priv->channel, NvDmaGART, gpuobj);
543 nouveau_gpuobj_ref(NULL, &gpuobj);
544 if (ret)
545 goto out_err;
546
547 mutex_unlock(&dev_priv->channel->mutex);
548 return 0;
549
550 out_err:
551 nouveau_channel_put(&dev_priv->channel);
552 return ret;
553 }
554
555 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
556 enum vga_switcheroo_state state)
557 {
558 struct drm_device *dev = pci_get_drvdata(pdev);
559 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
560 if (state == VGA_SWITCHEROO_ON) {
561 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
562 nouveau_pci_resume(pdev);
563 drm_kms_helper_poll_enable(dev);
564 } else {
565 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
566 drm_kms_helper_poll_disable(dev);
567 nouveau_pci_suspend(pdev, pmm);
568 }
569 }
570
571 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
572 {
573 struct drm_device *dev = pci_get_drvdata(pdev);
574 bool can_switch;
575
576 spin_lock(&dev->count_lock);
577 can_switch = (dev->open_count == 0);
578 spin_unlock(&dev->count_lock);
579 return can_switch;
580 }
581
582 int
583 nouveau_card_init(struct drm_device *dev)
584 {
585 struct drm_nouveau_private *dev_priv = dev->dev_private;
586 struct nouveau_engine *engine;
587 int ret;
588
589 vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
590 vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
591 nouveau_switcheroo_can_switch);
592
593 /* Initialise internal driver API hooks */
594 ret = nouveau_init_engine_ptrs(dev);
595 if (ret)
596 goto out;
597 engine = &dev_priv->engine;
598 spin_lock_init(&dev_priv->channels.lock);
599 spin_lock_init(&dev_priv->context_switch_lock);
600
601 /* Make the CRTCs and I2C buses accessible */
602 ret = engine->display.early_init(dev);
603 if (ret)
604 goto out;
605
606 /* Parse BIOS tables / Run init tables if card not POSTed */
607 ret = nouveau_bios_init(dev);
608 if (ret)
609 goto out_display_early;
610
611 nouveau_pm_init(dev);
612
613 ret = nouveau_mem_vram_init(dev);
614 if (ret)
615 goto out_bios;
616
617 ret = nouveau_gpuobj_init(dev);
618 if (ret)
619 goto out_vram;
620
621 ret = engine->instmem.init(dev);
622 if (ret)
623 goto out_gpuobj;
624
625 ret = nouveau_mem_gart_init(dev);
626 if (ret)
627 goto out_instmem;
628
629 /* PMC */
630 ret = engine->mc.init(dev);
631 if (ret)
632 goto out_gart;
633
634 /* PGPIO */
635 ret = engine->gpio.init(dev);
636 if (ret)
637 goto out_mc;
638
639 /* PTIMER */
640 ret = engine->timer.init(dev);
641 if (ret)
642 goto out_gpio;
643
644 /* PFB */
645 ret = engine->fb.init(dev);
646 if (ret)
647 goto out_timer;
648
649 if (nouveau_noaccel)
650 engine->graph.accel_blocked = true;
651 else {
652 /* PGRAPH */
653 ret = engine->graph.init(dev);
654 if (ret)
655 goto out_fb;
656
657 /* PCRYPT */
658 ret = engine->crypt.init(dev);
659 if (ret)
660 goto out_graph;
661
662 /* PFIFO */
663 ret = engine->fifo.init(dev);
664 if (ret)
665 goto out_crypt;
666 }
667
668 ret = engine->display.create(dev);
669 if (ret)
670 goto out_fifo;
671
672 ret = nouveau_irq_init(dev);
673 if (ret)
674 goto out_display;
675
676 ret = drm_vblank_init(dev, 0);
677 if (ret)
678 goto out_irq;
679
680 /* what about PVIDEO/PCRTC/PRAMDAC etc? */
681
682 if (!engine->graph.accel_blocked) {
683 ret = nouveau_fence_init(dev);
684 if (ret)
685 goto out_irq;
686
687 ret = nouveau_card_init_channel(dev);
688 if (ret)
689 goto out_fence;
690 }
691
692 ret = nouveau_backlight_init(dev);
693 if (ret)
694 NV_ERROR(dev, "Error %d registering backlight\n", ret);
695
696 nouveau_fbcon_init(dev);
697 drm_kms_helper_poll_init(dev);
698 return 0;
699
700 out_fence:
701 nouveau_fence_fini(dev);
702 out_irq:
703 nouveau_irq_fini(dev);
704 out_display:
705 engine->display.destroy(dev);
706 out_fifo:
707 if (!nouveau_noaccel)
708 engine->fifo.takedown(dev);
709 out_crypt:
710 if (!nouveau_noaccel)
711 engine->crypt.takedown(dev);
712 out_graph:
713 if (!nouveau_noaccel)
714 engine->graph.takedown(dev);
715 out_fb:
716 engine->fb.takedown(dev);
717 out_timer:
718 engine->timer.takedown(dev);
719 out_gpio:
720 engine->gpio.takedown(dev);
721 out_mc:
722 engine->mc.takedown(dev);
723 out_gart:
724 nouveau_mem_gart_fini(dev);
725 out_instmem:
726 engine->instmem.takedown(dev);
727 out_gpuobj:
728 nouveau_gpuobj_takedown(dev);
729 out_vram:
730 nouveau_mem_vram_fini(dev);
731 out_bios:
732 nouveau_pm_fini(dev);
733 nouveau_bios_takedown(dev);
734 out_display_early:
735 engine->display.late_takedown(dev);
736 out:
737 vga_client_register(dev->pdev, NULL, NULL, NULL);
738 return ret;
739 }
740
741 static void nouveau_card_takedown(struct drm_device *dev)
742 {
743 struct drm_nouveau_private *dev_priv = dev->dev_private;
744 struct nouveau_engine *engine = &dev_priv->engine;
745
746 nouveau_backlight_exit(dev);
747
748 if (!engine->graph.accel_blocked) {
749 nouveau_fence_fini(dev);
750 nouveau_channel_put_unlocked(&dev_priv->channel);
751 }
752
753 if (!nouveau_noaccel) {
754 engine->fifo.takedown(dev);
755 engine->crypt.takedown(dev);
756 engine->graph.takedown(dev);
757 }
758 engine->fb.takedown(dev);
759 engine->timer.takedown(dev);
760 engine->gpio.takedown(dev);
761 engine->mc.takedown(dev);
762 engine->display.late_takedown(dev);
763
764 mutex_lock(&dev->struct_mutex);
765 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
766 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
767 mutex_unlock(&dev->struct_mutex);
768 nouveau_mem_gart_fini(dev);
769
770 engine->instmem.takedown(dev);
771 nouveau_gpuobj_takedown(dev);
772 nouveau_mem_vram_fini(dev);
773
774 nouveau_irq_fini(dev);
775
776 nouveau_pm_fini(dev);
777 nouveau_bios_takedown(dev);
778
779 vga_client_register(dev->pdev, NULL, NULL, NULL);
780 }
781
782 /* here a client dies, release the stuff that was allocated for its
783 * file_priv */
784 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
785 {
786 nouveau_channel_cleanup(dev, file_priv);
787 }
788
789 /* first module load, setup the mmio/fb mapping */
790 /* KMS: we need mmio at load time, not when the first drm client opens. */
791 int nouveau_firstopen(struct drm_device *dev)
792 {
793 return 0;
794 }
795
796 /* if we have an OF card, copy vbios to RAMIN */
797 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
798 {
799 #if defined(__powerpc__)
800 int size, i;
801 const uint32_t *bios;
802 struct device_node *dn = pci_device_to_OF_node(dev->pdev);
803 if (!dn) {
804 NV_INFO(dev, "Unable to get the OF node\n");
805 return;
806 }
807
808 bios = of_get_property(dn, "NVDA,BMP", &size);
809 if (bios) {
810 for (i = 0; i < size; i += 4)
811 nv_wi32(dev, i, bios[i/4]);
812 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
813 } else {
814 NV_INFO(dev, "Unable to get the OF bios\n");
815 }
816 #endif
817 }
818
819 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
820 {
821 struct pci_dev *pdev = dev->pdev;
822 struct apertures_struct *aper = alloc_apertures(3);
823 if (!aper)
824 return NULL;
825
826 aper->ranges[0].base = pci_resource_start(pdev, 1);
827 aper->ranges[0].size = pci_resource_len(pdev, 1);
828 aper->count = 1;
829
830 if (pci_resource_len(pdev, 2)) {
831 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
832 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
833 aper->count++;
834 }
835
836 if (pci_resource_len(pdev, 3)) {
837 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
838 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
839 aper->count++;
840 }
841
842 return aper;
843 }
844
845 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
846 {
847 struct drm_nouveau_private *dev_priv = dev->dev_private;
848 bool primary = false;
849 dev_priv->apertures = nouveau_get_apertures(dev);
850 if (!dev_priv->apertures)
851 return -ENOMEM;
852
853 #ifdef CONFIG_X86
854 primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
855 #endif
856
857 remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
858 return 0;
859 }
860
861 int nouveau_load(struct drm_device *dev, unsigned long flags)
862 {
863 struct drm_nouveau_private *dev_priv;
864 uint32_t reg0;
865 resource_size_t mmio_start_offs;
866 int ret;
867
868 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
869 if (!dev_priv) {
870 ret = -ENOMEM;
871 goto err_out;
872 }
873 dev->dev_private = dev_priv;
874 dev_priv->dev = dev;
875
876 dev_priv->flags = flags & NOUVEAU_FLAGS;
877
878 NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
879 dev->pci_vendor, dev->pci_device, dev->pdev->class);
880
881 dev_priv->wq = create_workqueue("nouveau");
882 if (!dev_priv->wq) {
883 ret = -EINVAL;
884 goto err_priv;
885 }
886
887 /* resource 0 is mmio regs */
888 /* resource 1 is linear FB */
889 /* resource 2 is RAMIN (mmio regs + 0x1000000) */
890 /* resource 6 is bios */
891
892 /* map the mmio regs */
893 mmio_start_offs = pci_resource_start(dev->pdev, 0);
894 dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
895 if (!dev_priv->mmio) {
896 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
897 "Please report your setup to " DRIVER_EMAIL "\n");
898 ret = -EINVAL;
899 goto err_wq;
900 }
901 NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
902 (unsigned long long)mmio_start_offs);
903
904 #ifdef __BIG_ENDIAN
905 /* Put the card in BE mode if it's not */
906 if (nv_rd32(dev, NV03_PMC_BOOT_1))
907 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
908
909 DRM_MEMORYBARRIER();
910 #endif
911
912 /* Time to determine the card architecture */
913 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
914
915 /* We're dealing with >=NV10 */
916 if ((reg0 & 0x0f000000) > 0) {
917 /* Bit 27-20 contain the architecture in hex */
918 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
919 /* NV04 or NV05 */
920 } else if ((reg0 & 0xff00fff0) == 0x20004000) {
921 if (reg0 & 0x00f00000)
922 dev_priv->chipset = 0x05;
923 else
924 dev_priv->chipset = 0x04;
925 } else
926 dev_priv->chipset = 0xff;
927
928 switch (dev_priv->chipset & 0xf0) {
929 case 0x00:
930 case 0x10:
931 case 0x20:
932 case 0x30:
933 dev_priv->card_type = dev_priv->chipset & 0xf0;
934 break;
935 case 0x40:
936 case 0x60:
937 dev_priv->card_type = NV_40;
938 break;
939 case 0x50:
940 case 0x80:
941 case 0x90:
942 case 0xa0:
943 dev_priv->card_type = NV_50;
944 break;
945 case 0xc0:
946 dev_priv->card_type = NV_C0;
947 break;
948 default:
949 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
950 ret = -EINVAL;
951 goto err_mmio;
952 }
953
954 NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
955 dev_priv->card_type, reg0);
956
957 ret = nouveau_remove_conflicting_drivers(dev);
958 if (ret)
959 goto err_mmio;
960
961 /* Map PRAMIN BAR, or on older cards, the aperture withing BAR0 */
962 if (dev_priv->card_type >= NV_40) {
963 int ramin_bar = 2;
964 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
965 ramin_bar = 3;
966
967 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
968 dev_priv->ramin =
969 ioremap(pci_resource_start(dev->pdev, ramin_bar),
970 dev_priv->ramin_size);
971 if (!dev_priv->ramin) {
972 NV_ERROR(dev, "Failed to PRAMIN BAR");
973 ret = -ENOMEM;
974 goto err_mmio;
975 }
976 } else {
977 dev_priv->ramin_size = 1 * 1024 * 1024;
978 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
979 dev_priv->ramin_size);
980 if (!dev_priv->ramin) {
981 NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
982 ret = -ENOMEM;
983 goto err_mmio;
984 }
985 }
986
987 nouveau_OF_copy_vbios_to_ramin(dev);
988
989 /* Special flags */
990 if (dev->pci_device == 0x01a0)
991 dev_priv->flags |= NV_NFORCE;
992 else if (dev->pci_device == 0x01f0)
993 dev_priv->flags |= NV_NFORCE2;
994
995 /* For kernel modesetting, init card now and bring up fbcon */
996 ret = nouveau_card_init(dev);
997 if (ret)
998 goto err_ramin;
999
1000 return 0;
1001
1002 err_ramin:
1003 iounmap(dev_priv->ramin);
1004 err_mmio:
1005 iounmap(dev_priv->mmio);
1006 err_wq:
1007 destroy_workqueue(dev_priv->wq);
1008 err_priv:
1009 kfree(dev_priv);
1010 dev->dev_private = NULL;
1011 err_out:
1012 return ret;
1013 }
1014
1015 void nouveau_lastclose(struct drm_device *dev)
1016 {
1017 }
1018
1019 int nouveau_unload(struct drm_device *dev)
1020 {
1021 struct drm_nouveau_private *dev_priv = dev->dev_private;
1022 struct nouveau_engine *engine = &dev_priv->engine;
1023
1024 drm_kms_helper_poll_fini(dev);
1025 nouveau_fbcon_fini(dev);
1026 engine->display.destroy(dev);
1027 nouveau_card_takedown(dev);
1028
1029 iounmap(dev_priv->mmio);
1030 iounmap(dev_priv->ramin);
1031
1032 kfree(dev_priv);
1033 dev->dev_private = NULL;
1034 return 0;
1035 }
1036
1037 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1038 struct drm_file *file_priv)
1039 {
1040 struct drm_nouveau_private *dev_priv = dev->dev_private;
1041 struct drm_nouveau_getparam *getparam = data;
1042
1043 switch (getparam->param) {
1044 case NOUVEAU_GETPARAM_CHIPSET_ID:
1045 getparam->value = dev_priv->chipset;
1046 break;
1047 case NOUVEAU_GETPARAM_PCI_VENDOR:
1048 getparam->value = dev->pci_vendor;
1049 break;
1050 case NOUVEAU_GETPARAM_PCI_DEVICE:
1051 getparam->value = dev->pci_device;
1052 break;
1053 case NOUVEAU_GETPARAM_BUS_TYPE:
1054 if (drm_device_is_agp(dev))
1055 getparam->value = NV_AGP;
1056 else if (drm_device_is_pcie(dev))
1057 getparam->value = NV_PCIE;
1058 else
1059 getparam->value = NV_PCI;
1060 break;
1061 case NOUVEAU_GETPARAM_FB_PHYSICAL:
1062 getparam->value = dev_priv->fb_phys;
1063 break;
1064 case NOUVEAU_GETPARAM_AGP_PHYSICAL:
1065 getparam->value = dev_priv->gart_info.aper_base;
1066 break;
1067 case NOUVEAU_GETPARAM_PCI_PHYSICAL:
1068 if (dev->sg) {
1069 getparam->value = (unsigned long)dev->sg->virtual;
1070 } else {
1071 NV_ERROR(dev, "Requested PCIGART address, "
1072 "while no PCIGART was created\n");
1073 return -EINVAL;
1074 }
1075 break;
1076 case NOUVEAU_GETPARAM_FB_SIZE:
1077 getparam->value = dev_priv->fb_available_size;
1078 break;
1079 case NOUVEAU_GETPARAM_AGP_SIZE:
1080 getparam->value = dev_priv->gart_info.aper_size;
1081 break;
1082 case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1083 getparam->value = dev_priv->vm_vram_base;
1084 break;
1085 case NOUVEAU_GETPARAM_PTIMER_TIME:
1086 getparam->value = dev_priv->engine.timer.read(dev);
1087 break;
1088 case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1089 getparam->value = 1;
1090 break;
1091 case NOUVEAU_GETPARAM_GRAPH_UNITS:
1092 /* NV40 and NV50 versions are quite different, but register
1093 * address is the same. User is supposed to know the card
1094 * family anyway... */
1095 if (dev_priv->chipset >= 0x40) {
1096 getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1097 break;
1098 }
1099 /* FALLTHRU */
1100 default:
1101 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1102 return -EINVAL;
1103 }
1104
1105 return 0;
1106 }
1107
1108 int
1109 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1110 struct drm_file *file_priv)
1111 {
1112 struct drm_nouveau_setparam *setparam = data;
1113
1114 switch (setparam->param) {
1115 default:
1116 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1117 return -EINVAL;
1118 }
1119
1120 return 0;
1121 }
1122
1123 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1124 bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout,
1125 uint32_t reg, uint32_t mask, uint32_t val)
1126 {
1127 struct drm_nouveau_private *dev_priv = dev->dev_private;
1128 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1129 uint64_t start = ptimer->read(dev);
1130
1131 do {
1132 if ((nv_rd32(dev, reg) & mask) == val)
1133 return true;
1134 } while (ptimer->read(dev) - start < timeout);
1135
1136 return false;
1137 }
1138
1139 /* Waits for PGRAPH to go completely idle */
1140 bool nouveau_wait_for_idle(struct drm_device *dev)
1141 {
1142 struct drm_nouveau_private *dev_priv = dev->dev_private;
1143 uint32_t mask = ~0;
1144
1145 if (dev_priv->card_type == NV_40)
1146 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1147
1148 if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1149 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1150 nv_rd32(dev, NV04_PGRAPH_STATUS));
1151 return false;
1152 }
1153
1154 return true;
1155 }
1156
Linux kernel - Deliverables
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