2 * Copyright 2003 NVIDIA, Corporation
3 * Copyright 2006 Dave Airlie
4 * Copyright 2007 Maarten Maathuis
5 * Copyright 2007-2009 Stuart Bennett
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 #include "drm_crtc_helper.h"
30 #include "nouveau_drv.h"
31 #include "nouveau_encoder.h"
32 #include "nouveau_connector.h"
33 #include "nouveau_crtc.h"
34 #include "nouveau_hw.h"
37 #include "i2c/sil164.h"
39 #define FP_TG_CONTROL_ON (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | \
40 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS | \
41 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS)
42 #define FP_TG_CONTROL_OFF (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE | \
43 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_DISABLE | \
44 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_DISABLE)
46 static inline bool is_fpc_off(uint32_t fpc
)
48 return ((fpc
& (FP_TG_CONTROL_ON
| FP_TG_CONTROL_OFF
)) ==
52 int nv04_dfp_get_bound_head(struct drm_device
*dev
, struct dcb_entry
*dcbent
)
54 /* special case of nv_read_tmds to find crtc associated with an output.
55 * this does not give a correct answer for off-chip dvi, but there's no
56 * use for such an answer anyway
58 int ramdac
= (dcbent
->or & OUTPUT_C
) >> 2;
60 NVWriteRAMDAC(dev
, ramdac
, NV_PRAMDAC_FP_TMDS_CONTROL
,
61 NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE
| 0x4);
62 return ((NVReadRAMDAC(dev
, ramdac
, NV_PRAMDAC_FP_TMDS_DATA
) & 0x8) >> 3) ^ ramdac
;
65 void nv04_dfp_bind_head(struct drm_device
*dev
, struct dcb_entry
*dcbent
,
68 /* The BIOS scripts don't do this for us, sadly
69 * Luckily we do know the values ;-)
71 * head < 0 indicates we wish to force a setting with the overrideval
72 * (for VT restore etc.)
75 int ramdac
= (dcbent
->or & OUTPUT_C
) >> 2;
76 uint8_t tmds04
= 0x80;
81 if (dcbent
->type
== OUTPUT_LVDS
)
84 nv_write_tmds(dev
, dcbent
->or, 0, 0x04, tmds04
);
86 if (dl
) /* dual link */
87 nv_write_tmds(dev
, dcbent
->or, 1, 0x04, tmds04
^ 0x08);
90 void nv04_dfp_disable(struct drm_device
*dev
, int head
)
92 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
93 struct nv04_crtc_reg
*crtcstate
= dev_priv
->mode_reg
.crtc_reg
;
95 if (NVReadRAMDAC(dev
, head
, NV_PRAMDAC_FP_TG_CONTROL
) &
97 /* digital remnants must be cleaned before new crtc
98 * values programmed. delay is time for the vga stuff
99 * to realise it's in control again
101 NVWriteRAMDAC(dev
, head
, NV_PRAMDAC_FP_TG_CONTROL
,
105 /* don't inadvertently turn it on when state written later */
106 crtcstate
[head
].fp_control
= FP_TG_CONTROL_OFF
;
109 void nv04_dfp_update_fp_control(struct drm_encoder
*encoder
, int mode
)
111 struct drm_device
*dev
= encoder
->dev
;
112 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
113 struct drm_crtc
*crtc
;
114 struct nouveau_crtc
*nv_crtc
;
117 if (mode
== DRM_MODE_DPMS_ON
) {
118 nv_crtc
= nouveau_crtc(encoder
->crtc
);
119 fpc
= &dev_priv
->mode_reg
.crtc_reg
[nv_crtc
->index
].fp_control
;
121 if (is_fpc_off(*fpc
)) {
122 /* using saved value is ok, as (is_digital && dpms_on &&
123 * fp_control==OFF) is (at present) *only* true when
124 * fpc's most recent change was by below "off" code
126 *fpc
= nv_crtc
->dpms_saved_fp_control
;
129 nv_crtc
->fp_users
|= 1 << nouveau_encoder(encoder
)->dcb
->index
;
130 NVWriteRAMDAC(dev
, nv_crtc
->index
, NV_PRAMDAC_FP_TG_CONTROL
, *fpc
);
132 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
133 nv_crtc
= nouveau_crtc(crtc
);
134 fpc
= &dev_priv
->mode_reg
.crtc_reg
[nv_crtc
->index
].fp_control
;
136 nv_crtc
->fp_users
&= ~(1 << nouveau_encoder(encoder
)->dcb
->index
);
137 if (!is_fpc_off(*fpc
) && !nv_crtc
->fp_users
) {
138 nv_crtc
->dpms_saved_fp_control
= *fpc
;
139 /* cut the FP output */
140 *fpc
&= ~FP_TG_CONTROL_ON
;
141 *fpc
|= FP_TG_CONTROL_OFF
;
142 NVWriteRAMDAC(dev
, nv_crtc
->index
,
143 NV_PRAMDAC_FP_TG_CONTROL
, *fpc
);
149 static struct drm_encoder
*get_tmds_slave(struct drm_encoder
*encoder
)
151 struct drm_device
*dev
= encoder
->dev
;
152 struct dcb_entry
*dcb
= nouveau_encoder(encoder
)->dcb
;
153 struct drm_encoder
*slave
;
155 if (dcb
->type
!= OUTPUT_TMDS
|| dcb
->location
== DCB_LOC_ON_CHIP
)
158 /* Some BIOSes (e.g. the one in a Quadro FX1000) report several
159 * TMDS transmitters at the same I2C address, in the same I2C
160 * bus. This can still work because in that case one of them is
161 * always hard-wired to a reasonable configuration using straps,
162 * and the other one needs to be programmed.
164 * I don't think there's a way to know which is which, even the
165 * blob programs the one exposed via I2C for *both* heads, so
168 list_for_each_entry(slave
, &dev
->mode_config
.encoder_list
, head
) {
169 struct dcb_entry
*slave_dcb
= nouveau_encoder(slave
)->dcb
;
171 if (slave_dcb
->type
== OUTPUT_TMDS
&& get_slave_funcs(slave
) &&
172 slave_dcb
->tmdsconf
.slave_addr
== dcb
->tmdsconf
.slave_addr
)
179 static bool nv04_dfp_mode_fixup(struct drm_encoder
*encoder
,
180 struct drm_display_mode
*mode
,
181 struct drm_display_mode
*adjusted_mode
)
183 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
184 struct nouveau_connector
*nv_connector
= nouveau_encoder_connector_get(nv_encoder
);
186 /* For internal panels and gpu scaling on DVI we need the native mode */
187 if (nv_connector
->scaling_mode
!= DRM_MODE_SCALE_NONE
) {
188 if (!nv_connector
->native_mode
)
190 nv_encoder
->mode
= *nv_connector
->native_mode
;
191 adjusted_mode
->clock
= nv_connector
->native_mode
->clock
;
193 nv_encoder
->mode
= *adjusted_mode
;
199 static void nv04_dfp_prepare_sel_clk(struct drm_device
*dev
,
200 struct nouveau_encoder
*nv_encoder
, int head
)
202 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
203 struct nv04_mode_state
*state
= &dev_priv
->mode_reg
;
204 uint32_t bits1618
= nv_encoder
->dcb
->or & OUTPUT_A
? 0x10000 : 0x40000;
206 if (nv_encoder
->dcb
->location
!= DCB_LOC_ON_CHIP
)
209 /* SEL_CLK is only used on the primary ramdac
210 * It toggles spread spectrum PLL output and sets the bindings of PLLs
211 * to heads on digital outputs
214 state
->sel_clk
|= bits1618
;
216 state
->sel_clk
&= ~bits1618
;
219 * bit 0 NVClk spread spectrum on/off
220 * bit 2 MemClk spread spectrum on/off
221 * bit 4 PixClk1 spread spectrum on/off toggle
222 * bit 6 PixClk2 spread spectrum on/off toggle
224 * nv40 (observations from bios behaviour and mmio traces):
225 * bits 4&6 as for nv30
226 * bits 5&7 head dependent as for bits 4&6, but do not appear with 4&6;
227 * maybe a different spread mode
228 * bits 8&10 seen on dual-link dvi outputs, purpose unknown (set by POST scripts)
229 * The logic behind turning spread spectrum on/off in the first place,
230 * and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table
231 * entry has the necessary info)
233 if (nv_encoder
->dcb
->type
== OUTPUT_LVDS
&& dev_priv
->saved_reg
.sel_clk
& 0xf0) {
234 int shift
= (dev_priv
->saved_reg
.sel_clk
& 0x50) ? 0 : 1;
236 state
->sel_clk
&= ~0xf0;
237 state
->sel_clk
|= (head
? 0x40 : 0x10) << shift
;
241 static void nv04_dfp_prepare(struct drm_encoder
*encoder
)
243 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
244 struct drm_encoder_helper_funcs
*helper
= encoder
->helper_private
;
245 struct drm_device
*dev
= encoder
->dev
;
246 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
247 int head
= nouveau_crtc(encoder
->crtc
)->index
;
248 struct nv04_crtc_reg
*crtcstate
= dev_priv
->mode_reg
.crtc_reg
;
249 uint8_t *cr_lcd
= &crtcstate
[head
].CRTC
[NV_CIO_CRE_LCD__INDEX
];
250 uint8_t *cr_lcd_oth
= &crtcstate
[head
^ 1].CRTC
[NV_CIO_CRE_LCD__INDEX
];
252 helper
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
254 nv04_dfp_prepare_sel_clk(dev
, nv_encoder
, head
);
256 /* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f)
257 * at LCD__INDEX which we don't alter
259 if (!(*cr_lcd
& 0x44)) {
262 if (nv_two_heads(dev
)) {
263 if (nv_encoder
->dcb
->location
== DCB_LOC_ON_CHIP
)
264 *cr_lcd
|= head
? 0x0 : 0x8;
266 *cr_lcd
|= (nv_encoder
->dcb
->or << 4) & 0x30;
267 if (nv_encoder
->dcb
->type
== OUTPUT_LVDS
)
269 if ((*cr_lcd
& 0x30) == (*cr_lcd_oth
& 0x30)) {
270 /* avoid being connected to both crtcs */
271 *cr_lcd_oth
&= ~0x30;
272 NVWriteVgaCrtc(dev
, head
^ 1,
273 NV_CIO_CRE_LCD__INDEX
,
282 static void nv04_dfp_mode_set(struct drm_encoder
*encoder
,
283 struct drm_display_mode
*mode
,
284 struct drm_display_mode
*adjusted_mode
)
286 struct drm_device
*dev
= encoder
->dev
;
287 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
288 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(encoder
->crtc
);
289 struct nv04_crtc_reg
*regp
= &dev_priv
->mode_reg
.crtc_reg
[nv_crtc
->index
];
290 struct nv04_crtc_reg
*savep
= &dev_priv
->saved_reg
.crtc_reg
[nv_crtc
->index
];
291 struct nouveau_connector
*nv_connector
= nouveau_crtc_connector_get(nv_crtc
);
292 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
293 struct drm_display_mode
*output_mode
= &nv_encoder
->mode
;
294 uint32_t mode_ratio
, panel_ratio
;
296 NV_DEBUG_KMS(dev
, "Output mode on CRTC %d:\n", nv_crtc
->index
);
297 drm_mode_debug_printmodeline(output_mode
);
299 /* Initialize the FP registers in this CRTC. */
300 regp
->fp_horiz_regs
[FP_DISPLAY_END
] = output_mode
->hdisplay
- 1;
301 regp
->fp_horiz_regs
[FP_TOTAL
] = output_mode
->htotal
- 1;
302 if (!nv_gf4_disp_arch(dev
) ||
303 (output_mode
->hsync_start
- output_mode
->hdisplay
) >=
304 dev_priv
->vbios
.digital_min_front_porch
)
305 regp
->fp_horiz_regs
[FP_CRTC
] = output_mode
->hdisplay
;
307 regp
->fp_horiz_regs
[FP_CRTC
] = output_mode
->hsync_start
- dev_priv
->vbios
.digital_min_front_porch
- 1;
308 regp
->fp_horiz_regs
[FP_SYNC_START
] = output_mode
->hsync_start
- 1;
309 regp
->fp_horiz_regs
[FP_SYNC_END
] = output_mode
->hsync_end
- 1;
310 regp
->fp_horiz_regs
[FP_VALID_START
] = output_mode
->hskew
;
311 regp
->fp_horiz_regs
[FP_VALID_END
] = output_mode
->hdisplay
- 1;
313 regp
->fp_vert_regs
[FP_DISPLAY_END
] = output_mode
->vdisplay
- 1;
314 regp
->fp_vert_regs
[FP_TOTAL
] = output_mode
->vtotal
- 1;
315 regp
->fp_vert_regs
[FP_CRTC
] = output_mode
->vtotal
- 5 - 1;
316 regp
->fp_vert_regs
[FP_SYNC_START
] = output_mode
->vsync_start
- 1;
317 regp
->fp_vert_regs
[FP_SYNC_END
] = output_mode
->vsync_end
- 1;
318 regp
->fp_vert_regs
[FP_VALID_START
] = 0;
319 regp
->fp_vert_regs
[FP_VALID_END
] = output_mode
->vdisplay
- 1;
321 /* bit26: a bit seen on some g7x, no as yet discernable purpose */
322 regp
->fp_control
= NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS
|
323 (savep
->fp_control
& (1 << 26 | NV_PRAMDAC_FP_TG_CONTROL_READ_PROG
));
324 /* Deal with vsync/hsync polarity */
325 /* LVDS screens do set this, but modes with +ve syncs are very rare */
326 if (output_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
327 regp
->fp_control
|= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS
;
328 if (output_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
329 regp
->fp_control
|= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS
;
330 /* panel scaling first, as native would get set otherwise */
331 if (nv_connector
->scaling_mode
== DRM_MODE_SCALE_NONE
||
332 nv_connector
->scaling_mode
== DRM_MODE_SCALE_CENTER
) /* panel handles it */
333 regp
->fp_control
|= NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER
;
334 else if (adjusted_mode
->hdisplay
== output_mode
->hdisplay
&&
335 adjusted_mode
->vdisplay
== output_mode
->vdisplay
) /* native mode */
336 regp
->fp_control
|= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE
;
337 else /* gpu needs to scale */
338 regp
->fp_control
|= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE
;
339 if (nvReadEXTDEV(dev
, NV_PEXTDEV_BOOT_0
) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT
)
340 regp
->fp_control
|= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12
;
341 if (nv_encoder
->dcb
->location
!= DCB_LOC_ON_CHIP
&&
342 output_mode
->clock
> 165000)
343 regp
->fp_control
|= (2 << 24);
344 if (nv_encoder
->dcb
->type
== OUTPUT_LVDS
) {
345 bool duallink
, dummy
;
347 nouveau_bios_parse_lvds_table(dev
, nv_connector
->native_mode
->
348 clock
, &duallink
, &dummy
);
350 regp
->fp_control
|= (8 << 28);
352 if (output_mode
->clock
> 165000)
353 regp
->fp_control
|= (8 << 28);
355 regp
->fp_debug_0
= NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND
|
356 NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND
|
357 NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR
|
358 NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR
|
359 NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED
|
360 NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE
|
361 NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE
;
363 /* We want automatic scaling */
364 regp
->fp_debug_1
= 0;
365 /* This can override HTOTAL and VTOTAL */
366 regp
->fp_debug_2
= 0;
368 /* Use 20.12 fixed point format to avoid floats */
369 mode_ratio
= (1 << 12) * adjusted_mode
->hdisplay
/ adjusted_mode
->vdisplay
;
370 panel_ratio
= (1 << 12) * output_mode
->hdisplay
/ output_mode
->vdisplay
;
371 /* if ratios are equal, SCALE_ASPECT will automatically (and correctly)
372 * get treated the same as SCALE_FULLSCREEN */
373 if (nv_connector
->scaling_mode
== DRM_MODE_SCALE_ASPECT
&&
374 mode_ratio
!= panel_ratio
) {
375 uint32_t diff
, scale
;
376 bool divide_by_2
= nv_gf4_disp_arch(dev
);
378 if (mode_ratio
< panel_ratio
) {
379 /* vertical needs to expand to glass size (automatic)
380 * horizontal needs to be scaled at vertical scale factor
381 * to maintain aspect */
383 scale
= (1 << 12) * adjusted_mode
->vdisplay
/ output_mode
->vdisplay
;
384 regp
->fp_debug_1
= NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE
|
385 XLATE(scale
, divide_by_2
, NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE
);
387 /* restrict area of screen used, horizontally */
388 diff
= output_mode
->hdisplay
-
389 output_mode
->vdisplay
* mode_ratio
/ (1 << 12);
390 regp
->fp_horiz_regs
[FP_VALID_START
] += diff
/ 2;
391 regp
->fp_horiz_regs
[FP_VALID_END
] -= diff
/ 2;
394 if (mode_ratio
> panel_ratio
) {
395 /* horizontal needs to expand to glass size (automatic)
396 * vertical needs to be scaled at horizontal scale factor
397 * to maintain aspect */
399 scale
= (1 << 12) * adjusted_mode
->hdisplay
/ output_mode
->hdisplay
;
400 regp
->fp_debug_1
= NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE
|
401 XLATE(scale
, divide_by_2
, NV_PRAMDAC_FP_DEBUG_1_YSCALE_VALUE
);
403 /* restrict area of screen used, vertically */
404 diff
= output_mode
->vdisplay
-
405 (1 << 12) * output_mode
->hdisplay
/ mode_ratio
;
406 regp
->fp_vert_regs
[FP_VALID_START
] += diff
/ 2;
407 regp
->fp_vert_regs
[FP_VALID_END
] -= diff
/ 2;
411 /* Output property. */
412 if (nv_connector
->use_dithering
) {
413 if (dev_priv
->chipset
== 0x11)
414 regp
->dither
= savep
->dither
| 0x00010000;
417 regp
->dither
= savep
->dither
| 0x00000001;
418 for (i
= 0; i
< 3; i
++) {
419 regp
->dither_regs
[i
] = 0xe4e4e4e4;
420 regp
->dither_regs
[i
+ 3] = 0x44444444;
424 if (dev_priv
->chipset
!= 0x11) {
427 for (i
= 0; i
< 3; i
++) {
428 regp
->dither_regs
[i
] = savep
->dither_regs
[i
];
429 regp
->dither_regs
[i
+ 3] = savep
->dither_regs
[i
+ 3];
432 regp
->dither
= savep
->dither
;
435 regp
->fp_margin_color
= 0;
438 static void nv04_dfp_commit(struct drm_encoder
*encoder
)
440 struct drm_device
*dev
= encoder
->dev
;
441 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
442 struct drm_encoder_helper_funcs
*helper
= encoder
->helper_private
;
443 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(encoder
->crtc
);
444 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
445 struct dcb_entry
*dcbe
= nv_encoder
->dcb
;
446 int head
= nouveau_crtc(encoder
->crtc
)->index
;
448 if (dcbe
->type
== OUTPUT_TMDS
)
449 run_tmds_table(dev
, dcbe
, head
, nv_encoder
->mode
.clock
);
450 else if (dcbe
->type
== OUTPUT_LVDS
)
451 call_lvds_script(dev
, dcbe
, head
, LVDS_RESET
, nv_encoder
->mode
.clock
);
453 /* update fp_control state for any changes made by scripts,
454 * so correct value is written at DPMS on */
455 dev_priv
->mode_reg
.crtc_reg
[head
].fp_control
=
456 NVReadRAMDAC(dev
, head
, NV_PRAMDAC_FP_TG_CONTROL
);
458 /* This could use refinement for flatpanels, but it should work this way */
459 if (dev_priv
->chipset
< 0x44)
460 NVWriteRAMDAC(dev
, 0, NV_PRAMDAC_TEST_CONTROL
+ nv04_dac_output_offset(encoder
), 0xf0000000);
462 NVWriteRAMDAC(dev
, 0, NV_PRAMDAC_TEST_CONTROL
+ nv04_dac_output_offset(encoder
), 0x00100000);
464 /* Init external transmitters */
465 if (get_tmds_slave(encoder
))
466 get_slave_funcs(get_tmds_slave(encoder
))->mode_set(
467 encoder
, &nv_encoder
->mode
, &nv_encoder
->mode
);
469 helper
->dpms(encoder
, DRM_MODE_DPMS_ON
);
471 NV_INFO(dev
, "Output %s is running on CRTC %d using output %c\n",
472 drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder
)->base
),
473 nv_crtc
->index
, '@' + ffs(nv_encoder
->dcb
->or));
476 static inline bool is_powersaving_dpms(int mode
)
478 return (mode
!= DRM_MODE_DPMS_ON
);
481 static void nv04_lvds_dpms(struct drm_encoder
*encoder
, int mode
)
483 struct drm_device
*dev
= encoder
->dev
;
484 struct drm_crtc
*crtc
= encoder
->crtc
;
485 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
486 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
487 bool was_powersaving
= is_powersaving_dpms(nv_encoder
->last_dpms
);
489 if (nv_encoder
->last_dpms
== mode
)
491 nv_encoder
->last_dpms
= mode
;
493 NV_INFO(dev
, "Setting dpms mode %d on lvds encoder (output %d)\n",
494 mode
, nv_encoder
->dcb
->index
);
496 if (was_powersaving
&& is_powersaving_dpms(mode
))
499 if (nv_encoder
->dcb
->lvdsconf
.use_power_scripts
) {
500 struct nouveau_connector
*nv_connector
= nouveau_encoder_connector_get(nv_encoder
);
502 /* when removing an output, crtc may not be set, but PANEL_OFF
505 int head
= crtc
? nouveau_crtc(crtc
)->index
:
506 nv04_dfp_get_bound_head(dev
, nv_encoder
->dcb
);
508 if (mode
== DRM_MODE_DPMS_ON
) {
509 if (!nv_connector
->native_mode
) {
510 NV_ERROR(dev
, "Not turning on LVDS without native mode\n");
513 call_lvds_script(dev
, nv_encoder
->dcb
, head
,
514 LVDS_PANEL_ON
, nv_connector
->native_mode
->clock
);
516 /* pxclk of 0 is fine for PANEL_OFF, and for a
517 * disconnected LVDS encoder there is no native_mode
519 call_lvds_script(dev
, nv_encoder
->dcb
, head
,
523 nv04_dfp_update_fp_control(encoder
, mode
);
525 if (mode
== DRM_MODE_DPMS_ON
)
526 nv04_dfp_prepare_sel_clk(dev
, nv_encoder
, nouveau_crtc(crtc
)->index
);
528 dev_priv
->mode_reg
.sel_clk
= NVReadRAMDAC(dev
, 0, NV_PRAMDAC_SEL_CLK
);
529 dev_priv
->mode_reg
.sel_clk
&= ~0xf0;
531 NVWriteRAMDAC(dev
, 0, NV_PRAMDAC_SEL_CLK
, dev_priv
->mode_reg
.sel_clk
);
534 static void nv04_tmds_dpms(struct drm_encoder
*encoder
, int mode
)
536 struct drm_device
*dev
= encoder
->dev
;
537 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
539 if (nv_encoder
->last_dpms
== mode
)
541 nv_encoder
->last_dpms
= mode
;
543 NV_INFO(dev
, "Setting dpms mode %d on tmds encoder (output %d)\n",
544 mode
, nv_encoder
->dcb
->index
);
546 nv04_dfp_update_fp_control(encoder
, mode
);
549 static void nv04_dfp_save(struct drm_encoder
*encoder
)
551 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
552 struct drm_device
*dev
= encoder
->dev
;
554 if (nv_two_heads(dev
))
555 nv_encoder
->restore
.head
=
556 nv04_dfp_get_bound_head(dev
, nv_encoder
->dcb
);
559 static void nv04_dfp_restore(struct drm_encoder
*encoder
)
561 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
562 struct drm_device
*dev
= encoder
->dev
;
563 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
564 int head
= nv_encoder
->restore
.head
;
566 if (nv_encoder
->dcb
->type
== OUTPUT_LVDS
) {
567 struct drm_display_mode
*native_mode
= nouveau_encoder_connector_get(nv_encoder
)->native_mode
;
569 call_lvds_script(dev
, nv_encoder
->dcb
, head
, LVDS_PANEL_ON
,
572 NV_ERROR(dev
, "Not restoring LVDS without native mode\n");
574 } else if (nv_encoder
->dcb
->type
== OUTPUT_TMDS
) {
575 int clock
= nouveau_hw_pllvals_to_clk
576 (&dev_priv
->saved_reg
.crtc_reg
[head
].pllvals
);
578 run_tmds_table(dev
, nv_encoder
->dcb
, head
, clock
);
581 nv_encoder
->last_dpms
= NV_DPMS_CLEARED
;
584 static void nv04_dfp_destroy(struct drm_encoder
*encoder
)
586 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
588 NV_DEBUG_KMS(encoder
->dev
, "\n");
590 if (get_slave_funcs(encoder
))
591 get_slave_funcs(encoder
)->destroy(encoder
);
593 drm_encoder_cleanup(encoder
);
597 static void nv04_tmds_slave_init(struct drm_encoder
*encoder
)
599 struct drm_device
*dev
= encoder
->dev
;
600 struct dcb_entry
*dcb
= nouveau_encoder(encoder
)->dcb
;
601 struct nouveau_i2c_chan
*i2c
= nouveau_i2c_find(dev
, 2);
602 struct i2c_board_info info
[] = {
605 .addr
= (dcb
->tmdsconf
.slave_addr
== 0x7 ? 0x3a : 0x38),
606 .platform_data
= &(struct sil164_encoder_params
) {
607 SIL164_INPUT_EDGE_RISING
614 if (!nv_gf4_disp_arch(dev
) || !i2c
||
615 get_tmds_slave(encoder
))
618 type
= nouveau_i2c_identify(dev
, "TMDS transmitter", info
, 2);
622 drm_i2c_encoder_init(dev
, to_encoder_slave(encoder
),
623 &i2c
->adapter
, &info
[type
]);
626 static const struct drm_encoder_helper_funcs nv04_lvds_helper_funcs
= {
627 .dpms
= nv04_lvds_dpms
,
628 .save
= nv04_dfp_save
,
629 .restore
= nv04_dfp_restore
,
630 .mode_fixup
= nv04_dfp_mode_fixup
,
631 .prepare
= nv04_dfp_prepare
,
632 .commit
= nv04_dfp_commit
,
633 .mode_set
= nv04_dfp_mode_set
,
637 static const struct drm_encoder_helper_funcs nv04_tmds_helper_funcs
= {
638 .dpms
= nv04_tmds_dpms
,
639 .save
= nv04_dfp_save
,
640 .restore
= nv04_dfp_restore
,
641 .mode_fixup
= nv04_dfp_mode_fixup
,
642 .prepare
= nv04_dfp_prepare
,
643 .commit
= nv04_dfp_commit
,
644 .mode_set
= nv04_dfp_mode_set
,
648 static const struct drm_encoder_funcs nv04_dfp_funcs
= {
649 .destroy
= nv04_dfp_destroy
,
653 nv04_dfp_create(struct drm_connector
*connector
, struct dcb_entry
*entry
)
655 const struct drm_encoder_helper_funcs
*helper
;
656 struct nouveau_encoder
*nv_encoder
= NULL
;
657 struct drm_encoder
*encoder
;
660 switch (entry
->type
) {
662 type
= DRM_MODE_ENCODER_TMDS
;
663 helper
= &nv04_tmds_helper_funcs
;
666 type
= DRM_MODE_ENCODER_LVDS
;
667 helper
= &nv04_lvds_helper_funcs
;
673 nv_encoder
= kzalloc(sizeof(*nv_encoder
), GFP_KERNEL
);
677 encoder
= to_drm_encoder(nv_encoder
);
679 nv_encoder
->dcb
= entry
;
680 nv_encoder
->or = ffs(entry
->or) - 1;
682 drm_encoder_init(connector
->dev
, encoder
, &nv04_dfp_funcs
, type
);
683 drm_encoder_helper_add(encoder
, helper
);
685 encoder
->possible_crtcs
= entry
->heads
;
686 encoder
->possible_clones
= 0;
688 if (entry
->type
== OUTPUT_TMDS
&&
689 entry
->location
!= DCB_LOC_ON_CHIP
)
690 nv04_tmds_slave_init(encoder
);
692 drm_mode_connector_attach_encoder(connector
, encoder
);